Thermal Challenges in Nanoscale Devices and Packaging http:nanoheat.stanford.edu Silicon Nanoelectronics and Beyond SRC/Intel/NNI Workshop, October 29-30, 2003 Eric Pop1 Kenneth Goodson2 and Robert Dutton1 Dept. of Electrical1 and Mechanical2 Engineering Stanford University E.Pop, Stanford U. SRC SiNB Workshop, 2003 Transistor Thermal Challenges 0.8 µm 0.35 µm 0.13 µm 0.05 µm AMD Intel 100 PowerPC Trend 10 AMD Intel Nuclear Reactor Power PC 100 Trend Hot Plate 10 F.Labonte 1 1 1990 Rocket Nozzle 1000 Power Density (W/cm2) Transistor Count (millions) 1000 1994 1998 2002 2006 2010 1990 1994 1998 2002 2006 2010 Confined Geometries, Novel Materials Electrostatic Discharge (ESD) 1 µm IBM Siemens E.Pop, Stanford U. SRC SiNB Workshop, 2003 Packaging Work and Challenges Heat sinks are 3000x larger & heavier than the chip They crowd away power deliver components Unable to address local chip-level hotspots Mixed signal integration competes for I/O area Grand Challenge – power delivery & heat removal Microchannel cooling of chip-level hotspots Solid-state electroosmotic pumping Thermofluidic CAD Microprocessor with Integrated Power Module: (Stanford - MARCO) Photonic I/O RF conventional heat sink Integrated MEMS Sensing Fluidic I/O Electrical Connections E.Pop, Stanford U. Microprocessor Fluidic Cooling SRC SiNB Workshop, 2003 Sub-Continuum Heat Transport Macroscale (D » Λ) ∂T = ∇ ⋅ (k s ∇ T ) + Q ′′′ Cs Ox Me tsi ∂t D Nanoscale (D < Λ) ′′ − e′′ eeq ∂e′′ r + v ⋅ ∇e′′ = + Q′′′ ∂t τ phon Heat transfer issues Bulk Devices E.Pop, Stanford U. optical-acoustic small heat source impurity scattering boundary scattering boundary thermal res. Λ ~ 200 nm Ox Thin Body Devices Si SRC SiNB Workshop, 2003 Nanodevice Thermal Projections Extract device self-heating from comprehensive electron-phonon Monte Carlo Pop, Banerjee, Dutton, Goodson, IEDM 2001 ∆T Increase (K) Power Q’ (µW/µm) Channel Length L (nm) Bulk Devices optical-acoustic bottleneck small heat source peak drain T estimate E.Pop, Stanford U. Drain T Rise (K) Pop, Dutton, Goodson, IEDM 2003 Channel Length L (nm) Thin Body (FD-SOI) boundary scattering thin, doped layers boundary thermal resistance role of raised source & drain SRC SiNB Workshop, 2003 URL: E.Pop, Stanford U. http://nanoheat.stanford.edu SRC SiNB Workshop, 2003 Summary Device dimensions ↓↓ , kth ↓ , power (I.V) ↓ Result Æ power density and T ↑ Fundamental aspects of nano-heating Complex codes fast enough for device design Side-effect Æ compact, physical models Nanoscale temperature rise is significant Must learn electro-thermal device scaling We CAN improve thermal device design Need research on thin film phonon dispersion New materials & boundary thermal properties g Strong ties with industry, information sharing f E.Pop, Stanford U. SRC SiNB Workshop, 2003 Computed Phonon Generation Optical optical acoustic Acoustic Near-full band MC complexity for analytic-band MC speed – towards a device designer’s MC? E.Pop, Stanford U. SRC SiNB Workshop, 2003 Confined Electrons and Phonons 2-D Electrons 2-D Phonons tsi Electro-thermal transport in ultra-thin silicon films (tsi ~ 5 nm): role of electron and phonon confinement E.Pop, Stanford U. SRC SiNB Workshop, 2003 Overview Device dimensions scale quicker than power (I.V) Result Æ power density and T ↑ Work on fundamental aspects of nano-heating Electron Monte Carlo Æ heat generation rates Phonon Molecular Dynamics Æ scat./transport Finite volume methods for BTE Goal: electro-thermal simulator Compact, physical models for devices Goal: trends, circuit simulation Apply to bulk and SOI/FinFETs Goal: improve device design E.Pop, Stanford U. g f SRC SiNB Workshop, 2003
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