Power Dissipation in Nanoscale
CMOS and Carbon Nanotubes
Eric Pop
Dept. of Electrical & Computer Engineering
http://poplab.ece.uiuc.edu
E. Pop
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Power and Heat: The Big Picture
2
(W/cm
Density
Power
(W/cm 2))
Density
Power
1000
100
AMD
Intel
Power PC
Trend
Rocket
Nozzle
Nuclear
Reactor
Hot
Plate
10
1
1990
1994
1998
2002
2006
2010
Sun surface? 6000 W/cm2
http://phys.ncku.edu.tw/~htsu/humor/fry_egg.html
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Thermal Management Challenges
•
•
IBM S/390 refrigeration
Grid computing: power plants co-located near computer farms
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Power and Heat: The Tiny Picture
Suspended
On substrate
Carbon nanotubes burn at high enough applied voltage
(they also emit light when they get this hot)
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Power, Thermal Management Methods
System Level
 Active Microchannel Cooling (Cooligy)
Is there a bottom-up
IBM
approach?
Circuit + Software Level
 active power management
(turn parts of circuit on/off)
From the device and
materials level?
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Chip-Level Thermal Network
Intel Itanium
Cinterconnect
Top view
Hottest spots > 300 W/cm2
Tinterconnect
Ctransistor
Rdielectric
Ttransistors
Cchip
Cross-section
8 metal levels + ILD
Rspreading
Intel 65 nm
Tchip
Cheat sink
Rchip
Theat sink
chip carrier
Si chip
heat spreader
fin array heat sink
Rconvection
fan
Tcoolant
Transistor < 100 nm
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Thermal and Electrical Resistance
P = I2 × R
∆T = P × RTH
∆V=I×R
R = f(∆T)
Fourier’s Law (1822)
Ohm’s Law (1827)
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Device-Level Thermal Challenges
• Small geometry
Device Level:
Confined Geometries, Novel Materials
– High power density (device-level
hot spot)
– Higher surface-to-volume ratio, i.e.
higher role of thermal interfaces
between materials
• Lower thermal conductivity
• Lowering power (but can it
ever be low enough?!)
• Device-level thermal design
(phonon engineering)
Material
k (W/m/K)
Si
148
Ge
60
Silicides
40
Si (10 nm)
13
SiO2
1.4
Source: E. Pop (Proc. IEEE 2006)
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Thermal Resistance of a Single Device
Single-wall
nanotube SWNT
100000
High thermal resistances:
• SWNT due to small thermal
conductance (very small d ~ 2 nm)
10000
RTH (K/mW)
1000
100
• Others due to low thermal
conductivity, decreasing dimensions,
increased role of interfaces
GST
Phase-change
Memory (PCM)
Silicon-onInsulator FET
SiO2
10
Cu
Cu Via
Power input also matters:
L ~ channel length
• SWNT
~ diameter
0.01-0.1 mW
or via
1
Si
0.1
0.01
0.1
Bulk FET
L (mm)
• Others ~ 0.1-1 mW
1
10
Data: Mautry (1990), Bunyan (1992), Su (1994), Lee (1995), Jenkins (1995), Tenbroek (1996),
Jin (2001), Reyboz (2004), Javey (2004), Seidel (2004), Pop (2004-6), Maune (2006).
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Modeling Device Thermal Resistance
100000
• Steady-state models
RTH (K/mW)
10000
– Lumped: Mautry (1990), Goodson-Su
(1994-5), Pop (2004), Darwish (2005)
1000
100
SOI FET
10
1
– Finite-Element models
0.1
0.01
Bulk FET
0.1
L (mm)
1
10
D
L
tSi
W
tBOX
Bulk Si FET
RTH 
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1

2kSi D 4kSi LW
SOI FET
RTH 
1
2W
1/ 2
 tBOX 


 k BOX kSi tSi 
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A More Detailed Look
1. Monte Carlo heat generation
in bulk and strained silicon
Gate
Buried oxide
2. Self-heating in thin-body
SOI and GOI devices
Silicon substrate
3. Self-heating and lessons
from carbon nanotubes
nanotube on
substrate
2 μm
suspended
over trench
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Quick Recap of Phonons
Graphene Phonons [100]
200 meV
CO2 molecule
vibrations
transverse
small k
transverse
max k=2p/a
Frequency ω (cm-1)
160 meV
100 meV
silicon
26 meV =
300 K
u(r, t )  A exp[i(k  r  it )]
k
•
•
•
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Phonons = lattice vibration waves
Phonons are responsible for heat transport in semiconductors
“Hot phonons” = highly occupied modes above room temperature
12
Details Picture of Joule Heating
High Electric
Field
Hot Electrons
(Energy E)
E > 50 meV
t ~ 0.1ps
60
optical
(vop ~ 1000 m/s)
Optical Phonons
t ~ 1 ms – 1 s
(vac ~ 9000 m/s)
40
30
Freq (Hz)
t ~ 5 ps
Acoustic Phonons
50
20
acoustic
Heat Conduction
to Package
Energy (meV)
E < 50 meV
t ~ 0.1ps
Note: optical phonon energy
in CNTs (180 meV) about 3x
higher than in Si (60 meV)
10
Wave vector qa/2p
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2D Thin-Body SOI Simulation
E. Pop et al., Proc. IEEE, 2006
Mesh
Study of device matching
LG = 18 nm ITRS specs
E-field
if W/L = 4 then Nelec ~ 2500 total!
Current
Monte Carlo (MONET)
Notice heat is dissipated
in device drain
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Heat Generation in Quasi-Ballistic Devices
E. Pop et al., SISPAD 2005
L=500 nm
100 nm
20 nm
Heat Gen. (eV/cm3/s)
Monte Carlo
Medici
source
channel
Error: DL/L = 0.10
DL
drain
source
channel
Medici
drain
source
DL/L = 0.38
Monte Carlo
channel
drain
DL/L = 0.80
• Monte Carlo vs. Medici (drift-diffusion commercial code):
– “Long” (500 nm) device: same current, potential, nearly identical
– Importance of non-local transport in short devices
– Heat dissipation in DRAIN (optical, acoustic) of shortest devices
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Phonon Generation Spectrum in Silicon
E. Pop et al., Appl. Phys. Lett. 86, 082101 (2005)
• Complete spectral information on phonon generation rates
• Note: effect of scattering selection rules (less f-scat in strained Si)
• Note: same heat generation at high-field in Si and strained Si
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What About Device Design?
Monte Carlo
Analysis
Thermal
Conductivity
Design and
Scaling
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Thin Film Thermal Conductivity
E. Pop et al., Proc. IEDM 2003-2004
80
Bulk Si ~ 150, Ge ~ 60 W/m/K
70
Intel DST/SOI Transistor
k (W/m/K)
60
Thin Si
50
Thin Ge
40
30
20
Si NW
10
SiGe NW
0
0
50
d (nm)
100
150
•
Phonon boundary scattering and confinement
•
Strong decrease in thin film or nanowire thermal conductivity (k), up to
10-100x lower than bulk
•
How does this affect nanometer scale devices?
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Boundary Thermal Resistance
E. Pop et al., Proc. IEEE (2006)
Lyeo, Cahill
(2006)
Intel DST/SOI Transistor
Al/SiO2/Si
GST/ZnS/SiO2
• Thermal interface resistance at solid-solid material interfaces
• Caused by phonon dispersion mismatch b/w materials (~Cv/4), electronphonon energy conversion at boundary, roughness at boundary
• Approximately equivalent to ~10-100 nm additional SiO2
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Self-Consistent Electro-Thermal Model
E. Pop et al., Proc. IEDM 2004
P=VI
Cex  2sw ln 1  Lex / tox  / p
Rxd  Rex  RQ  Rsd  Rco
(RQ due to heat source position)
R
P=VI
Geometry
C
E. Pop
T=PR
t=CV/I
T 1.4
I
I ~ m  Vdd  Vt 
n
 0.7 mV/K
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SOI/GOI Device Design Optimization
E. Pop et al., Proc. IEDM 2004
Intrinsic Delay (ps)
CV/I
tSD
tfilm
tSD = ntfilm
n = 1... 5
Lex
Gate Length Lg (nm)
• Larger Source/Drain (S/D) volume will help heat spreading in drain
• BUT… no improvement for S/D thickness tSD > 3-4 x tfilm = Effect of
parasitic side-wall capacitance on Intrinsic Delay
• Optimized, “well-behaved” GOI devices 30% faster than optimized SOI
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Transient Device Thermal Modeling
100 nm
Silicon
72 nm
Silicon
Dioxide
Heat Generation
315 nm
1633 nm
0
20
40
60
80
70
Temperature Swings
60
TTM (ton=2.52ps)
50
Fourier (ton=5.04ps)
TTM (ton=5.04ps)
40
30
20
0
Fourier (ton=2.52ps)
50
100
150
Time elapsed (ps)
100
ITRS 2014
device specs
9
200
8
(TL)
Relative Leakage
900 nm
TL in center of hotspot (K)
Z.-Y. Ong and E. Pop, submitted (2008)
7
5
Fourier (Pulsed)
Fourier (Steady)
4
3
2
0
•
TTM (Steady)
TTM (Pulsed)
6
Compact thermal device model including:
50
100
150
Time elapsed (ps)
200
– Non-equilibrium heat generation from Monte Carlo
– Phonon relaxation parameter-matched to Boltzmann Transport Eq.
•
•
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Capture spatial and temporal temperature excursions
What is the effect on leakage & reliability?
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Onto Carbon Nanotubes…
Single-wall
nanotube SWNT
100000
RTH (K/mW)
10000
1000
100
Silicon-onInsulator FET
SiO2
10
1
0.1
0.01
0.1
L (mm)
1
10
Data: Mautry (1990), Bunyan (1992), Su (1994), Lee (1995), Jenkins (1995), Tenbroek
(1996), Jin (2001), Reyboz (2004), Javey (2004), Seidel (2004), Pop (2004-6), Maune (2006).
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Where Carbon Nanotubes Fit In
Allotropes of Carbon:
Graphite (pencil lead)
Diamond
Buckyball
(C60)
Amorphous
(soot)
Single-Walled Nanotube
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Carbon Nanotubes for Electronics
• Carbon nanotube = rolled up graphene sheet
• Great electrical properties
– Semiconducting  Transistors
– Metallic  Interconnects
d ~ 1-3 nm
– Electrical Conductivity σ ≈ 100 x σCu
– Thermal Conductivity k ≈ kdiamond ≈ 5 x kCu
HfO2
• Nanotube challenges:
top gate (Al)
S (Pd)
– Reproducible growth
– Control of electrical and thermal properties
– Going “from one to a billion”
CNT
D (Pd)
SiO2
back gate
(p++ Si)
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Nanotube Back-of-the-Envelope Estimates
DT
• Typical L ~ 2 mm, d ~ 2 nm
• On insulating solid substrate
Pt
• Heat dissipated into substrate
– Moderate power ~ 10 mW/mm
– Peak DT ~ 60 K
g
SiO2
DT
• Thermal conductivity k ~ 3000 W/m/K
• Freely suspended nanotube
k
Pt
• Heat dissipated along tube length
– Moderate power ~ 10 mW (10 mA @ 1 V)
– Peak DT ~ 400 K!
E. Pop
SiO2
26
Transport in Suspended Nanotubes
E. Pop et al., Phys. Rev. Lett. 95, 155505 (2005)
nanotube on
substrate
2 μm
nanotube
Pt
suspended
over trench
Pt gate
Si3N4
SiO2
• Observation: significant current degradation and negative
differential conductance at high bias in suspended tubes
• Question: Why? Answer: Tube gets HOT (how?)
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Transport Model Including Hot Phonons
E. Pop et al., Phys. Rev. Lett. 95, 155505 (2005)
I2(R-Rc)
Non-equilibrium OP:
TOP
TOP  TAC   (TAC  T0 )
ROP
TAC = TL
Heat transfer via AC:
RTH
A(kT )  I 2 ( R  RC ) / L  0
T0
Phonon Temperature (K)
1000
I2(R-RC)
900
800
Landauer electrical resistance
700
TAC = TL
600
R(V , T )  RC 
Optical TOP
500
h  L  eff (V , T ) 


4q 2  eff (V , T ) 
Include OP absorption:
400
Acoustic TAC
300
0
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oxidation T
TOP
0.2
0.4
0.6
V (V)
0.8
1
1.2
 1
1
1

1
eff  



 AC OP ,ems OP ,abs 
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Extracting SWNT Thermal Conductivity
E. Pop et al., Nano Letters 6, 96 (2006)
Yu et al. (NL’05)
This work
• “Inverse” numerical extraction of k from the high bias (V > 0.3 V) tail
• Comparison to data from 100-300 K of UT Austin group (C. Yu, NL Sep’05)
• Result: first “complete” picture of SWNT thermal conductivity from 100 – 800 K
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Light Emission from Metallic SWNTs
Wavelength (nm)
900
750
600
3
S
Vds = 1.4 V
suspended
2
D
1 Vds = 7 V
on substrate
0
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1.4
1.6 1.8 2.0
Energy (eV)
0
-5
~ σT4
drain
0
1
2
γ (a.u.)
Polarization
1
γ (a.u.)
γ (a.u.)
– Comes from center, highly polarized
– Quasi-metallic = small band gaps
– Emitted photons at higher energy than
applied bias (high energy tail)
source
5
trench
• Joule-heated tubes emit light:
Distance (mm)
D. Mann et al., Nature Nano 2, 33 (2007)
S
2.2
0
0
90
angle
30
Return to SWNTs On Substrates
E. Pop et al., Proc IEDM 2005; Proc IEEE 2006
• SWNT on insulating solid substrate
• Heat dissipated into substrate rather than along tube length
• Q: How do I model heat loss into substrate?
• [A: need some gauge of the tube temperature]
DT
Pt
g
SiO2
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Nanotube Temperature Gauge
Pt
g
SiO2
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Nanotube Temperature Gauge
• Doesn’t exist
• But… oxidation (burning) temperature is known
O2
TBD ~ 600 oC
Suspended
On substrate
Pt
g
SiO2
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Breakdown of SWNTs in Air (Oxygen)
A(kT )  p' g (T  T0 )  0
At breakdown:
p' I BDVBD / L
VBD  gLTBD  T0  / I BD
E. Pop, Proc. IEDM (2005)
A. Javey, PRL 92, 106804 (2004)
•
Data shows SWNTs exposed to air break down by oxidation at
500 < TBD < 700 oC (800–1000 K)
•
Joule breakdown voltage data shows VBD scales with L in air
•
Supports cooling mechanism along the length, into the substrate
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Electrical Breakdown of SWNTs
E. Pop et al., J. Appl. Phys. 101, 093710 (2007)
d
L
Pt
g
tOX
SiO2
VBD
(a)
•
•
•
•
tSI
Si
(b)
SWNT exposed to air from the top
Sweep voltage low to high
Temperature peaks in the middle
When Tmax = TBD  V = VBD and PBD = IBDVBD
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Electrical Breakdown of SWNTs
E. Pop et al., J. Appl. Phys. 101, 093710 (2007)
900
Tmax
T (K)
700
VBD
500
300
•
•
•
•
E. Pop
ΔTC
-1
0
X (m m)
1
2
SWNT exposed to air from the top
Sweep voltage low to high
Temperature peaks in the middle
When Tmax = TBD  V = VBD and PBD = IBDVBD
36
Breakdown Data from Literature
E. Pop, DRC (2007)
PBD  gLTBD  T0 
1
PBD (mW)
0.2
Stanford
Caltech
Infineon
1.2
0.8
Zoom into L < 2 mm
"short"
0.15
PBD = 88.8L
R2 = 0.87
0.6
cosh( L / 2 LH )  gLH R T sinh( L / 2 LH )
cosh( L / 2 LH )  gLH R T sinh( L / 2 LH )  1
"long"
0.1
0.4
0.05
0.2
0
0
0
2
4
L (µm)
6
0
8
0.5
1
L (µm)
1.5
2
• “Short” vs. “long” breakdown: Compared to thermal “healing” length ~ 0.2 µm
• Note: There is a minimum breakdown power ~ 0.05 mW
• We can learn a lot more about electrical and thermal properties
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SWNT Compact Model Up to Breakdown
E. Pop et al., J. Appl. Phys. 101, 093710 (2007)
Data
Model
Understanding transport
in a 3 mm metallic SWNT
up to breakdown:
Tmax ~ 600 oC = 873 K
Vmax ~ 15 V
• Thermal “healing length” along SWNT ~ 0.2 mm
• Current saturation ~ 20 mA in long tubes (> 1 mm) due to self-heating
• Self-heating not significant when p’ < 5 mW/mm (design goal?)
• More current in short nanotubes = less heating?
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Summary
•
Small device dimensions, high local
power densities
SWNT
•
Increased device thermal resistance with
decreasing dimensions
SOI FET
•
Physics-based models to capture:
100000
RTH (K/mW)
10000
1000
100
PCM
10
1
0.1
0.01
– Size effects
Bulk FET
0.1
L (mm)
– Phonon non-equilibrium
1
– Transient temperature effects
10
•
Opportunity for “bottom-up” thermal
device and materials design
http://poplab.ece.uiuc.edu
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