Y86 Instruction Set
CS:APP Chapter 4
Computer Architecture
Sequential
Implementation
Randal E. Bryant
Carnegie Mellon University
http://csapp.cs.cmu.edu
!
!
!
A
nop
0
0
halt
1
0
rrmovl rA, rB
2
0 rA rB
irmovl V, rB
3
0
8 rB
V
rmmovl rA, D(rB)
4
0 rA rB
D
mrmovl D(rB), rA
5
0 rA rB
D
OPl rA, rB
6
fn rA rB
jXX Dest
7
fn
Dest
call Dest
8
0
Dest
ret
9
0
pushl rA
A
0 rA 8
B
0 rA 8
=
3
4
5
addl
6
0
subl
6
1
andl
6
2
xorl
6
3
jmp
7
0
jle
7
1
jl
7
2
je
7
3
jne
7
4
jge
7
5
7
6
CS:APP
!
Very simple hardware description language
!
Can only express limited aspects of hardware operation
" Parts we want to explore and modify
0
Data Types
MUX
1
Operate on data and implement
control
2
Hardware Control Language
A
L
U
Compute Boolean functions of
inputs
B
Continuously respond to input
changes
1
jg
fun
Combinational Logic
0
popl rA
–2–
CS:APP
Building Blocks
Byte
!
bool: Boolean
!
int: words
" a, b, c, …
" A, B, C, …
Storage Elements
!
!
–3–
Store bits
Addressable memories
!
Non-addressable registers
!
Loaded only as clock rises
" Does not specify word size---bytes, 32-bit words, …
valA
srcA
A
valB
srcB
Statements
valW
Register
Register
file
file
B
W
! bool a = bool-expr ;
dstW
! int A = int-expr ;
Clock
Clock
CS:APP
–4–
CS:APP
SEQ Hardware
Structure
HCL Operations
!
Logic Operations
" a && b, a || b, !a
!
!
Program counter register (PC)
!
!
Condition code register (CC)
Register File
!
Memories
Word Comparisons
" Access same memory space
" A == B, A != B, A < B, A <= B, A >= B, A > B
!
valM
Data
Data
memory
memory
Memory
Addr, Data
valE
Execute
Bch
CC
CC
ALU
ALU
aluA, aluB
" Data: for reading/writing program
data
Set Membership
" Instruction: for reading
" A in { B, C, D }
valA, valB
instructions
» Same as A == B || A == C || A == D
Read instruction at address
specified by PC
" [ a : A; b : B; c : C ]
!
" Evaluate test expressions a, b, c, … in sequence
!
Process through stages
Update program counter
icode ifun
rA , rB
valC
CS:APP
B
valP
,
Fetch
" Return word expression A, B, C, … for first successful test
–5–
A
Register
RegisterM
file
file
E
!
Case expressions
srcA, srcB
dstA, dstB
Decode
Instruction Flow
Word Expressions
!
valE, valM
Write back
State
Classify by type of value returned
Boolean Expressions
!
newPC
PC
Instruction
Instruction
memory
memory
PC
PC
increment
increment
PC
CS:APP
–6–
newPC
SEQ Stages
PC
Instruction Decoding
valE, valM
Write back
valM
Optional
Fetch
!
Read instruction from instruction
memory
Data
Data
memory
memory
Memory
Addr, Data
5
Decode
!
!
Execute
Bch
CC
CC
Compute value or address
Read or write data
valA, valB
B
Instruction Format
valP
,
Fetch
!
A
Register
RegisterM
file
file
E
icode ifun
rA , rB
valC
Write program registers
PC
srcA, srcB
dstA, dstB
Decode
Write Back
!
D
icode
ifun
rA
rB
valC
ALU
ALU
aluA, aluB
Memory
!
0 rA rB
valE
Read program registers
Execute
Optional
Instruction
Instruction
memory
memory
PC
PC
increment
increment
Update program counter
!
Instruction byte
icode:ifun
!
Optional register byte
rA:rB
!
Optional constant word valC
PC
–7–
CS:APP
–8–
CS:APP
Executing Arith./Logical Operation
OPl rA, rB
Fetch
!
Read 2 bytes
!
!
Fetch
Do nothing
Write back
Read operand registers
Execute
!
6 fn rA rB
Memory
Decode
!
!
Perform operation
Set condition codes
!
–9–
Executing rmmovl
Decode
!
Read operand registers
Execute
!
Compute effective address
Write back result
PC ! valP
Update PC
!
Formulate instruction execution as sequence of simple
steps
!
Use same general form for all instructions
CS:APP
– 10 –
D
Fetch
Memory
Read 6 bytes
R[rB] ! valE
back
PC update
Stage Computation: rmmovl
rmmovl rA, D(rB) 4 0 rA rB
Fetch
Set CC
Execute
Increment PC by 2
!
Write to memory
Write back
!
Decode
Do nothing
Execute
PC Update
!
Memory
Write
Increment PC by 6
back
PC update
!
– 11 –
valP ! PC+2
valA ! R[rA]
valB ! R[rB]
valE ! valB OP valA
Read instruction byte
Read register byte
Memory
Write
Decode
PC Update
OPl rA, rB
icode:ifun ! M1[PC]
rA:rB ! M1[PC+1]
Compute next PC
Read operand A
Read operand B
Perform ALU operation
Set condition code register
Update register
CS:APP
!
Stage Computation: Arith/Log. Ops
CS:APP
– 12 –
rmmovl rA, D(rB)
icode:ifun ! M1[PC]
rA:rB ! M1[PC+1]
valC ! M4[PC+2]
valP ! PC+6
valA ! R[rA]
valB ! R[rB]
valE ! valB + valC
Read instruction byte
Read register byte
Read displacement D
Compute next PC
Read operand A
Read operand B
Compute effective address
M4[valE] ! valA
Write value to memory
PC ! valP
Update PC
Use ALU for address computation
CS:APP
Executing popl
popl rA
Stage Computation: popl
b 0 rA 8
Fetch
!
Read 2 bytes
!
Decode
!
valP ! PC+2
Read from old stack pointer
Write back
Read stack pointer
Execute
!
Fetch
Memory
Increment stack pointer by 4
Decode
!
Update stack pointer
!
Write result to register
Execute
Memory
Write
PC Update
!
popl rA
icode:ifun ! M1[PC]
rA:rB ! M1[PC+1]
Increment PC by 2
back
PC update
valA ! R[%esp]
valB ! R [%esp]
valE ! valB + 4
valM ! M4[valA]
R[%esp] ! valE
R[rA] ! valM
PC ! valP
Read instruction byte
Read register byte
Compute next PC
Read stack pointer
Read stack pointer
Increment stack pointer
Read from stack
Update stack pointer
Write back result
Update PC
!
Use ALU to increment stack pointer
!
Must update two registers
" Popped value
CS:APP
– 13 –
Executing Jumps
jXX Dest
7 fn
fall thru:
XX XX
target:
" New stack pointer
– 14 –
CS:APP
Stage Computation: Jumps
Dest
Not taken
Fetch
XX XX
Taken
jXX Dest
icode:ifun ! M1[PC]
Read instruction byte
valC ! M4[PC+1]
valP ! PC+5
Read destination address
Fall through address
Bch ! Cond(CC,ifun)
Take branch?
PC ! Bch ? valC : valP
Update PC
Decode
Fetch
Memory
!
Read 5 bytes
!
Increment PC by 5
Decode
!
Do nothing
Execute
!
– 15 –
Determine whether to take
branch based on jump
condition and condition
codes
!
Execute
Do nothing
Memory
Write
Write back
!
Do nothing
back
PC update
PC Update
!
Set PC to Dest if branch
taken or to incremented PC
if not branch
CS:APP
– 16 –
!
Compute both addresses
!
Choose based on setting of condition codes and branch
condition
CS:APP
Executing call
Stage Computation: call
call Dest
return:
target:
8 0
call Dest
icode:ifun ! M1[PC]
Read instruction byte
valC ! M4[PC+1]
valP ! PC+5
Read destination address
Compute return point
valB ! R[%esp]
valE ! valB + –4
Read stack pointer
Decrement stack pointer
Memory
Write
M4[valE] ! valP
R[%esp] ! valE
Write return value on stack
Update stack pointer
back
PC update
PC ! valC
Set PC to destination
Dest
XX XX
Fetch
XX XX
Decode
Fetch
!
Read 5 bytes
!
Increment PC by 5
!
!
Read stack pointer
Update stack pointer
PC Update
Execute
!
Write incremented PC to
new value of stack pointer
Write back
Decode
!
Execute
Memory
Decrement stack pointer by
4
!
Set PC to Dest
CS:APP
– 17 –
Executing ret
ret
!
Use ALU to decrement stack pointer
!
Store incremented PC
CS:APP
– 18 –
Stage Computation: ret
ret
icode:ifun ! M1[PC]
Read instruction byte
valA ! R[%esp]
valB ! R[%esp]
valE ! valB + 4
Read operand stack pointer
Read operand stack pointer
Increment stack pointer
Memory
Write
valM ! M4[valA]
R[%esp] ! valE
Read return address
Update stack pointer
back
PC update
PC ! valM
Set PC to return address
9 0
Fetch
return:
XX XX
Fetch
!
Read 1 byte
!
Decode
!
Read stack pointer
Execute
!
Increment stack pointer by 4
Read return address from
old stack pointer
Execute
Write back
!
Update stack pointer
PC Update
!
– 19 –
Decode
Memory
Set PC to return address
CS:APP
– 20 –
!
Use ALU to increment stack pointer
!
Read return address from memory
CS:APP
Computation Steps
Fetch
Decode
Execute
Memory
Write
back
PC update
icode,ifun
rA,rB
valC
valP
valA, srcA
valB, srcB
valE
Cond code
valM
dstE
dstM
PC
Computation Steps
OPl rA, rB
icode:ifun ! M1[PC]
rA:rB ! M1[PC+1]
Read instruction byte
Read register byte
[Read constant word]
Compute next PC
Read operand A
Read operand B
Perform ALU operation
Set condition code register
[Memory read/write]
Write back ALU result
[Write back memory result]
Update PC
valP ! PC+2
valA ! R[rA]
valB ! R[rB]
valE ! valB OP valA
Set CC
R[rB] ! valE
PC ! valP
Fetch
Decode
Execute
Memory
Write
back
PC update
icode,ifun
rA,rB
valC
valP
valA, srcA
valB, srcB
valE
Cond code
valM
dstE
dstM
PC
call Dest
icode:ifun ! M1[PC]
Read instruction byte
[Read register byte]
Read constant word
Compute next PC
[Read operand A]
Read operand B
Perform ALU operation
[Set condition code reg.]
[Memory read/write]
[Write back ALU result]
Write back memory result
Update PC
valC ! M4[PC+1]
valP ! PC+5
valB ! R[%esp]
valE ! valB + –4
M4[valE] ! valP
R[%esp] ! valE
PC ! valC
!
All instructions follow same general pattern
!
All instructions follow same general pattern
!
Differ in what gets computed on each step
!
Differ in what gets computed on each step
CS:APP
– 21 –
CS:APP
– 22 –
newPC
Computed Values
Fetch
SEQ Hardware
Execute
Key
icode
Instruction code
!
valE
ALU result
ifun
rA
Instruction function
Instr. Register A
!
Bch
Branch flag
rB
valC
Instr. Register B
Instruction constant
valP
Incremented PC
data out
!
Blue boxes:
predesigned hardware
blocks
!
Gray boxes:
control logic
read
Mem.
control
Memory
Data
Data
memory
memory
write
Addr
" E.g., memories, ALU
valM Value from
memory
Bch
Execute
Data
valE
ALU
fun.
ALU
ALU
CC
CC
ALU
A
ALU
B
" Describe in HCL
!
Decode
– 23 –
valM
Memory
!
New
PC
PC
srcA
srcB
Register ID A
Register ID B
!
dstE
dstM
Destination Register E
Destination Register M
!
valA
valB
Register value A
Register value B
!
CS:APP
– 24 –
White ovals:
labels for signals
Thick lines:
32-bit word values
Thin lines:
4-8 bit values
Dotted lines:
1-bit values
valA
valB
dstE dstM srcA srcB
dstE dstM srcA srcB
Decode
A
B
Register
Register M
file
file E
Write back
icode
Fetch
ifun
rA
rB
Instruction
Instruction
memory
memory
valC
valP
PC
PC
increment
increment
PC
CS:APP
Fetch Logic
icode
ifun
rA
rB
valC
valP
Need
valC
Instr
valid
Need
regids
Split
Split
Fetch Logic
icode
ifun
rA
rB
PC
PC
increment
increment
PC
PC
increment
increment
Need
regids
Split
Split
Align
Align
Byte 0
Bytes 1-5
Bytes 1-5
Instruction
Instruction
memory
memory
Instruction
Instruction
memory
memory
Predefined Blocks
valP
Need
valC
Instr
valid
Align
Align
Byte 0
valC
PC
PC
Control Logic
!
PC: Register containing PC
!
Instr. Valid: Is this instruction valid?
!
Instruction memory: Read 6 bytes (PC to PC+5)
!
!
Split: Divide instruction byte into icode and ifun
Need regids: Does this instruction have a register
bytes?
!
Align: Get fields for rA, rB, and valC
!
Need valC: Does this instruction have a constant word?
CS:APP
– 25 –
Fetch Control
Logic
nop
0
0
halt
1
0
rrmovl rA, rB
2
0 rA rB
irmovl V, rB
3
0
8 rB
V
rmmovl rA, D(rB)
4
0 rA rB
D
mrmovl D(rB), rA
5
0 rA rB
D
OPl rA, rB
6
fn rA rB
CS:APP
– 26 –
Decode Logic
valA
jXX Dest
7
fn
Dest
call Dest
8
0
Dest
ret
9
0
pushl rA
A
0 rA 8
popl rA
B
0 rA 8
valB
valM valE
Register File
!
Read ports A, B
!
Write ports E, M
!
Addresses are register IDs or
8 (no access)
A
B
Register
Register
file
file
dstE
dstM
srcA
dstE dstM srcA
M
E
srcB
srcB
Control Logic
bool need_regids =
icode in { IRRMOVL, IOPL, IPUSHL, IPOPL,
IIRMOVL, IRMMOVL, IMRMOVL };
!
srcA, srcB: read port
addresses
!
dstA, dstB: write port
addresses
icode
rA
rB
bool instr_valid = icode in
{ INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL,
IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL };
– 27 –
CS:APP
– 28 –
CS:APP
A Source
E Destination
Decode
OPl rA, rB
valA ! R[rA]
Read operand A
OPl rA, rB
Write-back R[rB] ! valE
Decode
rmmovl rA, D(rB)
valA ! R[rA]
Read operand A
Write-back
None
Decode
popl rA
valA ! R[%esp]
Read stack pointer
popl rA
Write-back R[%esp] ! valE
Update stack pointer
No operand
Write-back
None
No operand
call Dest
Write-back R[%esp] ! valE
Update stack pointer
Read stack pointer
ret
Write-back R[%esp] ! valE
Update stack pointer
rmmovl rA, D(rB)
jXX Dest
jXX Dest
Decode
call Dest
Decode
Decode
ret
valA ! R[%esp]
int srcA = [
icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL
icode in { IPOPL, IRET } : RESP;
1 : RNONE; # Don't need register
];
} : rA;
CS:APP
– 29 –
int dstE = [
icode in { IRRMOVL, IIRMOVL, IOPL} : rB;
icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP;
1 : RNONE; # Don't need register
];
– 30 –
ALU A Input
Execute Logic
ALU
OPl rA, rB
valE ! valB OP valA
Perform ALU operation
Execute
rmmovl rA, D(rB)
valE ! valB + valC
Compute effective address
Execute
popl rA
valE ! valB + 4
Increment stack pointer
" Implements 4 required functions
" Generates condition code values
!
Bch
" Register with 3 condition code
bcond
bcond
bits
!
bcond
Set
CC
Control Logic
!
!
!
– 31 –
Set CC: Should condition code
register be loaded?
jXX Dest
icode ifun
ALU
fun.
ALU
ALU
CC
CC
" Computes branch flag
!
valE
CC
CS:APP
Execute
Units
!
Write back result
ALU
A
valC
ALU
B
valA
Execute
No operation
Execute
call Dest
valE ! valB + –4
Decrement stack pointer
Execute
ret
valE ! valB + 4
Increment stack pointer
valB
ALU A: Input A to ALU
ALU B: Input B to ALU
ALU fun: What function should
ALU compute?
CS:APP
int aluA = [
icode in { IRRMOVL, IOPL } : valA;
icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valC;
icode in { ICALL, IPUSHL } : -4;
icode in { IRET, IPOPL } : 4;
# Other instructions don't need ALU
– 32 –
];
CS:APP
ALU Operation
Execute
OPl rA, rB
valE ! valB OP valA
Execute
rmmovl rA, D(rB)
valE ! valB + valC
Execute
popl rA
valE ! valB + 4
Memory Logic
Perform ALU operation
Memory
!
Compute effective address
Increment stack pointer
jXX Dest
– 33 –
No operation
Execute
call Dest
valE ! valB + –4
Decrement stack pointer
Execute
ret
valE ! valB + 4
Increment stack pointer
int alufun = [
icode == IOPL : ifun;
1 : ALUADD;
];
CS:APP
Memory Address
data out
Mem.
read
Mem.
write
Control Logic
!
Execute
valM
Reads or writes memory
word
Mem. write: should word be
written?
!
Mem. addr.: Select address
!
Mem. data.: Select data
Data
Data
memory
memory
write
data in
Mem. read: should word be
read?
!
read
Mem
addr
icode
valE
Mem
data
valA valP
CS:APP
– 34 –
Memory Read
OPl rA, rB
Memory
No operation
Memory
rmmovl rA, D(rB)
M4[valE] ! valA
Memory
popl rA
valM ! M4[valA]
OPl rA, rB
Memory
Write value to memory
Memory
Memory
Memory
Memory
rmmovl rA, D(rB)
M4[valE] ! valA
Write value to memory
Memory
popl rA
valM ! M4[valA]
Read from stack
Read from stack
jXX Dest
No operation
call Dest
M4[valE] ! valP
ret
valM ! M4[valA]
No operation
jXX Dest
Memory
Write return value on stack
Memory
call Dest
M4[valE] ! valP
Write return value on stack
Memory
ret
valM ! M4[valA]
Read return address
Read return address
int mem_addr = [
icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : valE;
icode in { IPOPL, IRET } : valA;
# Other instructions don't need address
CS:APP
– 35 – ];
No operation
bool mem_read = icode in { IMRMOVL, IPOPL, IRET };
– 36 –
CS:APP
PC
Update
PC Update Logic
PC
PC update
OPl rA, rB
PC ! valP
Update PC
PC update
rmmovl rA, D(rB)
PC ! valP
Update PC
PC update
popl rA
PC ! valP
Update PC
PC update
jXX Dest
PC ! Bch ? valC : valP
Update PC
PC update
call Dest
PC ! valC
Set PC to destination
PC update
ret
PC ! valM
Set PC to return address
New PC
!
New
PC
Select next value of PC
icode
Bch
valC
valM
valP
CS:APP
– 37 –
SEQ Operation
State
!
Combinational
Logic
Read
Write
Data
Data
memory
memory
PC register
!
Cond. Code register
!
Data memory
– 38 –
int new_pc = [
icode == ICALL : valC;
icode == IJXX && Bch : valC;
icode == IRET : valM;
1 : valP;
];
SEQ
Operation
#2
Register file
All updated as clock rises
Cycle 1
Cycle 2
Cycle 3
CS:APP
Cycle 4
Clock
Cycle 1:
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
!
CC
CC
Read
Ports
Write
Ports
Register
Register
file
file
PC
0x00c
Combinational
Logic
Read
Combinational Logic
!
ALU
!
Control logic
!
Memory reads
CC
CC
100
100
Write
!
state set according to
second irmovl
instruction
!
combinational logic
starting to react to
state changes
Data
Data
memory
memory
Read
Ports
Write
Ports
Register
Register
file
file
%ebx
%ebx == 0x100
0x100
" Instruction memory
" Register file
" Data memory
– 39 –
PC
0x00c
CS:APP
– 40 –
CS:APP
SEQ
Operation
#3
Combinational
Logic
CC
CC
100
100
Cycle 1
Cycle 3
Cycle 4
Cycle 1:
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
Read
Write
!
Data
Data
memory
memory
Read
Ports
000
Cycle 2
Clock
!
Write
Ports
Register
Register
file
file
SEQ
Operation
#4
Cycle 1
Combinational
Logic
CC
CC
000
000
combinational logic
generates results for
addl instruction
Cycle 4
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
Write
!
state set
according to addl
instruction
!
combinational
logic starting to
react to state
changes
Data
Data
memory
memory
Read
Ports
Write
Ports
Register
Register
file
file
%ebx
%ebx == 0x100
0x100
Cycle 3
Cycle 1:
Read
state set according to
second irmovl
instruction
Cycle 2
Clock
%ebx
%ebx == 0x300
0x300
0x00e
PC
0x00c
PC
0x00e
CS:APP
– 41 –
SEQ
Operation
#5
Cycle 1
Cycle 3
SEQ Summary
Cycle 4
Clock
Implementation
Cycle 1:
0x000:
irmovl $0x100,%ebx
# %ebx <-- 0x100
Cycle 2:
0x006:
irmovl $0x200,%edx
# %edx <-- 0x200
Cycle 3:
0x00c:
addl %edx,%ebx
# %ebx <-- 0x300 CC <-- 000
Cycle 4:
0x00e:
je dest
# Not taken
Read
Combinational
Logic
CC
CC
000
000
Cycle 2
CS:APP
– 42 –
Write
!
Data
Data
memory
memory
Read
Ports
Write
Ports
Register
Register
file
file
%ebx
%ebx == 0x300
0x300
!
state set
according to addl
instruction
!
Express every instruction as series of simple steps
!
Follow same general flow for each instruction type
!
Assemble registers, memories, predesigned combinational
blocks
!
Connect with control logic
Limitations
combinational
logic generates
results for je
instruction
!
Too slow to be practical
!
In one cycle, must propagate through instruction memory,
register file, ALU, and data memory
!
Would need to run clock very slowly
!
Hardware units only active for fraction of clock cycle
0x013
PC
0x00e
– 43 –
CS:APP
– 44 –
CS:APP