Overview of Logic Design
CS:APP Chapter 4
Computer Architecture
Fundamental Hardware Requirements
!
Logic Design
Communication
" How to get values from one place to another
!
Computation
!
Storage
Bits are Our Friends
Randal E. Bryant
!
Everything expressed in terms of values 0 and 1
!
Communication
!
Computation
" Low or high voltage on wire
" Compute Boolean functions
Carnegie Mellon University
!
Storage
" Store bits of information
http://csapp.cs.cmu.edu
CS:APP
–2–
CS:APP
Digital Signals
Computing with Logic Gates
0
1
And
0
a
b
Voltage
Or
out
out = a && b
Time
!
Use voltage thresholds to extract discrete values from
continuous signal
!
Simplest version: 1-bit signal
a
b
Not
out
out = a || b
a
out
out = !a
!
Outputs are Boolean functions of inputs
!
Respond continuously to changes in inputs
" With some, small delay
Rising Delay
Falling Delay
a && b
b
" Either high range (1) or low range (0)
" With guard range between them
!
Voltage
Not strongly affected by noise or low quality circuit elements
a
" Can make circuits simple, small, and fast
–3–
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–4–
Time
CS:APP
Combinational Circuits
Bit Equality
Acyclic Network
a
Bit equal
HCL Expression
eq
Primary
Inputs
Primary
Outputs
bool eq = (a&&b)||(!a&&!b)
b
!
Generate 1 if a and b are equal
Hardware Control Language (HCL)
Acyclic Network of Logic Gates
!
!
Continously responds to changes on primary inputs
!
Primary outputs become (after some delay) Boolean
functions of primary inputs
" Boolean operations have syntax similar to C logical operations
!
CS:APP
–5–
Very simple hardware description language
Word Equality
We’ll use it to describe control logic for processors
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–6–
Bit-Level Multiplexor
Word-Level Representation
b31
a31
b30
Bit equal
Bit equal
eq31
B
=
eq30
a0
–7–
Bit MUX
bool out = (s&&a)||(!s&&b)
out
HCL Representation
Bit equal
Bit equal
HCL Expression
b
Eq
a1
b0
s
A
a30
b1
Eq
bool Eq = (A == B)
a
eq1
!
eq0
!
32-bit word size
HCL representation
" Equality operation
!
Control signal s
!
Data signals a and b
!
Output a when s=1, b when s=0
" Generates Boolean value
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–8–
CS:APP
Word Multiplexor
HCL Word-Level Examples
Word-Level Representation
s
Minimum of 3 Words
s
B
b31
out31
Out
MUX
C
B
A
A
a31
HCL Representation
b30
int Out = [
s : A;
1 : B;
];
out30
a30
!
!
Min3
Select input word A or B
depending on control signal s
HCL representation
D0
D1
D2
D3
MUX4
Out4
" Output value for first
a0
successful test
–9–
!
Final case guarantees
match
!
Select one of 4 inputs
based on two control
bits
!
HCL case expression
Simplify tests by
assuming sequential
matching
s1
s0
" Series of test : value pairs
out0
!
Find minimum of three
input words
HCL case expression
4-Way Multiplexor
" Case expression
b0
MIN3
!
int Min3 = [
A < B && A < C : A;
B < A && B < C : B;
1
: C;
];
CS:APP
Arithmetic Logic Unit
int Out4 = [
!s1&&!s0: D0;
!s1
: D1;
!s0
: D2;
1
: D3;
];
!
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– 10 –
Storing 1 Bit
Bistable Element
0
Y
A
X
B
1
A
L
U
Y
A
X+Y
OF
ZF
CF
X
A
L
U
B
2
Y
A
X-Y
OF
ZF
CF
X
B
q
3
Y
A
L
U
A
X&Y
OF
ZF
CF
X
B
A
L
U
Q+
!q
X^Y
Q–
q = 0 or 1
OF
ZF
CF
V1
1
1
0.9
0.9
!
Combinational logic
0.8
0.8
V2
" Continuously responding to inputs
!
V1
V1
V2
0.6
0.6
Control signal selects function computed
0.5
0.5
" Corresponding to 4 arithmetic/logical operations in Y86
!
0.7
0.7
0.4
0.4
Also computes values for condition codes
Vin
0.3
0.3
V1
0.2
0.2
0.1
0.1
0
00
– 11 –
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– 12 –
0.1
0.1
0.2
0.2
0.3
0.3
0.4
0.4
0.5
0.5
Vin
0.6
0.6
0.7
0.7
0.8
0.8
0.9
0.9
1
1
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Storing 1 Bit (cont.)
Physical Analogy
Stable 1
1
Bistable Element
1
0.9
0.9
q
0.8
Q+
0.8
0.7
0.7
V1Vin
V2V2
0.6
0.6
!q
0.5
0.5
Q–
0.4
0.4
q = 0 or 1
0.2
0.2
0.1
1
1
0.1
Stable 0
0.9
0.9
Vin = V2
V2
Metastable
0.3
0.3
Stable 1
0
0 0
0
0.1
0.2
0.3
0.4
0.1
0.2
0.3
0.4
0.8
0.7
0.7
Stable left
0.2
0.2
0.1
0.1
0.2
0.3
0.4
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.5
0.6
0.7
Vin
0.8
0.8
0.9
1
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q
!q
S
0
0
Q–
Stable right
D
R
Q+
Q–
Q–
S
Storing
0
S
1
1
Q+
Q–
C
S
Clock
0
0
R
Data
Q+
Setting
R
CS:APP
R-S Latch
1
0
Q+
Q–
R
S
0
Latching
!q
q
q
!q
Q+
d
CS:APP
D
Storing
!d
!d
R
!d
d
d
D
!d
0R
!q
q
Q+
Q+
Q–
1
– 15 –
.
1-Bit Latch
q = 0 or 1
1
1
D Latch
Bistable Element
Q+
1
– 14 –
Storing and Accessing 1 Bit
0
0.9
1
0.9
Vin
1
0.9
0
0 0
0
– 13 –
R
0.8
.
.
0.1
1
0.8
Metastable
0.3
0.3
Resetting
0.7
Metastable
0.4
0.4
Stable 0
0.7
0.6
V2V2
0.5
0.5
V1
0.6
0.5
V1Vin
0.6
0.6
Vin
0.5
Vin
Vin
0.8
– 16 –
C
Q–
dS
d
!d
0
C
0
S
q
!q
Q–
CS:APP
Transparent 1-Bit Latch
Changing D
Latching
d
D
Edge-Triggered Latch
!d
!d
!d
R
D
d
C
R
Data
Q+
Q+
D
1
Q–
C
dS
d
!d
Q+
Q–
C
Time
T
Clock
!
When in latching mode, combinational propogation from D
to Q+ and Q–
!
Value latched depends on value of D as C falls
S
Trigger
C
!
Only in latching mode
for brief period
!
Value latched depends
on data as clock rises
!
Output remains stable at
all other times
T
" Rising clock edge
D
Q+
Time
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– 17 –
Registers
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– 18 –
Register Operation
Structure
i7
i6
i5
i4
i3
i2
i1
i0
D
C
Q+
o7
D
C
Q+
o6
D
C
Q+
o5
D
C
Q+
o4
D
C
Q+
o3
D
C
Q+
o2
D
C
Q+
o1
D
C
Q+
o0
State = x
Input = y
I
x
O
!
Rising
clock
!
Output = y
y
Clock
Clock
!
Output = x
State = y
!
Stores data bits
!
For most of time acts as barrier between input and output
!
As clock rises, loads input
Stores word of data
" Different from program registers seen in assembly code
– 19 –
!
Collection of edge-triggered latches
!
Loads input on rising edge of clock
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CS:APP
State Machine Example
Random-Access Memory
valA
Comb. Logic
srcA
0
!
A
L
U
0
Out
MUX
In
1
Load
!
Accumulator
circuit
A
valW
Register
Register
file
file
Read ports
valB
srcB
Load or
accumulate on
each cycle
W
dstW
Write port
B
Clock
!
Stores multiple words of memory
!
Register file
" Address input specifies which word to read or write
Clock
" Holds values of program registers
Clock
" %eax, %esp, etc.
" Register identifier serves as address
Load
» ID 8 implies no read or write performed
x0
In
x1
x0
Out
x2
x0+x1
x3
x0+x1+x2
x4
x3
x3+x4
x5
!
" Can read and/or write multiple words in one cycle
x3+x4+x5
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– 21 –
Register File Timing
x
A
valB
srcB
!
Like combinational logic
Register
Register
file
file
!
Output data generated based on
input address
B
" After some delay
2
!
!
Very simple hardware description language
!
Can only express limited aspects of hardware operation
" Parts we want to explore and modify
Data Types
Writing
!
CS:APP
Hardware Control Language
x
2
» Each has separate address and data input/output
– 22 –
Reading
valA
srcA
Multiple Ports
!
bool: Boolean
!
int: words
" a, b, c, …
Like register
Update only as clock rises
" A, B, C, …
2
x
valW
Register
Register
file
file
W
dstW
y
2
!
Rising
clock
2
!
" Does not specify word size---bytes, 32-bit words, …
y
valW
Register
Register
file
file
W
Statements
dstW
! bool a = bool-expr ;
! int A = int-expr ;
Clock
– 23 –
Clock
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– 24 –
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HCL Operations
!
Summary
Computation
Classify by type of value returned
Boolean Expressions
!
Logic Operations
" a && b, a || b, !a
!
Word Comparisons
Performed by combinational logic
!
Computes Boolean functions
!
Continuously reacts to input changes
Storage
" A == B, A != B, A < B, A <= B, A >= B, A > B
!
!
!
Set Membership
" Hold single words
" A in { B, C, D }
" Loaded as clock rises
» Same as A == B || A == C || A == D
!
Word Expressions
!
Registers
Random-access memories
" Hold multiple words
" Possible multiple read or write ports
Case expressions
" Read word when address input changes
" [ a : A; b : B; c : C ]
" Write word as clock rises
" Evaluate test expressions a, b, c, … in sequence
" Return word expression A, B, C, … for first successful test
– 25 –
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