chapter 3

DIGITAL LOGIC DESIGN
by
Dr. Fenghui Yao
Tennessee State University
Department of Computer Science
Nashville, TN
Gate-Level Minimization
1
What is minimization?


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Simplifying boolean expressions
Algebraic manipulations is hard since
there is not a uniform way of doing it
Karnaugh map or K-map techniques is
very commonly used
Gate-Level Minimization
2
Two-Variable K-Map
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Example
F  AB  A' B  B
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Example
F  AB  A' B  A' B'  A' B
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Three-Variable K-Map
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Three-Variable K-Map
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Example
F  ABC ' A' B' C ' AB' C  ABC
 AB  AC  A' B' C '
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Note


In K-maps, you can have groups of 2,
4, 8, or 16
You cannot have groups of other
combinations such as a group of 6
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Exercises
F1  A' BC  AB' C ' AB' C ' AB
F2  A' C  A' C ' AB' C ' ABC '
F3  A' B  A' BC 'C '
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Example

Represent F in the minimal format and
draw the network diagram
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Example

Represent F in the minimal format and
draw the network diagram
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Example
F   0,2,3,4,5,7

Represent F in the minimal format and
draw the network diagram
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Four-Variable K-Map
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Four-Variable K-Map
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Example
F ( A, B, C, D)   0,1,2,4,5,6,8,12,13

Represent
F in the
minimal
format and
draw the
network
diagram
F ( A, B, C , D)  A' C ' A' D'C ' D' ABC '
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Example
F ( A, B, C, D)   3,5,6,8,10,11,12,13,15

Represent F in the minimal format and
draw the network diagram
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Example

Represent F in the minimal format and
draw the network diagram
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18
Prime Implicants
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You must cover all of the minterms
You must avoid redundancy
You must follow some rules
Prime Implicant


A product term that is generated by combining
the maximum number of adjacent squares in the
map
Essential Prime Implicant

A minterm that is covered by only one prime
implicant
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Maxterm Simplification

Remember
F  (F ' )'
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Example

Simplify F in product of sums
F ( A, B, C, D)   1,2,3,5,6,8,10,11,12
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Example (cont)

Step – 1

Fill the K-map for F
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Example (cont)

Step – 1

Fill the K-map for F
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Example (cont)

Step – 2

Fill zeros in the rest of the squares
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Example (cont)

Step – 3

Cover zeros. This is your F’
F ( A, B, C , D)'  A' C ' D' AC ' D  BCD  ABC

F ( A, B, C , D)  ( A  C  D)( A'C  D' )( B'C ' D' )( A' B'C ' )
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Important
( A  B)'  A' B'
( AB)'  A' B'
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Don’t Care Conditions



A network is usually composed of subnetworks
Net-1 may not produce all
combinations of A,B, and C
In this case, F don’t care about those
combinations
A
Net-1
B
Net-2
F
C
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Don’t Care Conditions
X can be
considered
as 0 or 1,
whichever
is more
convenient
A B C F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
x
0
1
0
0
x
1
F  A' B 'C '  A' BC  ABC
F  A' B 'C '  A' BC  A' B 'C  ABC  A' B '  BC
F  A' B 'C '  A' BC  A' B 'C  ABC  ABC '  A' B '  BC  AB
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28
NAND/NOR
Implementations



AND, OR, and NOT gates can be used
to construct the digital systems
However, it is easier to fabricate NAND
and NOR gates
So try to replace AND, OR, and NOT
gates with NAND or NOR gates
Gate-Level Minimization
29
NAND Implementation




First implement with AND-OR
Put bubble at the output of each AND
gate
Put bubbles at the inputs of each OR
gate
Place necessary inverters
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Example
F ( A, B)  AB  CD  E
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Example
F ( A, B)  A' ( BC  D)  AB
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Example
F ( A, B)  A' ( BC  D)  AB
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NOR Implementation




First implement with AND-OR
Put bubble at the inputs of each AND
gate
Put bubbles at the output of each OR
gate
Place necessary inverters
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Example
F ( A, B)  ( A  B)C ( D  E )
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Study Problems

Course Book Chapter – 3 Problems






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3– 1
3–3
3–5
3–7
3 – 12
3 – 15
3 – 18
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Questions
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