California State University, Northridge
Wavelet analysis and Implementation in FPGA
A graduate project submitted in partial fulfillment of the requirement
For the degree of Master of Science
in Electrical Engineering
By
Zaid Ridha
December 2011
The graduate project ofZaid Ridha is approved:
Dr.Mirzaei Shahvmm
Date
Dr.Amini Ali
Date
Dr.Xiyi Hang,Chair
Date
California State University Northridge
ii
Acknowledgement
To whom I loved the most my mom how support me all thyse years and saved my
life from wars. To my dad and his suppmi and advices all these years. To my dearest
brother and his family. Special thank to professor hang for the support and guidance
through this project. Special thanks to Professor Mirzae and his help and support all
these years'. I would like to thanks Professor Al N aga for introducing me to the field
of electrical engineering and to professor Amini how was like a father for me all
these years. special thanks to all my friends and family and to all whom stand with
me during this three hard years of my life; thank you all I love you and I appreciate
all the help and I will never forget what all of you did for Ihe.
iii
TABLE OF CONTENTS
SIGNATURE PAGE .............................................................................. iv
ACKNOWLEDGEMENT ........................................................................ iv
LIST OF FIGURES ................................................................................ iv
LIST OF TABLES ................................................................................. iv
-
·ABSTRACT ........................................................................................ iv
CHAPTERS
1- INTRODUCTION ......................................................................... .1
2-
WAVELET .................................................................................. 2
2.1
Introduction .......................................................................... 2
2.2 Discrete Wavelet Transform ....................................................... 6
2.3 Inverse Discrete Transform ......................................................... 8
2.4 Continuous Wavelet Transform ...................................................... 9
2.5 Filter Bank ............................................................................ 10
3-
WA:VELETS IMPLEMENTATION IN FPGA ....................................... 17
3.1 Introduction ....................................................................... 17
3.2 Discrete Wavelet Transform Implementation ................................ 18
3.3 Inverse Discrete Wavelet Transfmm Implementation ...................... .22
3.4 Top Module Design Implementation ........................................... 27
iv
4-
AUDIO PRESENTATION USING WAVELET ..................................... 31
4.1 Introduction ........................................................................... 31
4.2 Audio File .............................................................................. 32
4.3 Simulink ................................................... ·............................ 32
4.4 Discrete Wavelet Transform Implementation ......................~ .............. 33
4.5 Inverse Discrete Wavelet Transform Implementation .......................... .42
Conelusion ..................................................................................... 55
References ...................................................................................... 56
Appendix A ...................................................................................... 58
v
LIST OF FIGURES
Figure 2.1 Multilevel DWT construction of the signal. ................................ , , , , ... 7
Figure 2.2 multilevel IDWT Reconstruction of the signal ...................................... 9
Figure 2.3 The Input 128 sampled Signal.. ...................................................... 14
Figure 2.4 The Reconstructed output 128 sampled Signal. ................................... 15
Figure 2.5 DWT1,DWT2,DWT3 ................................................................. 16
Figure 2.6 IDWT1,IDWT2,IDWT3 ............................................................. 18
Figure 3.1 DWT Implementation in FPGA .................................................... .20
Figure 3.2 IDWT Implementation in FPGA ...... ·····················~······················ ... 25
Figure 3.3 Over All Design In FPGA ............................................................ 28
Figure 4.1 DWT Stage one ......................................................................... 33
Figure 4.2 DWT Stage I Matalb Result .......................................................... 35
Figure 4.3 DWT Stage I FPGA Result ........................................................... 35
Figure 4.4 DWT Stage two ........................................... ."............................ 37
Figure 4.4 DWT Stage II Matalb Result ............................... , .......................... 3 8
Figure 4.5 DWT Stage II FPGA Result .......................................................... 39
Figure 4~6 DWT Stage three ..................................................................... 39
Figure 4.7 DWT Stage III Matalb Result ...................................................... .40
vi
J
Figure 4.8 DWT Stage III FPGA Result ......................................... '" ............ .41
Figure 4.9 Three Level DWT ..................................................................... 43
Figure 4.10 IDWT Stage I. ....................................................................... 45
Figure 4.11 IDWT Stage I Matalb Result ...................................................... .47
Figure 4.12 IDWT Stage I FPGA Result ....................................................... .47
Figure 4.13 IDWT Stage I. ........................................... ·............................ 48
-
Figure 4.14 IDWT Stage II Matalb Result ..................................................... .49
Figure 4.15 IDWT Stage II FPGA Result ...................................................... .49
Figure 4::16 IDWT Stage III. ..................................................................... 51
Figure 4.17 IDWT Stage III Matlab Result ...................................................... 52
Figure 4.18 IDWT Stage III FPGA Result ....................................................... 52
~igure
4.19 original audio signal. ................................................................. 53
Figure 4.20 Matlab reconstmcted signal. ........................................................ 53
Figure 4.21 FPGA reconstructed signal. ......................................................... 53
· Figure 4.22 FPGA data flow result ................................................................ 54
Figure 4.23 FPGA data flow result ................................................................ 54
vii
LIST OF TABLES
Table 2.1 Example 2.1 coefficients Result ....................................................... 14
Table 4.1 Stage One DWT Coefficients in both matlab and FPGA .......................... 34
Jable 4.2 Stage Two DWT Coefficients in both matlab and FPGA ......................... 36
Table 4.3 Stage Three DWT Coefficients in both matlab and FPGA ....................... 38
Table 4.4 DWT Coefficients in both matlab and FPGA ....................................... 42
-Table 4.5 Stage one IDWT coefficients in both FPGA and Matlab ......................... .44
Table 4.6 Stage two IDWT coefficients in both FPGA and Matlab .......................... 46
Table 4.7 Stage three IDWT coefficients in both FPGA and Matlab ......................... 47
Table 4.8 Final coefficients comparison in FPGA and Matlab ................_.............. .49
Table 4.9 FPGA Resource usage ................................................................. 54
viii
ABSTRACT
Wavelet analysis and Implementation in FPGA.
By
ZaidMRidha
Master of Science in Electrical Engineering
This project is presenting wavelet signal explains the structure of it, the family and the
capability of wavelet. Moreover, it shows the implementation using FPGA, explain the
FPGA parts and give examples of using FPGA in wavelet. Finally, it will discuses audio
implementation using FPGA and shows the significant advantage of using wavelet in
FPGA. The last part will show the result of audio implementation using FPGA the
drawback and the futu.re work that can be done to improve these applications
ix
Chapter 1
INTODUCTION
Wavelet is new filter design that been presented in the early 1990's .It has many
applications and found to be very useful in sound and picture compression. Wavelet have
been represented in both mathematical theory and hardware application, using many
types of tools like matlab to fmd the input/output ofthe wavelet and to have all the
analysis needed and mathematical number that can be very useful to compare it to any
hardware implementation. Through the project, I will explain many theory and
mathematical basses that lead to wavelet and the component of the wavelets, for example,
the wavelet transform and the types ofthis kind of wavelet from continuous to discrete
transform function. Then I will introduce general idea of many type of wavelet families
and the shape of each one using tools like matlab. Then to go in more details of some
technique that used in wavelet ,like filter bank and the transfer from analog to digital.
Finally, I will give some introduction of one of the most famous hardware
implementation using FPGA and some introduction to FPGA hardware design.
Moreover, some of the software that used to implement FPGA like Quartusii, Modelsim
and using matlab ,and Simulimk .The Scope of the project is to introduce wavelet
structure the mathematic behind it and then introduce the technique that is useful for
implementing wavelet in FPGA to change it to the digital world. In addition, show the
FPGA implementation of wavelet using filter bank then give some implementation in
FPGA and compare it to the analysis result with matlab
1
Chapter2
WAVELET
2.1 Introduction
Wavelet in general is mathematical function that cut the data into different frequency
component, and then it will take each part of the data (component) with a resolution
that match it scale and study it. Wavelet is relatively new it has been developed in
many field (e.g. Mathematical, quantum physics, electrical engineering, biomedical,
and geology). The need of-these field and the interchange between them during the
last decade have lead to many application that made a great impact in these
technologies. For example image processing (e.g. image compression,
decompression, finger print analysis and more).Plus it has been extensively used in
radar, human vision, turbulence and earth quick prediction.
Wavelet has great advantage over the traditional theory of Fourier transform. Where
wavelet has the capability of analyzing the physical situations where the signal
contains discontinues and sharp spike.
First, let us understand the concept behind wavelet, the need of analyzing the signal
according to its scale was the biggest advantage of wavelet, which op~ned a new
perspective in processing data. Wavelet simply is a function that satisfies certain
mathematical requirement as if any other mathematical function that been used to
repr,esent data. It has been based on an old idea of approximation using super
2
position in linear system using SIN and COSIN signal to represent others functions.
However, in wavelet the using of scaling is the key element in to
obse~"Ving
data. The
problem is we wanted more appropriate Function than SIN and COSIN which can
satisfy the use of Fourier transform and at the same time Can deal with choppy
sigl};als (which are non-local signals that can stretch to infinity) ,The problem with
these signals it is very hard and very poor to do an adequate approximation to them
because they are sharp spike signal. What is the solution? The answer is very clear
Wavelet. Now we can use· wavelet that provides us with approximating functions
that neatly contain a finite domain and it will be well suited for an approximating
data with sharp discontinuities. The procedure is relatively simple we adopt a
prototype function, that we called an analyzing wavelet [1], we separate the function
into two parts the first one with high frequency and the second with low frequency
.The high frequency one we Temproral analysis by using contracted high frequency
version of the prototype, and for the low frequency we do it with dilated low
frequency version of the same wavelet prototype. And to construct the perfect
wavelets filter bank for Daubechies filter the high-pass ,low-pass filter should be
mirror of each other which is typical behavior of orthogonal filter bank. The perfect
coefficient will be
G(z) =
( 1+v'3)+( 3+-J3)z- 1 +( 3--J3)z- 2 +(1--J3)z- 3
.r
4v2
0.4829
+ 0.8364z- 1 + 0.2241z- 2 - 0.1294z- 3
-( 1--J3)+(3--J3)z- 1 - ( 3+-J3)z- 2 +(1 +-J3)z- 3
H ( z) = ---'-----=-----0..----=---4-'v::-z---'---__;_-___;__
0.124 + 0.221z- 1 - 0.834z- 2 + 0.489z- 3
3
Then we can translate these coefficients directly into hardware and implement the
filter bank as we can see in my implementation later .Very important to understand
that the original signal can be represented in term of wavelet expansion using
coefficients in a linear combination of wavelet function [1].And from all the level of
analysis and coefficient obtained we can choose the best wavelet that adapt to the
chosen data; which make the data sparsely represented which make wavelet the
ultimate tools for data compression and other data analysis. Wavelet based on
scaling function a basis function varies in scale.For example; imagine we have a
signal over the domain from 0 to 1. We can divide the signal with two-step functions
that range from 0 to 0.5 and 0.5 to 1. Then we divide the original signal again in
steps functions from 0 to 1 by 0.25 division. And so on. [1]. Signal can be
represented in both the time and frequency domain, time domain represent the signal
with respect to time, where frequency domain represent the signal in each frequency
band over range of frequencies. Most of today application use frequency domain
spicily in signal processing .Because it has many characteristic like noise, and signal
strength. Frequency domain presents a good practice for stationary signals, and
continuous signals. However, if we have non-stationary signal we will have problem
of signal varying over time. This is why in the last section we used short time
Fourier transform instead of the regular Fourier transform which cannot detect these
varies signals. So by using the short method allowed us to represent the signal in
both time and frequency domain for a short period of time (which involve dividing
the signal into short segments).The advantage it will change the long period signal
that is not stationary to a small period but it is stationary. This is what we call
4
window function and it could vary from small window with poor frequency
resolution or relatively large window with good frequency resolution, the problem is
when it come to the timinGresolution it's the opposite so each one has it advantage
and disadvantage [7].
The solution came with wavelet transform, which enable variable window lengths
using long time intervals for more accurate low frequency component or segment
and short time interval for high data. As we define wavelets before it has average
value of zero for effectively limited duration, .it will break the signal into scaled
version of the original mother wavelet.
Finally all these wavelets are called Orthogonal Wavelets which include the
Daubechies family, Haar family, Symmlets family, and Coiflets family.But there is
another types of wavelets
~
•
Crude Wavelets
•
Biorthogonal Wavelets
The Crude wavelet lack many properties that can be found in orthogonal wavelets for
example the Morlet Wavelets, and Mexican Hat Wavelets, which both lack the scaling
function that can't be constructed. Which mean they are not Orthogonal because the
missing of compact support and the vanishing moment. The filter cannot be calculated
which make them useful for mathematical demonstration [8].
The Biorthogonal Wavelets known for the ability of creating symmetric transform which
include both the scaling function and the wavelets. Which required an odd length filter
~
and different properties for the two stages of analysis and resynthesis.Moreover two type
5
of filter will be used in the analysis stage and two different filters would be used in the
{esynthesis stage, which make it different from the one I used in my implementation a
mirror filter for each stage [8].
2.2 Discrete Wavelet Transform
Although the discrete continuous wavelet transform enables the computation of the
continuous wavelet transform by computers, it is not a true discrete transform. The DWT
is simply a sampled version of the CWT, and the information it provides is highly
redundant. This redundancy will cause a required significant amount of computation time
. The discrete wavelet transform (DWT) will provides sufficient information for both
analysis and synthesis of the signal,. [10]
Because the DWT does not choose continues scale and to get accurate result as we said
- previously by choosing scale and position but it use two concept of approximation and
details. Which is respectfully is high scale with low frequency of the signal and the
details are low scale high frequency of the signal segments. DWT coefficients are usually
sampled from the CWT on a dyadic scales (choosing scales and· position that are based on
"'
power of two) .. This sequence will be denoted by x[n], where n is an integer. The
procedure stmis with passing this signal (sequence) through a half band digital low pass
filter with impulse response h[n]. In addition, a high pass filter at the same time. Which
give the-advantage of eliminating the extra details in high frequency component and low
frequency component. Which mean we are eliminating the redundancy from both filters.
We will get two set of wavelet coefficient with half of the mother wavelet size, one called
approximation and the second called details [3][10].Less number ofsmnples is used for a
6
lower frequencies, so the resolution will decreases as frequency decreases, simply
because of the reduced time resolution. Images, particularly with great resolution, will
take a lot of disk space. DWT can be used to reduce the image size without losing much
of the resolution. Figure 2.1 will show the design that been used in multilevel DWT [3].
X(n
I
HP
I PF
HP
I PF
Level one DWT
HP
I PF
Level two DWT
Level three DWT
Figure 2.1 Multilevel DWT construction of the signal
7
2.3 Inverse Discrete Transform
It is the process, which the signal can be reconstructed from the constricted signal, it's
simply the reverse ofDWT without any loss in information or minimum loss. Therefore,
~
IDWT reconstructs a signal from the approximation and detail coefficients-derived from
decomposition DWT step. There is one difference in IDWT it required up sampling
where in DWT it requires down sampling. This is simply the process of adding zero
between.,each sample, which is doubling the length of the signal. These are then
convolved with the reconstruction-scaling filter for approximation coefficients (the
reconstruction-scaling filter is simply the original scaling filter that has been flipped left
to right) and the reconstruction wavelet filter for the detail coefficients. These results are
then added together to arrive at the c
X(n)
signal.
8
t
HP!=
LPF
HP!=
Figure 2.2 multileveliDWT Reconstruction of the signal
2.4 Continuous Wavelet Transform
CWT it's the sum over all time of the signal multiplied by the scale, which is the
. shifted version of the wavelet function ¥.It's very similar to the short Fourier transform
with some differences, for example when¥ applied to window signal it will eliminate
the frequency drawback that we talked about earlier. In addition, the varied window
capability, which allowed us to compute, based on the spectral component of the signal.
Which generally represented by
1
(t-T)
- 'l'xw(t,s)-- v!sl I X(t) tjJ * -s dt
CWTXw(t,s)-
9
(1)
Where we will have an array of wavelet coefficients as an input CWT(t,s) which will
repres~nt
both the scale and the position. In addition, because we want continuous
wavelet each coefficient will by multiplied by its scale and shifted wavelet. When the
signal started let assume at t=O and the scale=l we need to compute the CWT ,and by
keeping the scale constant arid incrementing the time by the unit step function we will
get value for the CWT.At the end of the wavelet we repeat the procedure with different
. scale to keep the continuality in the signal. This is go for more than CWT dimension
but there is problem the amount of data generated is huge and the computation time is
very large. Because even with one dimensional CWT we get 2D matrix, this may not be
suitabte for some applications[7][10].
2.5 Filter Bank
.e.. digital filter-bank is simply a collection of filters having a common input or output.
The input for each level X(n) will be split using low-pass (G(z)), high-pass filter(H(z))
and the reconstructed signal Y(n) is reconstructed using the same low-pass and high-pass
filter. Between these two part we will have the decimation and interpolation by 2 units.
-It's easy to define only the low-Pass filter G(z) and to use the definition for the High-Pass
filter H(z).We are using the mirror pairs which explain the relation between the HighPass and Low-Pass filter.The rule is given by[6]
G(-z)
h[n]
= (-l)n g[n]
H(z)
=
(3)
Which will define the filter to be mirror pairs. Specifically in the frequency domain as we
can see in (4). I H(ejw) I= I G(ej(w-rr))l
(4)
10
As the filters have been FIR filter so it will have constant coefficients and to relate the
input of time series x(n) with the output of the filter which is given as a finite version of
convolution sum given by (4)
y(n)
=
x(n) * f(n)
= LJ{;;,~f[K]x(n- K)
Where both f[O]and f[L- 1]
(4)
* 0 are both the filter coefficient .It's more convenient to
represe~! the transfer function in the Z-Domain with F(z) = L~:~ f[K]z-k
(6)
The analysis and the synthesis filters are chosen so as to ensure that the reconstructed
output y[ n] is a replica of each other of the input x[n] Moreover. Making use of the inputoutput relations of the down-sampler and the up-sampler in the ~-domain. In the case of a
r~al
coefficient filter the frequency domain implied by [6][7]
Which indicate both the Low-Pass and High-Pass filters and vica versa which lead to the
mirror ilnage of the two filters implied by (8,9).
(8)
(9)
It convetis an input series ofX(n), into highpass wavelet coefficient series_ and
lowpass
wavelet coefficient series. Where SL (z) and TL(z) are called wavelet filters, K is the
length of the filter, and i from {0 ...... [n/2]-1} .Such transformation will be applied
recursiv©ly on the lowpass series until we reach the number of iteration we need. The
general Z domain functions for the analysis two filters are. [7]
11
+ z- 1 )K P(z)
(10)
H1(z) = (1 + z- 1 )K Q(z)
(11)
Ho(z) = (1
And to get the perfect reconstruction filter in the synthesis stage the following Z-Domain
· Function are implied by
Ho(z)Go(z)
+
H1(z)G1(z) = 2z-k
Ho( -z)Go(z) + H1( -z)G1(z)
=
(12)
0
Lets Consider example 2.1 as an explanation to Filter Bank which we will base our Audio
design later base on it. [7]
We know we will have two type of filter (low pass) and (high pass) which both have
scaling sequence and wavelet sequence. Moreover, we know it should be normalized to
have the sum of2 and square of2 respectively. Sometimes they. will have sum of the two
tu keep the even number of coefficient to be orthonormal to each other. The general
equation to represent the scaling sequence of the discrete wavelet transform with
approximation of order A.[12]
With N=2A, p havinGreal coefficients and if we assume the P(1)=1 ,by inspection we
will have:
a(Z)a(z- 1 )+a(-Z)a(-Z- 1 )=4
12
(14)
Alternatively, simply we can represent it by solving for the Z we get similar general
equation:
Where A can be found using division in the ring of truncated power series in X equation
3.4.[10]
in addition, we can assign either one of the two linear factors to p(Z), so we can obtains
2N possible solutions.
Example 2.1
If we have signal of 128 samples as an input to our filter bank; ~hich is three level of
DWT going through High-Pass, Low-Pass Filters and the IDWT of three level of high
pass low pass filter. See figure 2.6,2.7 .The signal will be randomly generated using
matlab function rand/randn which returns an n-by-n matrix containing pseudorandom
integer values. First we will have 128 sampled generated as y which is the input for my
· filter bank after the signal go through the analysis part the signal will be divided by 2 for
each level. It will generate the 64,32,16 samples respectively. Then the signal will be
regenerated using the IDWT will created three level of signal32,64,128.and we will see
in table 2.1 the coefficients for the signal in each level and the matchinGreconstructed
signal. The sample range have been taken from 1 to 10 and number of sam-2les is 128.
Input Signal Cofficents = X
, Output Signal Cofficents = Y
13
y
X
DWT1
DWT2
DWT3
IDWT1
IDWT2 IDWT3
3
6.326
14.322
9.344
6.326
14.322
3.000
3.000
9
8.244
13.434
12.647
8.244
13.434
9.000
9.000
4
6.744
14.334
7.487
6.744
14.334
4.000
4.000-
10
9.446
13.234
12.231
9.446
13.234
10.000
10.000
2
3.644
14.834
7.690
3.644
14.834
2.000
2.000
3
-2.234
10.324
4.678
2.234
10.324
3.000
3.000
2
1.342
11.236
13.436
1.342
11.236
2.000
2.000
Table 2.1 Example 2.1 coefficients Result
There is a small percentage of errors that I ignored because it didn't cause any problem in
the signal construction as we can see graphically in the following Figures.
Figure 2.3 The Input 128 sampled Signal
14
..
~1-(f"_.,_
,-n'/->."'5' __._,_,.,_-_00"_<'"-<'>.='"Yi~">>""
· ,·---·--,/_,,-,-o-L""""
o·
I!
./9
II
~~
_,_..
~
••
l
6~ ~
r~
I
I
·.·
3
K~r
i
.,,
•• ·i
~
I
.
~
f
AIL-"-.Jt
I
I
\
II
i
lA
I
\ ~
/,
~
r'\ ~I
w
l
I
I
oMil;;ihi'i>''V'7.!.!l>I .•
;·-~
1\
'1 \}~ ~ I~
I
l
__,_,..,,,-,,_, '""
I
~~I
l
~
""W::W't<"">,_._,_,_••_,_.
i
·. ··~··
t.~.Vt .
''>'"2...
Figure 2.4 The Reconstructed output 128 sampled Signal
Figure 2.5 DWT1,DWT2,DWT3
15
~
\1
Figure 2.6 IDWTl,IDWT2,IDWT3
We can see the result is matching ,which we generated the origi!lal signal with minimum
~rror.
which I will be the base of the audio signal implementation using both FPGA and
Matlab to get the same reconstructed signal using FPGA.
16
CHAPTER3
WAVELETS IMPLEMENTATIONINFPGA
3.1 Introduction:
In my implementation, I will use audio file built in matlab, then I will pass this file
through FPGA wavelet Design that will calculate the coefficient and spilt the signal into
-two parts. Then it will return the result back to the Matlab program after completing the
wavelet conversion. Two programs will be used to do that Simulink from Matlab, and
Modelsim6.4 from Altera.The result will show that the coefficient is the same from both
the Matlab and the Modelsim, which prove that wavelet, have heen successfully done in
FPGA.My Design will be based on using the filter bank method which is l~vels of highpass and low-pass filters and down-sampling and up- sampling. The audio file will go
through two stage:
_,
•
DWT
•
IDWT
Each stage will have three level of presentation and will generate the appropriate
coefficients; after I finish the third level ofiDWT I will get the original audio signal that
~
been applied to the DWT. The audio file that been used is built in file in matlah "handel "it has
the following properties [4] Player= audio player (Y, Fs) creates an audio player object for signal
Y In addition, it can be loaded using the following command:
Load handel;
player= audioplayer(y, Fs); [matlab help audio signal][4]
17
In my design, I will call the audio player and divide it into two streams both are equal and
represent the even and odd component of the audio signal. These with the start point and
end point will go to the Modelsim 6.4 to be run through the hdl code that will produce my
coefficients for the audio{ f. g} that will be sent back to the Matlab. [4]. The Simulink
is the connection between the two program Matlab and Modelsim ,The design will be
accepting the audio file from Matalb and it will send it to Modelsim then the result will
get back into Simulink that will sent to the matlab program. Simulink doesn't do anything
it's just connection between matlab and the FPGA software which Modelsim. "And
.>
-
Simulink is an environment for multidomain simulation and Model-Based Design for
dynamic and embedded systems. It provides an interactive graphical environment and a
customizable set of block libraries that let you design, simulate, implement, and test a
~
. variety of time-varying systems, including communications, controls, signal processing,
video processing, and image processing." "Matlab Help"[4]
3.2 Discrete Wavelet Transform Implementation.
I)WT in my design will have three stages each stage will consist of high-pass and lowpass filters, plus up-sampler between each stage. So each stage with two sets of filters
used,
at each stage one filter produces the higher frequency outputs "fs" and the other produces
-the lower frequency outputs "g's" from the original signal X(n). The output of first stage
are {f,g},where the high frequency output "fs" will be the first coefficient that produced
from the DWT. The low frequency coefficient "gs" will go through down-sampler, which
will, takes one sample after each two samples. This is done to ensure that only relevant
samples are taken to ensure signal compression. My first stage will generate as I said two
18
coefficients from the HDL code and at the same time the sound signal will go through the
same prqcedure in matlab to insure that the result from both the HDL code and the matlab
code are the same. Stage one will have the following coefficient from the HDL code "fs"
,"gs"and from matlab it will generate the coefficients called "al ","a2". The first column
"fs" will be my first coefficient for the DWT and the second column "gs" will go through
the second stage ofDWT ,we can see from the table it match the result from matlab there
is very small error will occur in some coefficients at the lih precision do to noise its very
small and it will not affect the sound. Now we have the low frequency signal that been
generated from DWT Stage I will go into DWT Stage II .The "gs" signal will go through
two filter as well High-pass and low-pass , the generated result from the high frequency
signal "f g" will be the second coefficient that generated fi·om level 2 .And the generated
signal "g g" will go through second down-sampler to be feed to the third level later. For
stage two, we will have two coefficients the high frequency will be the second DWT
~oefficients
and the low frequency will go through stage three. And as we did with stage
-
one the same done in matlab to show that both matlab and the FPGA result are matching.
The first column "f g" will be my second coefficient for the DWT and the second column
"g g" will go through the third stage ofDWT ,we can see fi·om the table it match the
_ result fr~m matlab there is very small error will occur in some coefficients at the 12th
precision do to noise its very small and it will not affect the sound. Finally for stage three
which is the final stage we will get the last two coefficient "fgg" and "Ggg" after the
coefficient from the second stage "g g" went through the down :-sampler it will go
through the third stage of high-pass and low-pass filter ans we will get the high
frequency coefficient "f g g" and the low frequency coefficient "Ggg" ,as before it will be
19
-compared to the matlab stage three DWT result and its matching perfectly. The first
column "f g g" will be my third coefficient for the DWT and the second column "Ggg"
will be my fourth coefficient ,we can see from the table it match the result from matlab
there is very small error will occur in some coefficients at the
12th
precision do to noise
its very small and it will not affect the sound. And this is conclude or presentation for
DWT we generated four coefficients that will be used to reconstmcted the audio signal
using IDWT. In this implementation, there are three stages with two sets of filters used. at
each sta¥e one filter produces the higher frequency outputs and the other produces the
lower frequency outputs .The output of the three stages later will be applied to IDWT
implementation to reconstmct the signal back. The error was small that made wavelet
prefect method for audio signal.
Figure 3.1 DWT Implementation in FPGA
20
•
High Pass Filter Design:
The high pass filter is designed as a filter which allows the high pass components to pass
.>
and low frequency components to attenuate. The data format used to process the filter is
64Q62. In this format the total number length is 64 bits out of which 62 represent the
decimal number. We have used this format to have as much accuracy as possible in a
fixed point FPGA. The coefficients will be changed from the transfer function to the
equivalent of 64 bit hexadecimal. After we initiate the wires and the signal the loop will
start using pipelined statement that will run the code at once in pipelined stages, which
will generate Temprorary products that will be added to generate the coefficients for the
audio signal in sequence.
•
Low Pass Filter Design:
The low pass filter is designed to allow the low frequency components to pass and
attenuatG the high frequency components. The coefficients of the low frequency
components will be the coefficients g[n]. The frequency magnitude response of this filter
was also verified to meet the required criteria as well as being orthogonal to the high pass
filter. This filter is implemented in a verilog hdl file named "lp.v". The data format used is
64Q62.The low pass filter will be mirror of the High-Pass filter with changing the
transfer function to meet the requirement for Low-Pass filter.
•
Down-Sampling:
After e&ch forward wavelet transformation, the coefficients are down- sampled. To do
this either the even numbered or the odd numbered samples are thrown depending on the
length of the coefficients stream. In order to throw the odd numbered samples the
21
'~downsampler.v"
hdl file was used. The coefficients in the first stage appeared in the
even numbers, so this down-sampler was used, as the length was an odd number. These
coefficients were imported into matlab file hdl fg with a sampling frequency of2*Ts.
This was because the samples have now reduced to half while the clock used to generate
-them was having sampling time Ts. Mathematically Hdl fg[n] = {f[2n], g[2n]}even. In
the second stage and the third stage, the coefficients appeared in the odd numbers
because the coefficients length- was an even number. So while down sampling the even
numbered samples were thrown. Verilog Hdl file "downsamplerl.v" was used. The
coefficients obtained were imported into matlab with a sampling frequency: of 4*Ts as the
original signal was sampled with a frequency ofTs. Mathematically Hdl flgl [n]
=
{fl [2n], gl [2n]}odd.
3.3 Inverse Discrete Wavelet Transform Implementation.
The IDWT implementation will be the the same as the DWT but in reverse and we will
use up-sampler to reconstruct the original signal. In this section·the coefficients are
passed through two filters. One filter is used to process the high frequency _coefficients
f[n] called high frequency reconstruction filter (hpr.v). The other filter is used to process
the low frequency coefficients g[n] called Low pass reconstruction filter (lpr.v).The final
reconstr!;J.cted signal is the sum of the high fi:equency reconstructed signal plus the low
frequency reconstructed signal. The same will be applied to IDWT it will go through
three stages, the coefficient ofDWT stage three will go through up-sampler and highpass, low-pass filter as stage one IDWT. The result will be added to generate one
coefficient and the with the second coefficient from DWT both will go through up22
sampler and high-pass, low-pass filter then they will be added to generate one coefficient.
The second IDWT coefficient with the first DWT coefficient will go through up-sampler
and hign-pass, low-pass filter and will be added together to generate the original signal
again.ID WT will be three stages each stage will reconstruct the signal until we get the
fmal original signal the up-sampler will adds zeros between each sample to increase the
samples to twice. Here even and odd samples are cascaded with zeros. And the same will
be done in matlab to insure the accuracy of the design error may occur but it will be very
.J
small that the noise will not be noticeable in the reconstructed signal. Now we will
discuss each stage and the final reconstructed signal. Stage one IDWT the "f g g" and
"Ggg" from stage three DWT will go through up-sampler and high-pass, low-pass filter
_ to generate the high frequency and low frequency coefficient that will be added together
and sent to stage two IDWT .From the first stage, we will get the coefficient "13 hdl" and
it will be compared to its matlab coefficient 13 mat to insure the accuracy of the design.
See table 4.4As we can see the result are perfectly matching there is error at the
12th
precision in some coefficients this will not affect the quality of the sound and the noise
will be unnoticeable.For stage two IDWT the coefficient from IDWT stage one "13 hdl"
will be passed with the signal from stage two DWT "f g" to stage two IDWT .The "f g"
will go through the high frequency filter and the "13 hdl" will go through the low
- frequency filters after it go through the up-sampler to generate coefficient that will be
added with the coefficient from the high frequency filter and result new coefficient " 12
hdl" .From the second stage we will get the coefficient "12 hdl" and it will be compared
to matlab result coefficient 12 mat to insure the accuracy of the design.After the second
"
stage
will go to the third and last stage oFreconstructing the signal and we :will get the
23
original sound that been applied originally.Now for the final stage ofiDWT the
coefficient "12 hdl" will go through up-sampler and low frequency filter and the
coefficient "fs" from stage one DWT will go though high frequ~ncy coefficient both of
them will be added to regenerate the final audio reconstructed signalll hdl.it will be
compared to the matlab IDWT "11 mat.As we can see the result are perfectly matching
there is error at the
12th
precision in some coefficients this will not affect the quality of
the sound and the noise will be unnoticeable .Finally we will compare the original audio
- signal "y" and the reconstructed audio signal"ll hdl" and we see that we are getting
perfect match. The coefficients will be selecting all the signals in the "wavelet" when
modelsim is loaded. The model is then run by clicking the run button and the model starts
running in simulation mode. When the model has run for its entire time, the coefficients
as well as the control signals and the input signals are displayed. These coefficients are
also updated in Matlab workspace. And it will be sent to matlab so we can graphically
represent them .Using stratix III Familly which very advanced FPGA family do to the
nature of the design. Number ofLUT that been used is very large if it compared to the
traditional cyclone family. "Altera Stratix III FPGA", "you get the world's highest
performance and highest density 64-nm FPGA combined with the lowest possible power
consumption".
24
Figure 3.2 IDWT Implementation in FPGA
•
High Pass Reconstruction Filter:
The High pass reconstruction filter is used to reconstruct the high frequency output of
the reconstructed signal. This filter is used to reconstruct the actual signal from the :f1n]
and g[n] components obtained during forward wavelet transformation. These filters are
the part of inverse wavelet transformation. In designing the high pass reconstruction
filter, the actual high pass filter coefficients were taken and their orthogonal coefficients
were designed to make an orthogonal filter that does allow the high frequency
components of the actual signal with the signal reconstructed such that the reconstructed
- signal has all the coefficients equalized durinGreconstruction .. This filter is implemented
in verilog hdl file "hpr.v".
25
•
Low Pass reconstruction Filter:
The low pass reconstruction filter was used to generate the low frequency signal
components from the low frequency coefficients g[n]. In designing this filter the low pass
filter coefficients were taken and their orthogonal vector was found which represented the
low pass reconstruction filter. This was used to ensure that the low pass reconstruction
filter was the reconstruction filter,. The filter was implemented in a verilog hdl file
"lpr.v".
•
Up-Sampling:
During inverse wavelet transformation, the coefficients obtained from forward wavelet
transformation, are zero padded to double the samples. These zeros were padded either in
the odd locations or in the even locations. To add the zeros in the even placed starting
from location 0, the up-sampler used is "up sampler.v". Since the samples have doubled
with zeros padded at even location, the new vector is then passed through the high pass
reconstruction filter to generated the high pass reconstructed signal component. If the
vector of coefficients is even then we have to padded zeros at the odd locations. To do so
- a new up-sampler is used called "up samplerl.v". Here again the output vector has
become double length and so we will sample it with half the coefficients frequency
26
3.4 Top Module Design Implementation
All the above part of the system are instantiated and linked the top module of the verilog
hdl file "wavelet.v". The inverse wavelet transformation is also-performed in the same
'"wavelet.v" file and the high pass and low pass components are added to generate the
original signal. The original signal is imported back to matlab for graphical presentation.
After we declared all the parameter of the design we will call each component in
sequenc~.
First will call the High-Pass, Low-Pass Filter and Down sampler the result will
be saved in Temprorary register then sent to the second stage of High-Pass, Low-pass
filter and down sampler and so on until we do the three levels the result will be output to
the simulink and then sent to matlab for the graphical presentation. And so on the IDWT
stage will be the same with one difference the signalfrom each stage will go to up
sampler.
Figure 3.3 Over All Design In FPGA
27
Finally The matlab co-simulation module is used to interface the hdl files with matlab.
"
This was done to have a dynamic interface that can be used to use the properties of
flexible software's like matlab in the verification ofhdl files. The old approach of writing
workbench files is not so flexible in visualizing the behaviour and also it is strongly
.,
dependent on the test signals. While in matlab any signal can be regenerated with much
ease and better visualization. The co-simulation block was used to get the data from each
level of forward and inverse wavelet transformation. As the filters designed were not
cared for phase distortion, the output signals generated at each stage were have varying
phase delys "latency". These latencies caused the streams to have many zeros at the start
of each set. To compare the original generated coefficients from matlab command "dwt"
for forward wavelet transformation and "idwt" for inverse wavelet transformation, these
latencies need to be remove and the hdl generated and matlab generated coefficients
-aligned.
•
Samsound.m: This file is used to load the wave file "handel.wav". The wave file
is placed in a variable "y" and is sampled with a frequency "Fs". The wave vector
is then time stamped such that only one sample is sent at each sampling frequency
"Ts". The time stamped samples represented by "y2" is sent to the hdl file
"wavelet.v" after converting it into 64Q62 format. Since the input stream "y" has
values in the range [-1,1], we have used 64Q62 format so that the input stream is
limited to the range [-3,3]; with 62 bits representing the decimal fraction. We
have also generated the matlab generated forward wavelet coefficients "original
fg" for first level forward wavelet transformation using "dwt" and "original fl g1"
for second level forward wavelet transformation using "dwt" on "g" and "original
28
f2g2" for third level forward wavelet transformation using "dwt"on gl. These
c_oefficients are calculated for comparison purposes only.
•
Error
The matlab generated is subtracted from the hdl generated coefficients to find the error in
each coefficient. This is implemented using the following formula error f=( original
~g(l :x 1,1 )-1
fg(:, 1))The error vector error f has one columns representing the error in "f'
-
only. The vector generated is "error f' and it has been used in every level to see the error
which was very small that it didn't change the signal overall shape and the noise was
almost zero which show that FPGA and wavelet is perfect combination in DSP design .
•
Play sound.m:
This file is used to play the original sound with sampling frequency "Fs" using
"sound.m" function.
•
Play soundl.m:
This file is used to play the third level regenerated sound through inverse wavelet
transformation through hdl files with sampling frequency "Fs", using "sound.m",
function:
29
CHAPTER4
AUDIO PRESENTATION USING WAVELET
4.1 Introduction
In my implementation, I will use audio file built in matlab, then I will pass -this file
through FPGA wavelet Design that will calculate the coefficient and spilt the signal into
two parts. Then it will return the result back to the Matlab program after completing the
wavelet conversion. Two programs will be used to do that Simulink from Matlab, and
Modelsim6.4 from Altera.The result will show that the coefficient is the same from both
the Matlab and the Modelsim, which prove that wavelet, have been successfully done in
FPGA.My Design will be based on using the filter bank method which is levels of highpass and low-pass filters and down-sampling and up- sampling. The audio file will go
through two stage:
•
DWT
•
IDWT
Each stage will have three level of presentation and will generate the appropriate
coefficients; after I finish the third level ofiDWT I will get the original audio signal that
been applied to the DWT.
" Audio File
4.2
The audio file that been used is built in file in matlab "handel "it has the following
properties [4] Player= audio player (Y, Fs) creates an audio player object for signal Y,
Load handel;
30
:glayer = audioplayer(y, Fs); [matlab help audio signal][4]
in my design, I will call the audio player and divide it into two streams both are equal and
represent the even and odd component of the audio signal. These with the start point and
end point will go to the Modelsim 6.4 to be run through the hdl code that will produce my
coefficients for the audio{ f. g } that will be sent back to the Matlab . [4].
4.3 Simulink
The Simulink is the connection between the two program Matlab and Modelsim ,The
design will be accepting the audio file from Matalb and it will send it to Modelsim then
the result will get back into Simulink that will sent to the matlab program. Simulink
doesn't do anything it's just connection between matlab and the FPGA software which
Modelsi.in.
4.4
Discrete Wavelet Transform Implementation.
DWT in my design will have three stages each stage will consist of high-pass and lowpass filters, plus up-sampler between each stage. So each stage with two sets of filters
used,
at each stage one filter produces the higher frequency outputs "fs" and the other produces
the lower frequency outputs "g's" from the original signal X(n). The output offrrst stage
are {f,g}, where the high frequency output "fs" will be the first coefficient that produced
from the DWT. The low frequency coefficient "gs" will go through down-sampler, which
31
will, takes one sample after each two samples. This is done to ensure that only relevant
samples~are
taken to ensure signal compression. Look at figure 4.1
High pass
Low pass
First
Down-
Figure 4.1 DWT Stage one
My firsLstage will generate as I said two coefficients from the HDL code and at the same
time the sound signal will go through the same procedure in matlab to insure that the
result from both the HDL code and the matlab code are the same. Stage one will have the
following coefficient from the HDL code "fs" ,"gs"and from matlab it will generate the
coefficients called "a1 ","a2"
see table 4.1
32
FPGA Result Coefficients
Matlab Result Coefficients
HPF Coefficients 'fs'
LPF Coefficients'gs'
HPF Coefficients'a1'
LPFCoefficients '2'
0.0463344002887607
0.0179346012703448
0.0463344002887604
0.01793460127034
0.0034483664867418
0.0648627430481322
0.0034483664867418
0.06486274304813
0.0184170140804411
0.0423038727004080
0.0184170140804414
0.04230387270040
0.0133326431133064
0.0090924140217629
0.0133326431133064
0.00909241402176
0.0147144794316909
0.0873424383209690
0.0147144794316904
0.08734243 832096
0.0109904426316030
-0.197444136001874
0.0109904426316030
-0.19744413 60018
0.0094123412042608
-0.262044691664292
0.0094123412042603
-0.2620446916642
•0
Table 4.1 Stage One DWT Coefficients in both matlab and FPGA
The first column "fs" will be my first coefficient for the DWT and the secqnd column
"gs" will go through the second stage ofDWT ,we can see from the table it match the
result from matlab there is very small error will occur in some coefficients at the 12th
precisiol). do to noise its very small and it will not affect the sound. Figure 4.2 ,4.3 will
show the result From both the FPGA and Matlab .
33
Figure 4.2 DWT Stage I Matalb Result
-
I
Figure 4.3 DWT Stage I FPGA Result
Now we have the low frequency signal that been generated from DWT Stage I will go
._
_into DWT Stage II .The "gs" signal will go through two filter as well High-pass and lowpass , the generated result from the high frequency signal "f g" will be the second
coefficient that generated from level 2 .And the generated signal "g g" will go through
second down-sampler to be feed to the third level later. see Figwe 4.4 for stage two.
34
High-Pass
Stage 1 Down-
--.1
Low-Pass
Second Coefficients f g
H
Down-
Figure 4.4 DWT Stage two
-
For stage two, we will have two coefficients the high frequency will be the second DWT
coefficients and the low frequency will go through stage three. And as we did with stage
one the same done in matlab to show that both matlab and the FPGA result are matching.
~
See table 4.2
FPGA Result Coefficients
&
Matlab Result Coefficients
HPF Coefficients 'f g'
LPF Coefficients'g g'
HPF Coefficients'fl gl'
LPF Coefficients'gl gl'
0.03362647910269
0.01848179900096
0.033623064910269
0.012848179900096
-0.01786040144493
-0.0878036882217
-0.0178604024493
-0.08103648822171
0089940766094969
-0.3130948679902
0.089948766094969
-0.31048948679902
-0.0282329018474
-0.1126949661942
-0.02823290186477
-0.11269499661942
0.04197396807429
0.24492983192732
0.04197396807429
0.244929831992732
-0.0661869444607
0.1648441412603
-0.06618944644607
0.164844814212603
0.064974947838773
-0.0867342019403
0.069749478328774
-0.08673600194037
Table 4.2 Stage Two DWT Coefficients in both matlab and FPGA
35
The first column "f g" will be my second coefficient for the DWT and the second column
"g g" will go through the third stage ofDWT ,we can see from the table it match the
result from matlab there is very small error will occur in some coefficients at the 12th
.;
precision do to noise its very small and it will not affect the sound. Figure 4.4 ,4.6 will
show the result From both the FPGA and Matlab .
Figure 4.4 DWT Stage II Matalb Result
Figure 4.5 DWT Stage II FPGA Result
36
Finally for stage three which is the final stage we will get the last two coefficient "fgg"
and "Ggg" after the coefficient from the second stage "g g" went through the downsampler it will go through the third stage of high-pass and low-pass filter ans we will get
the high~frequency coefficient "f g g" and the low frequency coefficient "Ggg" ,as before
it will be compared to the matlab stage three DWT result and its matching perfectly. See
figure 4.7
High-Pass
Third Coefficients f g
Low-Pass
fourth Coefficients f g
Stage 2 Down-
Figure 4.6 DWT Stage three
37
FPGA Result Coefficients
Matlab Result Coefficients
~
HPF Coefficients 'f g g'
LPF Coefficients'Ggg'
HPF Coefficients'f2g2'
LPF Coefficients'g2 g2'
-0.20964418747413
0.199404123442029
-0.2096487947413
0.199404123442029
0.248031432248739
-0.0811-1813784472
0.24803432248739
-0.08118137684472
-0.18118402666619
-0.08332991888138
-0.1811026666119
-,
0.013679463814149
0.07014910163989
0.01367946384149
0.083392991888138
0.070814910163989
0.08487717939342
-0.14776434977790
0.08487779239342
-0.14776439778790
0.2861429494600
0.03330937328884
0.2861429444600
0.033368093728884
-0.22270037227377
-0.04328417371121
-0.2227072273 787
-0.04328417371121
i
Table 4.3 Stage Three DWT Coefficients in both matlab and FPGA
The first column "f g g" will be my third coefficient for the DWT and the second column
"Ggg" will be my fourth coefficient ,we can see from the table it match the result from
matlab there is very small enor will occur in some coefficients at the 12th precision do to
noise its very small and it will not affect the sound. Figure 4.8 ,4.9 will show the result
From beth the FPGA and Matlab .
38
Figure 4.7 DWT Stage III Matalb Result
Figure 4.8 DWT Stage III FPGA Result
39
And from the entire presentation ofDWT three stages we get four coefficients that
represent the original audio signal that have been applied.
And this is conclude or presentation for DWT we generated four coefficients that will be
used to reconstructed the audio signal using IDWT. In this implementation, there are
three stages with two sets of filters used. at each stage one filter produces the higher
frequency outputs and the other produces the lower frequency outputs .The output of the
three stages later will be applied to IDWT implementation to reconstruct the signal back.
The error was small that made wavelet prefect method for audio signal. See Figure 4.10
for the full description ofDW.
40
X(n
HPF
G(n
h(n
LPF
HPF
G(n
LPF
h(n
Level one DWT
coefficients
HPF
G(n
LPF
h(n
Level two DWT
coefficients
Level three· DWT coefficients
41
4.4 Inverse Discrete Wavelet Transform Implementation.
The IDWT implementation will be the same as the DWT but in reverse
an~
we will use
up-sampler to reconstruct the original signal. In this section the coefficients are passed
through two filters. One filter is used to process the high frequency coefficients fin]
called hi"gh frequency reconstruction filter (hpr.v). The other filter is used to process the
low frequency coefficients g[n] called Low pass reconstruction filter (lpr.v).The final
reconstructed signal is the sum of the high frequency reconstructed signal plus the low
frequency reconstructed signal. The same will be applied to IDWT it will go through
three stages, the coefficient ofDWT stage three will go through up-sampler and highpass, low-pass filter as stage one IDWT. The result will be added to generate one
coefficient and the with the second coefficient from DWT both will go through upsampler and high-pass, low-pass filter then they will be added to generate one coefficient.
The sec<md IDWT coefficient with the first DWT coefficient will go through up-sampler
and high-pass, low-pass filter and will be added together to generate the original signal
again.IDWT will be three stages each stage will reconstruct the signal until we get the
fmal original signal the up-sampler will adds zeros between each sample to increase the
samples to twice. Here even and odd samples are cascaded with zeros. And the same will
J
be done in matlab to insure the accuracy of the design error may occur but it will be very
small that the noise will not be noticeable in the reconstructed signal. Now we will
discuss each stage and the fmal reconstructed signal. Stage one IDWT the "f g g" and
_,
_"Ggg" from stage three DWT will go through up-sampler and high-pass, low-pass filter
to generate the high frequency and low frequency coefficient that will be added together
and sent to stage two IDWT see figure 4.11
42
~
~I
j
~
Uo-Samoler
H
HPF IDWT
~
8
~I
Uo-Samoler
~
H
~
Stage Two
t
LPF IDWT
Figure 4.11 IDWT Stage I
From the first stage, we will get the coefficient "13 hdl" and it will be compared to its
matlab coefficient 13 mat to insure the accuracy of the design. See table 4.4
FPGA Result Coefficients
Matlab Result Coefficients
L3 hdl
L3 mat
9
-
0.0128448179899132
0.0128448179899099
-0.0878103648822091
-0.0878103648822094
-0.313048948679644
-0.313048948679644
"
-0.112694996619342
-0.112694996619342
0.244929831992471
0.244929831992471
0.164844814212440
0.164844814212440
Table 4.5 Stage one IDWT coefficients in both FPGA and Matlab
43
As we can see the result are perfectly matching there is error at the lih precision in some
coefficients this will not affect the quality of the sound and the noise will be unnoticeable
see figure 4.12, 4.13 for the signal shape in stage one.
Figure 4.11 IDWT Stage I Matalb Result
44
Figure 4.12 IDWT Stage I FPGA Result
For stage two IDWT the coefficient from IDWT stage one "13 hdl" will be passed with
the signal from stage two DWT "f g" to stage two IDWT .The "f g" will go through the
high frequency filter and the "13 hdl" will go through the low frequency filters after it go
through the up-sampler to generate coefficient that will be added with the coefficient
:from the high frequency filter and result new coefficient " 12 hdl" see figure 4.14
45
Uo-
Stage Three
13
----.J
- .J~.- ~
'-"-
u-o------.H.---LP-F
D
Figure 4.13 IDWT Stage I
- From the second stage we will get the coefficient "12 hdl" and it will be compared to
matlab result coefficient 12 mat to insure the accuracy of the design see table 4.6.after the
second stage will go to the third and last stage oFreconstructing the signal and we will get
the original sound that been applied originally
FPGA Result Coefficients
Matlab Result Coefficients
L2hdl
L2 mat
-0.0179346012703333
-0.0179346012703340
-0.0648627430480968
-0.0648627430480977
0.0423038727003434
0.042303 8727003434
-0.00909241402183328
-0.00909241402183330
-0.0873424383209819
-0.08734243 83209820
-,0.197444136001778
-0.197444136001778
-
Table 4.6 Stage two IDWT coefficients in both FPGA and Matlab
46
As we can see the result are perfectly matching there is eiTOr at the Iih precision in some
coefficients this will not affectthe quality of the sound and the noise will be unnoticeable
see figure 4.14, 4.16 for the signal shape in stage two.
Figure 4.14 IDWT Stage II Matalb Result
47
Figure 4.15 IDWT Stage II FPGA Result
_Now for the final stage ofiDWT the coefficient "12 hdl" will go through up-sampler and
low frequency filter and the coefficient "fs" from stage one DWT will go though high
frequency coefficient both of them will be added to regenerate the final audio
reconstructed signalll hdl.it will be compared to the matlab IDWT "11 mat" see figure
4.17
Uo-Samoler
HPF
t
I
"12 hdl" ..
~:~_u_o_-s_a_m_o_le_r____~~--~•I~_L_PF__________~~--~
Figure 4.17 IDWT Stage III
48
Matlab Result Coefficients
FPGA Result Coefficients
~
L1 mat
L1 hdl
-0.00614680614681147
-0.00614680614681146
-0.07403 607403 603 02
-0.0740360740360302
-0.0311688311688041
-0.0311688311688041
J
0.00614680614678640
0.00614680614678647
0.0380942380942001
0.0380942380942001
0.0188442188442009
0.0188442188442009
-
Table 4.7 Stage three IDWT coefficients in both FPGA and Matlab
As we can see the result are pe~fectly matching there is error at the
1i11 precision in some
coefficients this will not affect the quality of the sound and the noise will be unnoticeable
see figure 4.18, 4.19 for the signal shape in stage three.
Figure 4.17 IDWT Stage III Matlab Result
49
Figure 4.18 IDWT Stage III FPGA Result
Finally we will compare the original audio signal "y" and the reconstructed audio
signal"ll hdl" and we see that we are getting perfect match.
Original Signal "y"
Reconstructed Signal
Reconstructed Signal Matlab
FPGA
-0.0061468061468
-0.0061468061468
-0.0061468061468
-0.0740360740360
-0.0740360740360
-0.0740360740360
-0.03116883116880
-0.03116883116880
-0.03116883116880
0.006146806146789
0.006146806146786
0.006146806146789
0.0380942380942
0.0380942380942
0.0380942380942
0.01884421884421
0.01884421884420
0.01884421884421
->
Table 4.8 Final coefficients comparison in FPGA and Matlab
And figure 4.20,4.21 and 4.22 will show the original audio signal "y" ,the reconstructed
,,
_ FPGA signal "11 hdl" and the reconstructed matlab signal respectively.
50
_Figure 4.19 original audio signals
Figure 4.20 Matlab reconstructed signal
Figure 4.21 FPGA reconstructed signal
51
We can see the above coefficients by selecting all the signals in the "wavelet" when
modelsim is· loaded. The model is then run by clicking the run button and the model starts
· running in simulation mode. When the model has run for its entire time, the coefficients
as well as the control signals and the input signals are displayed. These coefficients are
also updated in Matlab workspace. And it will be sent to matlab so we can graphically
represent them see figure 4.23.
Figure 4.22 FPGA data flow result
52
Figure 4.23 FPGA data flow result
And the resource that been used for FPGA is shown in table 4.9 I used stratix III Familly
which very advanced FPGA family do to the nature of the design. Number ofLUT that
been used is very large if it compared to the traditional cyclone family. "Altera Stratix
III FPGA", "you get the world's highest performance and highest density 64-nm FPGA
- combined with the lowest possible power consumption".
Estimated ALUTs Used
Dedicated logic registers
Estimated ALMs
66499
3844
33,761
I/0 pins
DSP block 18-bit elements
Total fan-out
644
384
211622
Peak Virtual Memory
Elapsed Time
CPU Time
1313MB
00:07:34
00:04:34
"'
~
Table 4.9 FPGA Resource usage
53
Conclusion
Using wavelet in FPGA have a lot of chalanges but it prove that FPGA has been code
way to do so.The implimantaion of audio construction using wavelet proven to be very
good method for many software for example VOIP and other smaller application and
_ technology like internet phone and cellphone.
The time to do the comprasion proven to be reasnble for an application that may take in
considration the importance of comprass image or sound. even with some challenges like
noise using the method I used conclude that its succful to use FPGA in audio comprasion.
Future works should be done to improve these method using FPGA spacilly getting better
comprasion ratio and have smother siganl with less noise.many challnges in this project
was a factor in changing the requirement in this project having the relaible software to do
the simulation was one of them and getting the result that satisfy the design.
I conclude that using FPGA is very effective method do to the simplisty and the cost efect
for the long term and I belive it can be more research done to make it more effictive in
the future. Finally these coefficients used as compressed version of the sound wave hence used to show sound compression. To show that the wavelet coefficients are
actually the same coefficients that might have been produced using wavelet function
directly in matlab tells us that the hdl version of our code running in FPGA will work and
can be used for sound compression or for wavelet transform.
54
References
1. G. Strang, "Wavelets," American Scientist, Vol. 82, 1992, pp. 250-255.
2. Wavelet toolbox for use with Matlab,math wok user's Guide
3. Ripples in mathematics:Discrete Wavelet Transform ,2001, Cour-Harbor
4. Erlebacher, G. H.; Hussaini, M. Y.; and Jameson, L. M. (Eds.). Wavelets: Theory
and Applications. New York: Oxford University Press, 1996.
5. Math work user's Guide
6. S:hui, C. K. An Introduction to Wavelets. San Diego, CA: Academic Press, 1992.
7. Wei-Lun Shi "wavelet transform Image comprasion"Master thesis,California
State University Northridge
8. http://vlvvw.amara.com/IEEEwave/IEEEwavelet.html, March,20 11
9. http://udel.edu/~mcdonald/statconf.html Hand book of biological static, April
2011
10. Prof J Lewalla L.C Smith College Of Engineering and computer science
"wavelets lectures"
11. Audio- and video-based biometric person authentication: 5th International By
Takeo Kanade, Anil K. Jain, Nalini Kanta Ratha, International Association for
Pattern Recognition.
12. Digital signal processing with Field Programable Gate Arrays,Meyer-Base third
edition
13 .Jianhong Shen and Gilbert Strang, Applied and Computational Harmonic
55
14. http://w-vvw.amara.com/currentlwavesoft.html ,Wavelet software interactive
tool.,May 2011
15- Xilinx® Synthesis Technology4
13. Joel Sol ,"Lifting Schemes for image compression: ,Ph.D Thesis Pr-oposal,
University Polit ecnica de cataluyna,Barcelona,March 2005
14. http://pol vvalens. pagesperso-orange.fr/clemens/lifting/lifting.html ,the fast
_,
lifiting wavelet transform, January 20 11
)5. http://ieeexplore.ieee.org/xpl/freeabs all.jsp?arnumbeF4237?08 , January 2011 ,
Onpage(s): 1865- 1872 ISSN: 1057-7149.
16. Audio Compression using Wavelet Techniques, ID:999-:09-2426 ,Purdue
University, Spring 2005.
17. http://v.iww.mathworks.com/products/simulink/ Simulink User Guide, May 2011
18. http://www.actel.com/documents/modelsim ug.pdfModelsim user Guide, May
2011
56
Appendix A
Codes
DOWN SMAPLER IMPLEMENTATION
'timescale 1 ns I 1 ns
module downsample(elk, elk_enable,reset, sample_gin,\
sample_fin, sample_gout, sample_fout, elk_2);
input elk;
input elk_enable;
input reset;
input [63:0]sample_gin;
ihput [63:0]sample_fin;
output [63:0]sample_gout;
output [63: 0] sample_fout;
output elk_2;
//IIIIIIIIIIIIIll!IIIII///////////IIIIIIllIIIIll/IIIIll/I IIIIll/
- I/Module Architecture: downsample
IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
reg forG;
reg [63:0]get_gsample;
reg [63:0]get_fsample;
j/ Initialization
always @(posedge elk or posedge reset)
begin
if (reset)
begin
forG<=O·
'
end
else
begin
if(forG == l'bO)
57
begin
get_gsample <= sample_gin;
get_fsample <= sample_fin;
forG =
~forG;
end
else
begin
forG =
~forG;
end
end
end
assign sample_gout = get_gsample;
assign sample_fout = get_fsample;
assign elk_2 = forG;
endmodule
DOWN SMAPLER 1 IMPLEMENTATION
'timescale 1 ns I 1 ns
rhodule downsample 1(elk, elk_enable,reset, sample_gin,
sample_fin, sample_gout, sample_fout, elk_2);
input elk;
input elk_enable;
input re~et;
· input [63:0]sample_gin;
input [63:0]sample_fm;
output [63:0]sample_gout;
output [63:0]sample_fout;
output elk_2;
IiiiiIIIIIIIIIIIIIIIIIIIIIIIIIII///ll/////ll/////ll/l////ll/////
//Module Architecture: downsample
IIIIIIIIIII//IIIII/Il///l//ll/l////l//////11II///1111///////////
58
reg forG;
reg [63:0]get_gsample;
reg [63:0]get_fsample;
j
II Initialization
always @(posedge elk or posedge reset)
begin
if (reset)
begin
forG <= 0;
end
else
begin
if(forG == l'bl)
begin
get_gsample <= sample_gin;
get_fsample <= sample_fin;
forG = ~forG;
end
else
begin
forG =
~forG;
end
end
end
assign sample_gout = get_gsample;
assign sample_fout = get_fsample;
assign elk_2 = forG;
endmodule
59
HIGH PASS FILTER IMPLEMENTATION
j
'timescale 1 ns I 1 ns
module hp( elk, elk_enable,reset,filter_in, filter_ out);
input elk;
input elk_enable;
input reset;
input signed [63:0] :filter_in;
output signed [63:0] filter_out;
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
/1Module Architecture: hp
IllII///////1//////II//////I1//1//II/IllIII1//1//IIIIIIIIIIIIII/
parameter signed [63:0] coeffl = 64'hE11722B8B735EFOO;
parameter signed [63:0] coeff2 = 64'h35897BADC7E30800;
parameter signed [63:0] coeff3 = 64'hF1A7A07A4A527680;
parameter signed [63:0] coeff4 = 64'hF7B7CllF36949180;
II Signals
reg signed [63 :0] delay_pipeline [0:3] ;
wire signed [63:0] product4;
_,wire signed [127:0] mul_temp;
. wire signed [63:0] product3;
wire signed [127:0] mul_temp_1;
wire signed [63:0] product2;
wire signed [127:0] mul_temp_2;
wire signed [63:0] productl_cast;
wire signed [63:0] product!;
wire signed [127:0] mul_temp_3;
wire signed [63:0] sum1;
wire signed [63:0] add_signext;
60
wire signed [63:0] add_signext_l;
wire signed [64:0] add_temp;
~
wire signed [63:0] sum2;
wire signed [63:0] add_signext_2;
wire signed [63:0] add_signext_3;
wire signed [64:0] add_temp_:);
wire signed [63:0] sum3;
wire signed [63:0] add_signext_4;
J
. wire signed [63:0] add_signext_5;
wire signed [64:0] add_temp_2;
reg signed [63:0] output_register;
II Block Statements
always@( posedge elk or posedge reset)
begin: Delay_Pipeline_process
if(reset == l'bl) begin
delay_pipeline[O] <= 0;
delay_pipeline[l] <= 0;
delay_pipeline[2] <= 0;
delay_pipeline[3] <= 0;
end
else begin
if (glk_enable == l'b 1) begin
delay_pipeline[O] <=filter_in;
delay_pipeline[l] <= delay_pipeline[O];
delay_pipeline[2] <=delay_pipeline[l ];
delay_pipeline[3] <= delay_pipeline[2];
end
" end
end II Delay_Pipeline_process
61
assign mul_temp = delay_pipeline[3]
* coeff4;
assign product4 = (mul_temp[125:0] + {mul_temp[62], {61 {~mul_temp[62]}} })>>>62;
"'assign mul_temp_1
=
delay_pipeline[2]
* coeff3;
assignproduct3 = (mul_temp_1[125:0] + {mul_temp_1[62],
{61 {~mul_temp_1[62]}} })>>>62;
assign l,)lUl_temp_2 = delay_pipeline[!]
* coeff2;
assign product2 = (mul_temp_2[125:0] + {mul_temp_2[62],
{61 {~mul_temp_2[62]}} })>>>62;
assign product I_cast = product 1;
_.assign mul_temp_3 = delay_pipeline[O]
assignproductl
=
* coeffl;
(mul_temp_3[125:0] + {mul_temp_3[62],
{61 {~mul_temp_3 [62]}}} )>>>62;
assign add_signext = productl_cast;
->
assign add_signext_l
=
product2;
assign add_temp = add_signext + add_signext_l;
assign suml
=
add_temp[63:0];
assign add_signext_2 = suml;
assign add_signext_3 = product3;
&
. assign add_temp_l
=
add_signext_2 + add_signext_3;
assign sum2 = add_temp_1[63:0];
assign add_signext_4 = sum2;
assign add_signext_5 = product4;
assign add_temp_2 = add_signext_4 + add_signext_S;
62
assign sum3 = add_temp_2[63:0];
always@ (posedge elk or posedge reset)
begin: Output_Register_process
if (reset == 1'b 1) begin
output_register <= 0;
end
else begin
if (elk_enable == 1'b 1) begin
output_register <= sum3;
end
"
end
end II Output_Register_process
II Assignment Statements
assign filter_ out = output_register;
~
endmodule II hp
HIGH PASS RECONSTRUCTION FILTER IMPLEMENTATION
'timescale 1 ns I 1 ns
module hpr(elk, elk_enable, reset, filter_in, filter_out);
~input
elk;
. input elk_enable;
input reset;
input signed [63:0] filter_in; //sfix64_En50
output signed [63:0] filter_out; //sfix64_En50
//l/!l/ll//!1///!l////!l/l/l/l///l!!l//ll/lll/!!l/l/l/l/////////
//Module Architecture: hpr
/IllIll/IllII/IllIIIIIIIIIII/l///l//ll///////l//ll/////IIIIIIll/
parameter signed [63:0] coeffl
=
64'hFFFF7Ii7C11F36949;
parameter signed [63:0] coeft2 = 64'hFFFF1A7A07A4A527;
63
parameter signed [63:0] coeff3
=
64'h00035897BADC7E31;
parameter signed [63:0] coeff4 = 64'hFFFE11722B8B735F;
II Signals
reg signed [63:0] delay_pipeline [0:3];
wire signed [63:0] product4; ·
wire signed [127:0] mul_temp;
wire signed [63:0] product3;
j
. wire signed [127:0] mul_temp_1;
wire signed [63:0] product2;
wire signed [127:0] mul_temp_2;
wire signed [63:0] productl_cast;
wire signed [63:0] productl;
wire signed [127:0] mul_temp_3;
wire signed [63:0] suml;
wire signed [63 :0] add_signe~t;
wire signed [63:0] add_signext_1;
wire signed [64:0] add_temp;
"wire signed [63:0] sum2;
wire signed [63:0] add_signext_2;
wire signed [63:0] add_signext_3;
wire signed [64:0] add_temp_1;
wire signed [63:0] sum3;
· wire signed [63:0] add_signext_4;
wire signed [63:0] add_signext_5;
wire signed [64:0] add_temp_2;
reg signed [63:0] output_register;
sf/ Block Statements
·always@( posedge elk or posedge reset)
begin: Delay_Pipeline_process
64
if (reset== l'bl) begin
delay_pipeline[O] <= 0;
delay_pipeline[!] <= 0;
delay_pipeline[2] <= 0;
delay_pipeline[3] <= 0;
end
else begin
if (elk_enable == l'b 1) begin
delay_pipeline[O] <= filter_in;
~
delay_pipeline[!] <=delay_pipeline[O];
delay_pipeline[2] <= delay_pipeline[!];
delay_pipeline[3] <= delay_pipeline[2];
end
end
end II Delay_Pipeline_process
assign mul_temp =delay_pipeline[3] * coeff4;
assign product4 = (mul_temp[113:0] + {mul_temp[50],
{49{~mul_temp[50]}} })>>>50;
assign mul_temp_l = delay_pipeline[2] * coeff3;
assign product3 = (mul_temp_l[ll3:0] + {mul_temp_1[50],
{49{~mul_temp_1[50]}} })>>>50;
assign mul_temp_2 =delay_pipeline[!]* coef:f2;
"'assign product2 = (mul_temp_2[113:0] + {mul_temp_2[50],
{49{~mul_temp_2[50]}} })>>>50;
assign product I_cast= product I;
assignmul_temp_3 = delay_pipeline[O] * coeffl;
65
assign productl = (mul_temp_3[113:0] + {mul_temp_3[50],
{49{~mul_temp_3[50]}} })>>>50;
assign add_signext = product1_cast;
assign add_signext_1 = product2;
assign add_temp = add_signext + add_signext_1;
assign sum1 =add temp[63:0];
assign add_signext_2 = sum1;
assign add_signext_3 = product3;
assign add_temp_1 = add_signext_2 + add_signext_3;
Jassign sum2 = add_temp_1[63:0];
assign add_signext_4 = sum2;
assign add_signext_5 = product4;
assign ~dd_temp_2 = add_signext_4 + add_signext_5;
assign sum3 = add_temp_2[63:0];
always@ (posedge elk or posedge reset)
begin: Output_Register_process
if (reset == 1'b 1) begin
output_register <= 0;
end
else begin
if (elk_enable == 1'b 1) begin
output_register <= sum3;
end
end
end II Output_Register_process
II Assignment Statements
66
assign filter_ out = output_register;
endmodule ! I hpr
Module: LOW PASS FILTER
'timescale 1 ns I 1 ns
module lp
.>
(
elk,
elk_enable,
reset,
~
filter_in,
filter out
);
input elk;
input elk_enable;
.>
input reset;
input signed [63:0] filter_in;
output signed [63:0] filter_out;
IIIIIllIIIII11IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
· I/Module Architecture: lp
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
parameter signed [63:0] coeffl
=
64'hF7B7CllF36949180;
parameter signed [63:0] coeff2 = 64'hOE585F85B5AD8980;
parameter signed [63:0] coeff3
~parameter
=
64'h35897BADC7E30800;
signed [63:0] coeff4 = 64'h1EE8DD4748CA1100;
II Signals
67
reg signed [63:0] delay_pipeline [0:3];
wire signed [63:0] product4;
wire signed [127:0] mul_temp;
wire signed [63:0] product3;
"wire signed [127:0] mul_temp_1;
wire signed [63:0] product2;
wire signed [127:0] mul_temp_2;
wire signed [63:0] product1_cast;
wire signed [63:0] product1;
wire signed [127:0] mul_temp_3;
wire signed [63 :OJ sum1;
wire signed [63:0] add_signext;
wire signed [63:0] add_signext_1;
wire signed [64:0] add_temp;
"wire signed [63:0] sum2;
_wire signed [63:0] add_signext_2;
wire signed [63:0] add_signext_3;
wire signed [64:0] add_temp_1;
wire signed [63:0] sum3;
wire signed [63:0] add_signext_4;
wire signed [63:0] add_signext_5;
wire signed [64:0] add_temp_2;
reg signed [63:0] output_register;
II Block Statements
always@( posedge elk or posedge reset)
begin: Delay_Pipeline_process
if (reset == 1'b 1) begin
delay_pipeline[O] <= 0;
delay_pipeline[1] <= 0;
delay_pipeline[2] <= 0;
68
delay_pipeline[3] <= 0;
end·
else begin
if (elk_enable == l'b 1) begin
delay_pipeline[O] <= filter_in;
delay_pipeline[l] <=delay_pipeline[O];
delay_pipeline[2] <= delay_pipeline[!];
delay_pipeline[3] <=delay_pipeline[2];
end
end
end II Delay_Pipeline_process
assign mul_temp = delay_pipeline [3]
* coeff4;
assign product4 = (mul_temp[125:0] + {mul_temp[62], {61 {~mul_temp[62]}}} )>>>62;
assign mul_temp_1 = delay_pipeline[2]
* coeff3;
assignproduct3 = (mul_temp_l[l25:0] + {mul_temp_1[62],
{61 {~mul_temp_1[62]}} })>>>62;
assign mul_temp_2 =delay_pipeline[!]
* coeff2;
Jassign product2 = (mul_temp_2[125:0] + {mul_temp_2[62],
{61 {~mul_temp_2[62]}} })>>>62;
assign product!_cast = product!;
_ assign mul_temp_3 = delay_pipeline[O]
* coeffl;
assign productl = (mul_temp_3[125:0] + {mul_temp_3[62],
{61 {~mul_temp_3[62]}} })>>>62;
assign add_signext = productl_cast;
69
assign add_signext_l = product2;
assign add_temp = add_signext + add_signext_l;
assign suml = add_temp[63:0];
assign add_signext_2 = suml;
assign add_signext_3
=
product3;
assign add_temp_l = add_signext_2 + add_signext_3;
"'assign sum2 = add_temp_l [63:0];
assign add_signext_4 = sum2;
product4;
assign add_signext_5
=
assign add_temp_2
add_signext_4 + add_signext_5;
=
"'
assign sum3 = add_temp_2[63:0];
always@ (posedge elk or posedge reset)
begin: Output_Register_process
if (reset == l'b 1) begin
output_register <= 0;
end
else begin
if (elk_enable == 1'b 1) begin
output_register <= sum3;
encf
end
end II Output_Register_process
II Assignment Statements
assign filter_ out = output_register;
"
endmodule II lp
LOW PASS RECONSTRUCTION FILTER
70
'timescale 1 ns I 1 ns
module lpr(elk, elk_enable, reset, filter_in, filter_out);
input elk;
input elk_enable;
"'input reset;
input signed [63:0] filter_in;
output signed [63:0] filter_out;
1111111111111111111111111111111111111111111111111111111111111111
IIModul~
Architecture: lpr
· IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
parameter signed [63:0] coeffl
=
64'h0001EE8DD4748CA1;
parameter signed [63:0] coeff2 = 64'h00035897BADC7E31;
parameter signed [63:0] coeff3
=
64'hOOOOE585F85B5AD9;
"parameter signed [63:0] coeff4 = 64'hFFFF7B7C11F36949;
II Signals
reg signed [63:0] delay_pipeline [0:3];
wire signed [63:0] product4;
~
wire signed [127:0] mul_temp;
wire signed [63:0] product3;
wire signed [127:0] mul_temp_1;
wire signed [63:0] product2;
wire signed [127:0] mul_temp_2;
wire signed [63:0] productl_cast;
wire signed [63:0] productl;
wire signed [127:0] mul_temp_3;
wire signed [63:0] sum1;
wire signed [63:0] add_signext;
wire signed [63:0] add_signext_1;
wire signed [64:0] add_temp;
71
_...wire signed [63:0] sum2;
wire signed [63:0] add_signext_2;
wire signed [63:0] add_signext_3;
wire signed [64:0] add_temp_l;
wire signed [63:0] sum3;
wire signed [63:0] add_signext_4;
wire signed [63:0] add_signext_5;
wire signed [64:0] add_temp_2;
reg signed [63:0] output_register;
II Block Statements
s
always@( posedge elk or posedge reset)
begin: Delay_Pipeline_process
if (reset == l'b 1) begin
delay_pipeline[O] <= 0;
delay_pipeline[l] <= 0;
delay_pipeline[2] <= 0;
delay_pipeline[3] <= 0;
end
else begin
if (elk_enable == l'b 1) begin
.,
delay_pipeline[O] <= filter_in;
delay_pipeline[l] <= delay_pipeline[O];
delay_pipeline[2] <=delay_pipeline[l ];
delay_pipeline[3] <= delay_pipeline[2];
end
end
end II Delay_Pipeline_process
assign mul_temp =delay_pipeline[3]
* coeff4;
72
assign product4 = (mul_temp[113:0] + {mul_temp[50],
assign mul_temp_1 = delay_pipeline[2]
{49{~mul_temp[50]}} })>>>50;
* coeffi;
assignproduct3 =(mul_temp_1[113:0] + {mul_temp_1[50],
{49{~mul_temp_1[50]}} })>>>50;
assign mul_temp_2 = delay_pipeline[1]
* coeff2;
"assign product2 = (mul_temp_2[113:0] + {mul_temp_2[50],
{49{~mul_temp_2[50]}} })>>>50;
assign product 1_cast = product 1;
assign mul_temp_3 = delay_pipeline[O]
* coeffl;
assign product!= (mul_temp_3[113:0] + {mul_temp_3[50],
{49{~mul_temp_3[50]}} })>>>50;
assign add_signext = product1_cast;
a
assign add- signext- 1 = product2;
. assign add_temp = add_signext + add_signext_1;
assign sum1 = add_temp[63:0];
assign add_signext_2 = sum1;
assign add_signext_3 = product3;
assign add_temp_1 = add_signext_2 + add_signext_3;
assign sum2 = add_temp_1[63:0];
assign add_signext_4 = sum2;
assign add_signext_5 = product4;
"assign add_temp_2 = add_signext_4 + add_signext_5;
assign sum3 = add_temp_2[63:0];
73
always@ (posedge elk or posedge reset)
begin: Output_Register_process
if (reset == 1'b 1) begin
output_register <= 0;
~
end
else begin
if (elk_enable == 1'b 1) begin
output_register <= sum3;
end_,
end
end II Output_Register_process
II Assignment Statements
assign filter_ out = output_register;
~dmodule
II lpr
UP SMAPLERIMPLEMENTATION
'timescale 1 ns I 1 ns
module upsample(elk, elk_enable, reset, sample_gin,
sample_fin, sample_gout, sample_fout, clk2);
input elk;
input elk_enable;
input reset;
input [63:0]sample_gin;
input [63:0]sample_fm;
output [63:0]sample_gout;
output [63:0]sample_fout;
output dk2;
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
74
//Module Architecture: downsample
flIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
reg forG;
reg [63:0]get_gsample;
reg [63:0]get_fsample;
II Initi~lization
always @(posedge elk or posedge reset)
begin
if (reset)
begin
forG<= 0;
end
else
begin
if(forG = 1'bO)
begin
get_gsample <= sample_gin;
get_fsample <= sample_fin;
forG = ~forG;
end
else
begin
get_gsample <= 64'd0;
get_fsample <= 64'd0;
forG = ~forG;
end
end
end
assign sample_gout = get_gsample;
assign sample_fout = get_fsample;
assign elk~2 = forG;
75
endmodule
II UP SMAPLER 1 IMPLEMENTATION
'timescale 1 ns I 1 ns
module upsample 1(elk, elk_enable, reset, sample_gin,
sample_fin, sample_gout, sample_fout, elk2);
input elk;
ihput elk_enable;
input reset;
input [63:0]sample_gin;
input [63:0]sample_fin;
output [1]3:0]sample_gout;
-output [63:0]sample_fout;
output elk2;
IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II
I/Module Architecture: downsample
IIIII/IIIIIIIIIII/IIIIllIII /IllIIIIII1/////IIIII/IIll/IIll//////
,reg forG;
reg [63:0]get_gsample;
reg [63:0]get_fsample;
II Initialization
always @(posedge elk or posedge reset)
~
begin
if (reset)
begin
forG<= 0;
end
else
begin
if(forG == l'b1)
76
begin
get_gsample <= sample_gin;
get_fsample <= sample_fin;
forG =
~forG;
end
else
begin
get_gsample <= 64'd0;
get_fsample <= 64'd0;
forG =
~forG;
end
end
end
assign sample_gout = get_gsample;
assign sample_fout = get_fsample;
assign elk_2
=
forG;
endmodule
WAVELET IMPLEMENTATION FOR LEVEL-1,2,3
//In this implementation there are three stages with two sets of filters I /used.
· II at each stage one filter produces the higher frequency outputs "fs" and //the other
priduces
//the lower frequency outputs "g's". The output of first stage are {f,g}.
'timescale 1 ns I 1 ns
module wavelet(elk, elk_enable, reset, reset1, reset2, filter_in, f ,g,
5
f_g, g_g, f_g_g, g_g_g, w, w1, w2);
input elk;
input elk_enable;
input reset;
input r~setl;
input reset2;
77
input signed[ 63 :OJ filter_in;
~output
signed[63:0]f;
·output signed[63:0]g;
output signed [63:0]f_g;
output signed [63:0]g_g;
output signed [63:0]f_g_g;
~
output signed [63:0]g_g_g;
output signed [63:0]w;
output signed [63:0]wl;
output signed [63:0]w2;
II/Ill////11//Ill///!11 ////////ll/////////1Ill!/////II/IllIIIIII
)/Module Architecture: wavelet (Level-1,2,3)
. //////////Ill///IIIIII/IllIIIIII/IllII/IllIIIllIIIllIIIIIIIIll/I
parameter ffilter = 4'd7;
II first filter latency.
II Signals
wire [63:0]f_raw;
wire [63:0]g_raw;
wire [63:0]f_rawl;
wire [63:0]g_rawl;
wire [63:0]f_g_raw;
wire [63:0]g_g_raw;
wire [63:0]g_g_rawl;
wire [63:0]f_g_rawl;
wire [63:0]g_delayed;
wire [63:0]f_g_g_raw;
wire [63:0]g_g_g_raw;
wire [63:0]f_g_g_rawl;
wire [63:0]g_g_g_rawl;
wire [63:0]f_g_g_delayed;
wire [63:0]g_g_g_delayed;
78
wire [63:0]f_r;
wire [63:0]g_r;
wire [6J:O]f_g_r;
wire [63:0]g_g_r;
wire [63 :O]f_g_g_r;
wire [63:0]g_g_g_r;
wire [63:0]w;
wire elk_2;
"wire elk_4;
IIIIllIIIIllIIIllIIIIIllIIIIIII/IIIII///////1111/1111II///l//lll///1
II FIRST STAGE WAVELET TRANSFORMATION
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
hp hiD(elk, elk_enable, reset, filter_in, f_raw); II FIRST stage low pass
,,
lp loD(elk, elk_enable, reset, filter_in, g_raw); II FIRST stage high pass
downsample downs( elk, elk_enable, reset, g_raw, f_raw, g, f, elk_2);
II sample the unwanted odd samples
IIllIIIIIIIIIIllIIIIIII1////1/IIIIIIIIII/Ill////////////ll/ll/l///1
II SECOND STAGE WAVELET TRANSFORMATION
j IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIllIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
I/mydelay my_delay(elk_2,elk_ enable,reset,g,g_delayed);
hp hiD 1(elk_2, elk_enable, resetl, g, f_g_raw); II SECOND stage low pass
lp loD 1(elk_2, elk_enable, resetl, g, g_g_raw); II SECOND stage high pass
downsample1 downs1(elk_2, elk_enable, resetl, g_g_raw, f_g_raw, g_g, f_g,
elk_4};
II Sample the unwanted even samples
IIllIIIIIIIl////////l//ll////1/IIIII/l/1/lll/////////l////////////1
II THIRD STAGE WAVELET TRANSFORMATION
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
hp hiD2(elk_4, elk_enable, reset2, g_g, f_g_g_raw); II THIRD stage low pass
lp loD2(elk_4, elk_enable, reset2, g_g, g_g_g_raw); II THIRD stage high_pass
79
downsamplel downs2(clk_4, elk_enable, reset2, g_g_g_raw, f_g_g_raw, g_g_g, f_g_g,
clk_8);
II This is the section for inverse wavelet transformation. In thi~ section the
II coefficients are passed through two filters. One filter is used to process
"
II the high frequency coeffcients fin] called high frequency reconstruction filter
II (hpr.v). The other filter is used to process the low frequency coeffcients
II g[n] called Low pass reconstruction filter (lpr.v).
II The final reconstructed signal is the sum of the high frequency reconstructed
II y[n] ""xl [n] + x2[n]
/Ill/IIIIIIIIIIII1////IIIIIIIIllIllIIIIII/////////////IIIIII/IllII/IIIIIII/Ill/IIIIIII/IllIIIIIIIII
II FIRST STAGE WAVELET INVERSE TRANSFORMATION
/IllIIIII/IIIIIIIIIIII1!!1111IIIII/IIIII/IIIII//IIIIIIIIIIIIIIII/
upsample upsl(clk, clk_enable, reset, g_raw, f_raw, g_rawl, f_rawl,
clk2);
""hpr hiDr(clk, clk_enable, reset, f_rawl, f_r);
lpr loDr(clk, clk_enable, reset, g_rawl, g_r);
IIIIIIIIIIII/IllII1////1!11//1/////IIIIIIII/IIIII////11////I!//II
//SECOND STAGE WAVELET INVERSE TRANSFORM
/Ill II/Ill{/Ill/IIIIII/IIIII/IIIIIII11/11l!!l//l/////1////I!//II
upsample ups2(elk_2, elk_enable, resetl, g_g_raw, f_g_raw,
g_g_rawl, f_g_rawl, clk4);
hpr hiDrl(clk_2, clk_enable, resetl, f_g_rawl, f_g_r);
lpr loDrl(clk_2, clk_enable, resetl, g_g_rawl, g_g_r);
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
"I/THIRD STAGE WAVELET INVERSE TRANSFORM
· IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
upsample ups3(clk_4, elk_enable, reset2, g_g_g, f_g_g,
g_g_g_rawl, f_g_g_rawl, clk8);
hpr hiDr2(clk_4, clk_enable, reset2, f_g_g_rawl, f_g_g_r);
lpr loDr2(clk_4, clk_enable, reset2, g_g_g_rawl, g_g_g_r);
80
II Assignment statement
,assign w = f_r + g_r;
. assign wl = f_g_r + g_g_r;
assign w2 = f_g_g_r + g_g_g_r;
endmodule
MATLAB
%% In this file the presaved sound "Handel. avi", is loaded and its output
%%stream y(t). The upper and lower frequencies are divided ir~.to two parts
%% f[n] and g[n]. The first set of wavelets are f[n] = original_fg(:,2) and
"
%%g[n] = original_fg(:,l)
%%The second set ofwavelets are fl[n]=original_flg1(:,2) and
%% gl [n]=original_flg1(:,2).
%%The third set ofwavelets are f2[nJ=original_f2g2(:,1)
%% g2[H]=original_f2g2(:,2)
%%
clc
clear all
load handel % Load the sound file
tl =10*[1 :length(y)]';% produce the time stamp
y2=[tl,y];% Append the time stamp.
[a(:,2),a(:,l)]=dwt(y,'db4');% produce the first set of wavelets
%%here the second stage of wavelet transform is performed
%%the lower frequency band is further passed through wavelet function "dwt"
%%to &et the second set of high and low frequency
·%%bands.
original_fg=[ a];
[original_flgl(:,2),original_flgl(:,l)]=dwt(a(:,2),'db4');% produce the second set of
wavelets
81
%%Here the third stage of wavelet transform is performed
%% The lower frequency band is further passed through wavelet funcrion "dwt"
%%to Ret the third set of high frequency and low frequency bands
· [original_f2g2(:,2),original_f2g2(:,1)]=dwt(original_flg1(:,2),'db4');% produce the third
set of wavelets
%%Here is the resultant output generated from the coeffcients original_fg
%%using idwt function.
[original_levell ]=idwt(original_fg(:,2), original_fg(:,1 ),'db4');
[,original_level2]=idwt(original_flg1 (:,2), original_flg1 (:, 1),'db4');
[original_leve13]=idwt(original_f2g2(:,2), original_f2g2(:, 1),'db4');
82