CHALLENGES OF ELECTRICAL MEASUREMENTS
OF ADVANCED GATE DIELECTRICS IN METALOXIDE-SEMICONDUCTOR DEVICES
Eric M. Vogel11 and George A. Brown*
^National Institute of Standards and Technology, Semiconductor Electronics Division
*International SEMATECH
Abstract. Experimental measurements and simulations are used to provide an overview of key issues with the electrical
characterization of metal-oxide-semiconductor (MOS) devices with ultra-thin oxide and alternate gate dielectrics.
Experimental issues associated with the most common electrical characterization method, capacitance-voltage (C-V), are
first described. Issues associated with equivalent oxide thickness extraction and comparison, interface state
measurement, extrinsic defects, and defect generation are then overviewed.
INTRODUCTION
As the lateral feature sizes of Complementary
Metal Oxide Semiconductor (CMOS) Field-EffectTransistors (FETs) are scaled downward, the gate
dielectric capacitance must be increased in order to
keep at least the same drive current. Historically, this
has been accomplished by decreasing the physical
thickness of SiO2. As the thickness of SiO2 moves
towards 1 nm, the gate leakage current becomes
unacceptably high. Therefore, numerous alternate
dielectrics (e.g., ZrO2, HfO2, Hf or Zr silicates, La2O3)
with dielectric constants greater than SiO2 have
recently been under intense investigation [1].
However, these dielectrics have a large number of
technological problems, perhaps the worst of which is
a generally poor interface with silicon.
Both ultra-thin SiO2 and alternate dielectrics pose
numerous problems to MOS device electrical
characterization. The purpose of this overview is not
to provide a discussion of all electrical characterization
methods and gate dielectric parameters of interest.
Instead, the overview presented here highlights issues
with the most common electrical characterization
methods (e.g., C-V) and the most fundamental
parameters of interest (e.g., equivalent oxide thickness
and electrically active defect density in the dielectric).
Experimental issues with C-V measurements are first
presented including measurement errors and
equivalent circuits. Next, issues with extracting and
comparing equivalent oxide thickness from C-V are
presented. Issues associated with extracting interfacial
and near-interfacial electrically active defects are then
presented.
Finally,
issues
associated
with
characterizing extrinsic defects and defect generation
are briefly discussed.
EXPERIMENTAL ISSUES WITH
CAPACITANCE-VOLTAGE
MEASUREMENTS
Measurement Conditions and Errors
Capacitance-voltage has historically been the most
common technique to extract the gate dielectric
parameters such as thickness and interface state
density [2,3]. The most popular method for measuring
capacitance in the 100 Hz to 1 MHz frequency regime
is through the use of an LCR meter which uses a small
ac signal superimposed over a dc bias to measure
capacitance, conductance, and inductance as a function
of dc voltage. In general, the ac voltage used in these
measurements should be kept as small as possible (25
CP683, Characterization and Metrology for VLSI Technology: 2003 International Conference,
edited by D. G. Seiler, A. C. Diebold, T. J. Shaffner, R. McDonald, S. Zollner, R. P. Khosla, and E. M. Secula
2003 American Institute of Physics 0-7354-0152-7/03/$20.00
771
mV to 50 mV) while still allowing accurate
measurement. Niccolian and Brews suggest that the
small signal range is the range over which the
capacitance and conductance are independent of the ac
signal amplitude [3]. An LCR meter can usually
assume that the equivalent capacitance and
conductance of the device under test is either in
parallel or in series. Assuming that device capacitance
is properly extracted from the measured capacitance,
both parallel and series equivalent circuit modes may
be used, since the one can be derived from the other
as:
103
C
=C paralle
D =-
(i)
' parallel
(2)
parallel
where Cseries is the series equivalent capacitance,
Cparaiiei *s tne parallel equivalent capacitance, Gparanei is
the parallel equivalent conductance, and F is the
frequency [4].
The relative measurement accuracy of an LCR
meter depends on the frequency, the ac voltage
amplitude, and the nominal capacitance and
conductance of the device under test. The calculation
for this error is sometimes complex and is usually
given in the meter manual. Since many researchers
use the HP4284A LCR meter*, we have produced a
spreadsheet that calculates its relative measurement
accuracy [4]. Figure 1 shows the relative capacitance
measurement accuracy as a function of frequency for
several values of equivalent parallel capacitance and
conductance. As observed in this figure, the relative
capacitance measurement error increases with
decreasing frequency, increasing conductance, and
decreasing capacitance.
In general, capacitance
measured in a regime where the error is high (e.g.,
dielectric with large leakage current measured at low
frequency) will show noisy behavior. Frequency
dispersion, a turnaround of capacitance with increasing
bias, or negative capacitance is usually not due to the
error of the LCR meter, but is instead due to
equivalent circuit effects which will be discussed later
in this section.
The most popular method for obtaining lowfrequency capacitance is the quasi-static technique in
which the displacement current or charge, associated
with a linear voltage ramp or steps, is measured [2,5].
However, quasi-static techniques cannot be used for
measurements of most advanced gate dielectrics since
the dc leakage current is usually greater than the
772
104
105
106
Frequency (Hz)
FIGURE 1. Relative capacitance measurement accuracy as a
function of frequency for various nominal capacitance (C)
and conductance (G).
displacement current. A low-frequency C-V curve can
be obtained using an LCR meter on a FET. This is
because the source-drain supplies minority carriers at a
rate faster than the measurement frequency. However,
it should be mentioned that this does not produce a
true quasi-static C-V curve. For example, interface
state capacitance will not be truly quasi-static since the
measurement is being performed at some higher
frequency.
Equivalent Circuits
As mentioned above, an LCR meter measures
either a parallel or series equivalent circuit consisting
of, for this discussion, capacitance and conductance.
In the following, a parallel equivalent measurement
circuit, as shown in Fig. 2a, will be assumed. The
actual circuit of the MOS capacitor being measured
contains oxide, gate, substrate, and interface state
capacitance, tunneling and interface state conductance,
and contact resistance [6,7]. A FET is even more
complicated since many of the circuit elements are
distributed across the channel [8]. To simplify this
discussion, a capacitor test structure will be assumed.
In order to extract parameters such as thickness
from C-V measurements, the correct device
capacitance (Cc), as shown in Fig. 2b, must be
extracted from the measured capacitance (Cm). Cc
contains the capacitance associated with the oxide, the
gate electrode, the substrate, etc. Cc can then be used
with theory, models, or simulation to extract
parameters such as oxide thickness. The series
resistance (Rs) and inductance (L0) in Fig. 2b are due
to cabling, contacts, etc and not to the intrinsic MOS
capacitor.
becoming negative. The measured capacitance as a
function of Cc, Gc, Rs, L0, and measurement frequency
in radians (CO) is given as:
^C c (l-o) 2 C c L 0 )-G 2 L 0
X
•0.
: = (G c R s -« 2 C c L 0 +l) 2 +
(a)
0) 2 (C C R S +G C L 0 ) 2
(b)
FIGURE 2. (a) Parallel equivalent measurement circuit, and
(b) corrected circuit.
The correct device conductance (Gc) in Fig. 2b is
conductance intrinsic to the MOS capacitor due to
tunneling, interface states, etc. Each of these terms
may result in deviation of the measured capacitance
from the correct device capacitance.
There are many possible observations associated
with non-ideal C-V (i.e., Cm^Cc). Figure 3a shows a
case where the capacitance measured at some high
frequency shows a simple reduction as compared to
the capacitance measured at a lower frequency. Figure
3b shows cases where the capacitance increases
dramatically or decreases with increasing bias, even
(3)
(4)
Note that the negative signs are only associated
with the inductance, indicating that the negative
capacitance can only be explained by an effective
inductance term. It is unknown whether this series
inductance is due to measurement (e.g., cabling) [9] or
a physical phenomenon [10]. Yang et al. provided a
methodology to correct the measured C-V curve for
series resistance when the capacitance shows
frequency dispersion [11]. Lue et al. recently showed
how to correct C-V including both series resistance
and inductance when the capacitance shows frequency
dispersion [12]. It is possible to observe a strong rollover of capacitance with no frequency dispersion. A
methodology provided in [7] can be used to correct CV measurements that show a strong roll-over with
increasing bias and no frequency dispersion.
600
-3
(a)
(b)
Figure 3. (a) Examples of measured C-V curves indicating a simple reduction in capacitance at high frequency, and (b) roll-over,
increasing, and negative capacitance with increasing bias.
773
ISSUES WITH OXIDE THICKNESS
EXTRACTION AND COMPARISON
1.70
1-65
Impact of Device Parameters
The gate dielectric thickness is the most
fundamental parameter that can be obtained from C-V
measurements. There are two different definitions of
C-V measured oxide thickness that we will be using.
The Equivalent Oxide Thickness (EOT) is obtained
from the gate dielectric capacitance, that is, the
capacitance of the dielectric alone without effects from
substrate, electrode, or defects. The EOT must be
determined from C-V measurements using a fitting or
extraction algorithm that includes quantum mechanical
effects, polysilicon depletion, etc. The Capacitance
Equivalent Thickness (CET) is determined by simply
taking £Si02xArea/Cm where Cm is the capacitance
measured in inversion or accumulation at some
defined voltage. The purpose of the work in this
section is to indicate some issues with extracting a
universal thickness metric. Ideally, one would like to
have a thickness metric that can be used to compare
equivalent dielectric thickness independent of device
parameters (e.g., substrate doping, interface state
density) across various research labs.
To analyze the impact of substrate and gate type
and doping on equivalent thickness, we have simulated
C-V curves with various device parameters and then
used these curves to extract CET. The simulations
were performed using code developed at NIST. The
NIST code quickly provides C-V data including
quantum-mechanical effects, polysilicon depletion,
and interface states. Figure 4 shows the extracted CET
at Vg = -2 V for a nominal EOT of 1.0 nm and various
gate electrodes as a function of substrate doping. It is
observed that the polysilicon doping (1019 cm"3 to 1020
cm"3) and substrate doping density doping (1016 cm"3 to
1018 cm"3) do not have a large impact on the extracted
CET. The capacitance associated with the polysilicon
is approximately independent of doping since the
polysilicon is accumulated. However, the CET is
much different when comparing a polysilicon gate to a
metal gate. This is because of the finite capacitance
associated with the accumulated polysilicon as
compared to the metal gate. The results indicate that,
at the very least, one should state whether the
measurement is performed on a metal or polysilicon
gate when reporting CET measurements.
774
W 1.55
O
1.50
EOT= 1.0 nm
N-channel Device
V = -2 V
Metal
1.45
1.40
1015
1016
1017
1018
1019
3
Nsub(cm- )
FIGURE 4. Extracted CET as a function of substrate doping
(Nsub) for various values of polysilicon doping (Npoiy) and a
metal gate electrode.
The impact of interface state density was
determined by simulating C-V curves with various
levels of interface state density (Dit). Figure 5 shows
the simulated C-V curves for a simple uniform energy
distribution of interface states used (donor below
midgap, acceptor above). The commonly used EOT
extraction code CVC, which was developed by Hauser
[13], was then used to extract the EOT from the
simulated "experimental" curves. The CVC program
can extract EOT from the entire curve or just from the
depletion portion (-1.5 V to -0.5 V).
FIGURE 5. Simulated quasi-static C-V curves with
different values of Dit.
Figure 6 shows -the extracted EOT a a function of
Dit using the entire curve or the depletion portion. The
extracted EOT is observed to be constant (within .03
nm) up to an interface state density of 1012 cm^eV"1
for both extraction cases. A bias is observed between
the "experimental" EOT (~1.0 nm) and the value
extracted by CVC (~1.2 nm). This bias will be
1.5
1.0
o Full Curve Fit
-•— Depletion Portion Fit
0.5
9
10
11
12
-1
13
V g (V)
log(Dit)
FIGURE 6. CVC extracted EOT as a function of the
interface state density.
FIGURE 7. Simulated C-V curves for a variety of different
simulators. The simulators are described within [14].
described in the next section. The results indicate that
interface state density does not strongly impact the
extraction of EOT for oxide or high-K gate dielectrics.
Impact of Simulation/Extraction Code
Simulation or modeling is usually needed in order
to extract EOT from measured C-V data. These
models must include effects such as quantization in the
substrate and polysilicon depletion. There have been
numerous such models and simulators [14]. Figure 7
shows C-V curves for the same nominal device
structure from a variety of different simulators. In
inversion, polysilicon depletion causes each of the
simulators to agree reasonably well. However, the
capacitance in accumulation and the threshold voltage
is observed to vary dramatically depending on the
simulator used. It has been shown that these various
simulators can be different by as much as 0.2 nm.
Possible reasons for these differences include the use
of approximations for quantum effects, wave function
boundary conditions, and type of carrier statistics. The
results indicate that, at the very least, the simulator or
extraction methodology must be indicated when
reporting EOT.
ISSUES WITH INTERFACE STATE
MEASUREMENTS
Historically, the main methods to extract Dit using
capacitance were the low-high frequency method and
the Terman method [2,3]. The low-high frequency
method was based on the difference in quasi-static
capacitance with that measured at high frequency.
However, since quasi-static measurements generally
cannot be performed on advanced dielectrics with
leakage currents, this method can not usually be used.
The Terman method is based on the voltage stretch-out
observed in a high frequency C-V measurement as
compared to a theoretical ideal (no Dit) C-V curve. As
the EOT decreases, the amount of voltage shift
associated with the interface state charge also
decreases as shown in Fig. 8.
10°
io-1
io-2
N ; =10 l u cm z
io-3
io-4
0
4
6
8
EOT (nm)
10
12
FIGURE 8. Voltage shift associated with interface charge
density (Nit) as a function of EOT.
775
The other assumption associated with the Terman
method is that the measured high frequency C-V curve
does not contain appreciable interface state
capacitance. In the C-V simulation code developed at
NIST, we have included the capability of simulating
the frequency response of the interface state
capacitance.
Figure 9 shows a simulated C-V curve for the case
of no Dit, a true (infinite) high-frequency curve
including Dit, and a 1 MHz C-V curve including Dit.
It is observed that the difference between the true
high-frequency C-V curve and the 1 MHz curve is on
the same order of the difference between the no Dit
curve and the 1 MHz curve. The reason is that the
interface state capacitance is small, but non-negligible,
as compared to the voltage stretch-out for small EOT
dielectrics. For thicker dielectrics, the interface state
capacitance would be the same, but the voltage stretchout would be much larger. Since both interface state
capacitance and voltage stretch-out scale with Dit, the
results indicate that the Terman method is not valid for
advanced (small EOT) gate dielectrics. Further work
is required to determine the thickness at which the
Terman method is no longer valid.
2.0
——— NoDit
True HF with Dit
——— F = l MHz with Dit
I 1-5 \
^
«
O
1 r\
1.0
'o
~
Crt
V.J
FIGURE 10. Measured conductance versus gate voltage for
a 2.0 nm SiO2 capacitor for various frequencies.
observed due to interface states. By correcting the
conductance for series resistance and tunneling, the
interface state portion can be isolated. From this, the
interface state density as a function of energy can be
extracted. It has been shown that the interface state
density of ultra-thin SiO2 can be determined down to
approximately 1.5 nm [7]. The Dit of high dielectric
constant materials can usually be extracted easily
using conductance since leakage currents tend to be
smaller and interface state density tends to be larger.
Figure 11 shows the interface state density and the
average interface state time constant as a function of
energy extracted using conductance for two ZrO2 films
and thin (~ 2 nm) SiO2. We have observed this for
many different high dielectric constant dielectrics.
C3
P, A ^
a=10- I4 cm 2
io-3
IO13
0.0
-1.5
-1.0
-0.5
IO12
Zr02-Si3N4
10-4
V B (V)
FIGURE 9. Simulated C-V curves including a dielectric
with no Dit, a true high-frequency curve with Dit, and a 1
MHz curve with Dit.
Since the main methods based on capacitance
cannot be used to determine Dit, other methods are
required. One of the methods that employ a capacitor
test structure is that of AC conductance [2,7]. Figure
10 shows the measured conductance of a thin SiO2
film as a function of gate voltage for several
frequencies. At large negative bias, the conductance is
high due to tunneling. The conductance at high
frequencies is observed to be larger than that at low
frequency. This is due to dispersion caused by series
resistance. In depletion, a peak in the conductance is
776
1011
10-^
1010
io-6
^
Open Symbols:
io-7
9
10
-0.30
-0.25
-0.20 -0.15
E-Ei(eV)
-0.10
-0.05
FIGURE 11. Extracted Dit and interface state time constant
(T) as a function of energy from midgap (E-Ej).
The interface state time constant is inversely
proportional to the capture cross-section of the defect
[2]. The results suggest that the dominant interface
state for high dielectric constant dielectrics is the same
as that of SiO2. This is likely because most high
dielectric constant dielectrics have a layer of SiO2 at
the interface.
-2.0
(a)
(b)
FIGURE 12. (a) Current measured during CP (Imeas), and (b) CP current corrected for leakage (Icp).
Charge pumping (CP) is the other main method to
extract interface state density [15]. However, CP
requires a FET test structure. In CP, a pulse is applied
to the gate of the transistor, and the resulting substrate
current is measured. The peak of this current with the
pulse base level is proportional to the interface or nearinterface state density. For advanced dielectrics with
moderate leakage current, the leakage current adds to
the measured CP current [16]. The correct CP current
can be obtained by subtracting a low frequency curve,
which is dominated by leakage as shown in Fig. 12.
For dielectrics with high leakage current,
modifications to this standard method are required
[17].
Charge-pumping can also provide information on
the spatial (into the dielectric) distribution of defects.
Modeling by Weintraub et al. [18] has shown that a
gate dielectric stack consisting of fast interface states,
slow states in the interfacial region, and slow states in
the bulk dielectric result in a significantly modified CP
current versus base level curve as compared to the case
of pure fast interface states.
The frequency
dependence of the extracted defect density can also
give semi-quantitative information regarding the
spatial distribution of defects [19]. Defect density
measured at low frequency contains defects further
into the bulk of the dielectric as compared to that at
high frequency.
ISSUES WITH CHARACTERIZING
EXTRINSIC DEFECT DENSITY
Traditionally, extrinsic defect density in gate
dielectrics has been measured by identifying
abnormally low breakdown voltage in arrays of MOS
capacitors incorporating the dielectric film. These
abnormal breakdown voltages are detected by either
ramp voltage breakdown testing, which measures the
low breakdown voltage directly, or by constant current
stress, where the low breakdown is associated with a
time-to-breakdown that is shorter than those of the
bulk of the distribution. Once these low or early
breakdowns are identified, the yield of 'good' devices
may be calculated and a defect density computed using
the known area of the capacitors being tested.
For the low defect densities required by modern
device technology, large areas of the gate dielectric
777
must be tested, which implies use of large area
capacitors. In the case of ultra-thin oxides or scaled
high-k dielectrics, these large areas lead to highly
conductive samples, and it is found that breakdown of
these structures is often difficult to measure
accurately. There may be several reasons for this. The
relatively high series resistance of the capacitor
substrate can lead to significant voltage drops,
reducing the voltage appearing across the dielectric
below that of the supply voltage. Another reason is
simply because the conductivity of the breakdown site
is not sufficiently lower than that of the large area
capacitor to make a resolvable difference in its
current-voltage characteristics.
It has been observed in these cases of ultra-thin
oxides or high-k dielectric stacks that extrinsic defects
most often have the effect of increasing the entire I-V
characteristic of the defective capacitor instead of only
changing its breakdown voltage. This is illustrated in
Fig. 13, which is a plot of 52 I-V characteristics of
high-k capacitors having an area of 5.0xlO~3 cm2, all
measured on a single wafer. It is seen that about 35 of
measurements on several other arrays of capacitors on
this test wafer are shown in Fig. 14, in which the
yields determined from this data are plotted versus
capacitor area. It is seen that yield decreases as
capacitor area increases, as would be expected. In
fact, the solid curve plotted over the data points is a
Poisson distribution, following the dependence
= exp(-DA)
(5)
where Y is the yield of good capacitors in a given
array, A is the area of the capacitors in the individual
array [cm ], and D is the extrinsic defect density [cm"
2
]. It is seen that the Poisson distribution provides a
good description of the yield data collected on the test
wafer, leading to specification of an extrinsic defect
density of 60 defects/cm2.
them are all very tightly grouped, while defective units
have a wide variety of higher current values, all more
than an order of magnitude higher than the group.
Definition of a yield criterion is very straightforward
in this case, as well as in most cases observed for these
films, and this criterion is indicated on the I-V plot of
Fig. 13. A yield of 71% is thus derived for this
distribution, and given the known area, sufficient
information is present to allow computation of a defect
density.
Measured Parameter: Gate Current at Vg = -2 V
52 units/sample area
Defect Density = 60 /cm2
lo-6
io-5
Area (cm2)
FIGURE 14. Capacitor yield data as a function of capacitor
area together with a Poisson statistical model for defect
density determination.
Measurements of this type have been made on a
number of wafers with high-k films including those
deposited by MOCVD and ALD techniques, as well as
combinations of the two, with defect densities ranging
FIGURE 13. Current-voltage characteristics of 52 units for
extrinsic defect density determination.
A more strongly based calculation is possible by
making similar measurements on other capacitor
arrays of different area on the same wafer. The test
patterns used in these studies contain 14 such arrays,
having areas varying from l.OxlO"6 cm2 to 0.1 cm2,
providing sets of areas sufficient for resolution of a
wide range of defect densities. Results of such
778
from about 1.0 /cm2 to 2.2xl04/cm2. While no clear
relationship between process technology and defect
density has been uncovered so far, it is clear that
extrinsic defect density is parameter that must be
included in any complete characterization of high-k
films. It appears that it is likely to be a more serious
limitation for these materials than it has become for
silicon oxide or oxynitride.
ISSUES WITH CHARACTERIZING
DEFECT GENERATION AND
RELIABILITY
Defect generation and reliability of advanced gate
dielectrics during electrical stress is an extremely
important aspect of their technological viability.
Defect generation and reliability of ultra-thin SiO2 has
been intensely studied and discussed over the last
1
several years [20]. Therefore, the focus here will be to
indicate several main issues associated with defect
generation and reliability of alternate dielectrics.
Figure 15(a) shows a constant voltage stress Qbd
Weibull plot for approximately 30 MOS capacitors
having a ZrO2 gate dielectric. A large extrinsic tail is
observed.
1012
Symbols: Experiment
Line: Theory (P=2,T)=103 C/cm2)
EOT = 1.2 nm, p-type Capacitor
Prior to Breakdown
0
ZrO2
A = 4xlO"4cm2
-2
Initial
-3
10
100
1000
10000
1011
-0.25
CUC/cm2)
-0.20 -0.15 -0.10 -0.05
0.00
Ef-Ej (eV)
(a)
(b)
FIGURE 15. (a) Qbd Weibull plot, and (b) Dit measured on a fresh device and immediately prior to breakdown for MOS
capacitors with ZrO2 gate dielectric under constant voltage stress.
Although the number of devices used for this
example is not large enough to obtain an accurate
Weibull slope value, the intrinsic portion of the
distribution suggests a Weibull slope of approximately
2. It has been conjectured that the large physical
thickness of high dielectric constant gate dielectrics
may result in large Weibull slopes. Figure 15(b)
shows the Dit measured using conductance for a fresh
capacitor and immediately prior to breakdown. The
number of interface states at breakdown is very high
and correlates with the large value of the Weibull
slope. There are obviously many issues associated
with breakdown of alternate dielectrics that still need
to be understood. However, the potential large defect
density at breakdown for alternate dielectrics suggests
that device parameter drift will likely be a more
important issue for alternate dielectrics than dielectric
breakdown. One of the largest differences between
SiO2 and most alternate dielectrics is that SiO2 is quite
uniform in composition, and electrical and physical
properties, as compared to most alternate dielectric
stacks. Figures 16(a) and 16(b) show the generation of
near-interfacial defects measured using CP at different
measurement frequencies as a function of stress time
for ZrO2 and SiO2, respectively. The rate of defect
generation in SiO2 is observed to be similar for
different measurement frequencies, indicating that the
rate of defect generation is approximately independent
of distance into the dielectric. However, the rate of
defect generation in ZrO2 is observed to have a strong
dependence on CP measurement frequency, indicating
a strong dependence on distance into the dielectric.
Specifically, the rate of defect generation further into
the bulk (low frequency) is observed to be larger than
that nearer the interface (high frequency). The results
indicate that fundamental understanding of defect
generation in alternate dielectric stacks will require
characterization techniques that can probe defects as a
function of distance into the dielectric. Furthermore,
this non-uniform defect generation may have a strong
impact
on
dielectric
breakdown
[21].
779
10°
10°
2.0 nm SiO
1
io-
io-1
io-3
io-2
io-4 6 5 4 3 2 1
io- io- io- io- io- io- 10° io1 io2 io3
io-3
io-6 io-5 io-4 io-3 io-2 io-1 10° io1 io2
Time (s)
Time (s)
(a)
(b)
FIGURE 16. (a) Relative increase in interfacial state density measured using CP at different frequencies as a function of time
under constant voltage stress for FETs having (a) ZrC>2 and (b) SiO2 gate dielectrics.
SUMMARY
An overview of the most common electrical
characterization methods (e.g., C-V) and the most
fundamental parameters of interest (e.g., equivalent
oxide thickness and electrically active defect density in
the dielectric) indicates a number of important issues.
Measurement, equivalent circuit, and analysis issues
complicate C-V measurements of advanced dielectrics.
EOT and CET extracted from C-V were shown to be
insensitive to most device parameters. C-V cannot be
used to extract Dit for low EOT dielectrics. Methods
such as conductance and charge pumping are required.
Defect generation and parameter shift may be
important issues in alternate dielectrics. Electrical
characterization of advanced gate dielectrics poses
numerous
challenges.
Further
fundamental
understanding of advanced gate dielectrics and
development of characterization techniques is
required.
that the materials or equipment identified are
necessarily the best available for the purpose. The
authors would like to thank NIST and SEMATECH
Inc. for financial support, and C. Richter, J. Suehle, D.
Heh, C. Weintraub, P. Hung, C. Young, and J. Han for
discussion.
REFERENCES
1. see e.g. R. M. Wallace, and G. Wilk, MRS Bulletin 27,
192-196(2002).
2. E. H. Nicollian and J. R. Brews, MOS Physics and
Technology, Wiley-Interscience, New York, 1982.
3. E. M. Vogel and V. Misra, "MOS Device
Characterization," in Handbook of Silicon Semiconductor
Metrology, edited by A. Diebold, Marcel Dekker, New
York, 2001, pp. 59-96.
4. Operation Manual for Model HP4284A Precision LCR
M^er, Hewlett-Packard, 1988.
5. Model 595 Quasistatic CV Meter Instruction Manual,
Keithley, 1986.
ACKNOWLEDGEMENTS
Contribution of the National Institute of Standards
and Technology is not subject to U.S. Copyright.
Certain commercial equipment, instruments, or
materials are identified in this paper in order to specify
the experimental procedure adequately. Such
identification is not intended to imply recommendation
or endorsement by the National Institute of Standards
and Technology or SEMATECH, Inc. d/b/a
International SEMATECH, nor is it intended to imply
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