Critical Dimension Calibration Standards for ULSI Metrology1^
Richard A. Alien1, Michael W. Cresswell1, Christine E. Murabito1,
Ronald G. Dixson2'3, and E. Hal Bogardus3
Semiconductor Electronic Division, National Institute of Standards and Technology, Gaithersburg, MD 20899, USA
'Precision Engineering Division, National Institute of Standards and Technology, Gaithersburg, MD 20899, USA
International SEMATECH, 2706Montopolis Drive, Austin, TX 78741, USA
Abstract. NIST and International SEMATECH are developing single-crystal reference materials
for use in evaluating and calibrating critical dimension (CD) metrology tools. Primary calibration
of these reference materials uses a high-resolution transmission electron microscopy (HRTEM)
image of the cross section of the feature at sufficient magnification to resolve and count the
individual lattice planes; the transfer calibration is provided by complementary metrology
techniques. In previous work, electrical test structure metrology served as the transfer metrology.
Recent work has centered on evaluating the performance of these CD reference materials in the
metrology tools which we expect will comprise the bulk of their usage: the critical dimension
scanning electron microscope (CD-SEM) and atomic force microscope (AFM). In particular, a
critical dimension AFM (CD-AFM) is particularly useful. This technique uses flared tips and
two-dimensional feedback to allow scanning of near-vertical sidewalls. It is currently expected
that CD-AFM will serve as an additional transfer calibration technique. Additionally, since earlier
samples showed a high variability in the appearance of the samples, additional screening using the
CD-SEM and AFM will provide significant improvement to verify that each device meets minimal
uniformity characteristics.
Key words: CD Reference Materials; Linewidth Metrology; Calibration; Atomic Force
Microscopy (AFM); Scanning Electron Microscopy (SEM).
BACKGROUND
The National Institute of Standards and
Technology (NIST) and International SEMATECH
(ISMT) are developing single-crystal reference
materials for use in evaluating and calibrating critical
dimension (CD), that is linewidth, metrology tools.1
Prior work has focused on the primary calibration of
these reference materials, via high-resolution
transmission electron microscopy (HRTEM) imaging of
the cross section of a feature at sufficient magnification
to resolve and count the individual lattice planes and the
transfer calibration by electrical test structure metrology
techniques.2'3 In this previous work, we demonstrated
total uncertainties in the range of 14 nm. Although
these uncertainties were better than had been reported
before, they still do not reach the target values specified
in The International Technology Roadmap for
Semiconductors: 2002 Update.4 In this paper, we will
discuss our current emphasis in this project: reporting
preliminary findings on the use of CD-AFM metrology
for transfer calibration. In addition, we describe
selected pattern-transfer process innovations that appear
to enhance the quality of the reference features as well
as recent work in which we evaluate the performance of
these CD reference materials in the metrology tools
which we expect will comprise the bulk of their usage.
These tools are the critical dimension scanning electron
microscope (CD-SEM) and the atomic force
microscope (AFM). The SEM is widely used for
Official Contribution of the National Institute of Standards and Technology; not subject to copyright in the
United States.
CP683, Characterization and Metrology for ULSI Technology: 2003 International Conference,
edited by D. G. Seiler, A. C. Diebold, T. J. Shaffner, R. McDonald, S. Zollner, R. P. Khosla, and E. M. Secula
2003 American Institute of Physics 0-7354-0152-7/03/$20.00
421
in
of a
tip
In Una
Figure 1. Example of "necking" effect near voltage tap.
Figure 2. Example of step change in linewidth.
monitoring the CDs of features in photoresist after each
lithography step. AFMs are used to monitor CD, step
height, and, in the case of boot-tip AFMs, cross section
of final patterned features without cleaving the feature.
Initial results show a strong correlation between the
profiles of the lines derived using the different
metrology techniques. Improvements provided by the
additional screening using SEM and AFM will also be
described.
extensive screening has been undertaken, with the goal
of quantifying these contamination and edge effects as
well as ensuring that no chips are distributed to end
users which exhibit these effects.
It is important to note that these two issues —
minor contamination due to redeposition and steps
along the edges — generally do not present a problem
when this etch process is used to produce MEMS
(MicroElectroMechanical Systems) devices. MEMS
devices tend to have significantly larger minimum size
features than the CD reference materials: 2 |im as
compared to 100 nm. Further, when producing MEMS
devices, the anisotropic etch is typically used to locally
remove silicon lying directly beneath structures
patterned in metal and/or insulators on the silicon
surface. For this application, therefore, the planarity of
the sidewalls beneath the "released" structures is
generally of little concern.
Previous etching had focused on producing the
base structures by using a lattice-plane selective etch
which results in features with edges aligned to the
crystal planes of the silicon. As more imaging
inspections were undertaken, two types of etch artifacts
were observed on the sidewalls of the features:
"necking" and "steps." Figure 1 shows necking, which
has been seen on a number of samples and occurs in the
region near the voltage tap. This effect can be quite
pronounced, but generally does not affect the
uniformity of the regions away from the voltage taps.
The second effect is abrupt transitions in width at a
random location along the feature ("step"); such as is
shown in Figure 2. In the region around the step, the
width is otherwise uniform. The source of these two
etch artifacts was hypothesized to be air bubbles
sticking to the corners or edges during the etch process
(TMAH and KOH both generate significant numbers of
bubbles during the pattern-transfer etch). These
PROCESSING
Earlier work has focused on demonstrating
prototype CD reference material and verifying which
processes would, in general, provide the best results.1'5'6
As these issues were solved and samples evaluated by
different metrology tools, two other issues were
identified:
1) Lines edges may not always be straight; this
was typically seen as steps along the feature, with
the ends of a line segment being wider than the
middle. The steps — which occur randomly along
the line — range in size from 1 nm to 10 nm while
the lines can widen by up to 20 nm within one
micrometer of the voltage tap intersection. Pictures
of lines showing these effects can be seen in
Figures 1 and 2.
2) Contamination, including that deposited either
during the etch process or by SEM, causes
difficulty in determining the edges of the lines.
In the earlier work, there had been optical and/or SEM
screening of a limited sample from the total number of
chips. This limited screening was not enough to
quantify the extent of the contamination and edge
effects described above. In the current work, a more
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(a)
(b)
Chemical eorttaminaion
(c)
(d)
Figure 3. Examples of the variety of contamination effects that have been observed on these samples.
bubbles prevent the etchant from reaching the edge of
the line, locally preventing the etching of the features.
A second class of problems was observed on the
etched wafers: contamination apparently resulting from
post-etch deposits of organic material films. This
contamination is observed randomly on chips that were
fabricated alongside chips that did not show any
contamination. Worst-case examples of the observed
contamination are shown in Figure 3.
Since a number of the structures exhibited neither
abrupt width variations nor contamination effects, an
experiment was conceived to see if changing the
process could lead to a higher yield of acceptably
uniform structures. The experimental matrix included
different doping of the surface conductive layer,
SIMOX and bulk isolation of the surface conducting
layer, and different etches. Further the lithography was
done using tools at two different sites. The process
matrix included the following starting wafers and etch
processes:
Bulk Wafers:
75 mm n-type wafers with implanted boron to
provide a 1019 cm"3 p-type surface layer
75 mm and 150 mm p-type wafers with
implanted arsenic to provide a 1019 cm"3 n-type
surface layer
150 mm p-type wafers with a deep implanted
phosphorous layer and a shallow implanted
boron layer to provide a 1019 cm"3 p-type
surface layer
Three etchants were used for the bulk wafers:
TMAH, KOH, and RIE etch of silicon
followed by KOH polish
SIMOX Wafers:
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75 mm and 150 mm p-type
SIMOX and bulk (both ptype and n-type surface
layers) starting material
The device layer of the
SIMOX was implanted with
boron to a doping level of
1019cm-3
Three etchants were used for
the SIMOX wafers: TMAH,
KOH, and KOH followed by
RIE to remove oxide layer to
reduce or eliminate surface
charging during SEM
imaging
Table 1. Optimized process parameters.
Time
Temperature
(°Q
Special
Condition
30 min
23
Ultrasonic
2. DI rinse/blow dry (N2)
45s
23
3. Buffered oxide etch
5s
23
Process Step
1. Isopropyl Alcohol
Next three steps should follow immediately after each other:
4. DI Dip
1s
23
5. TMAH (17%)
immersion
30s
81
Ultrasonic
15 min
23
Ultrasonic
6. DI Rinse
7. Expose chip to atmospheric oxygen for at least 15 minutes. Place chip
in clean Teflon carrier
Two additional variables were
included for all of the wet etch steps:
6 min
8. Transetch-N
183
temperature and use of an ultrasonic
bath during etch. The temperature
9. DI dip
Is
23
was varied between 77 °C and 85 °C.
10. BOB dip
Ultrasonic
The ultrasonic etch was achieved by
5s
23
using a temperature controlled
(extended)
11. DI Rinse
ultrasonic bath filled with deionized
water, into which a beaker of etchant
12. Blow dry
(e.g., TMAH) could be placed for the
duration of the etch. Finally, pre13. Store in vacuum
oven at low power
cleaning steps were investigated: IPA
_______
(isopropyl alcohol) cleaning to
remove any organic contamination
and BOE (buffered oxide etch) dips
specified in Table I.1" Using this combination of
immediately before etch to remove native oxide from
improvements to the chip processing, the instances of
the sidewalls. These two steps were taken to ensure
edge roughness and contamination were seen to be
that the anisotropic etchant would not be required to
lessened; this was observed qualitatively, in the number
remove a surface film before etching the silicon (e.g.,
of lines that could be evaluated without finding either of
the time required for the TMAH to remove surface
these effects. An example of an improved line is shown
films, include silicon dioxide and organics, can vary
in the SEM image in Figure 4; notice that there is
from seconds to minutes; the total TMAH etch time for
neither contamination nor width variation along the
the silicon was less than 20 seconds).
5 |im long feature shown.
Complete etch cycles were performed on both
complete wafers and individual chips. The greatest
effects were seen when comparing results for etch with
and without etching in an ultrasonic bath. A slight
dependence on etch temperature was also observed: the
higher temperatures tended to produce the best
sidewalls, but also tended to remove the narrowest
features. An etch temperature of 81 °C was chosen as a
Certain commercial equipment is identified in
best compromise between these two effects. Two clean
this
paper
to describe the experimental procedure
steps were seen to provide the greatest improvement: an
adequately.
Such identification does not imply
IPA dip before any other processing and a BOE dip
recommendation
or endorsement by the National Institute
directly before etch. The final etch procedure is
of Standards and Technology or International
SEMATECH, nor does it imply that the equipment
identified is necessarily the best available for the purpose.
424
I
Figure 4. Uniform line processed under optimal conditions with
uniform width and no contamination.
Figure 5. Limit to variation of a "clean" line. The numbers on
the line are measurements made by hand by the SEM operator,
using a self-consistent, but non-calibrated scale. The
dimensions shown are nominally in micrometers.
IMAGING METROLOGY TECHNIQUES
Three imaging techniques are used in the
investigation of these samples: reflected-light optical
microscopy, scanning electron microscopy, and atomic
force microscopy. None of these metrology techniques
provides all of the information of interest; further, the
time required to get a meaningful measurement varies
significantly between the techniques.
Reflected-Light Optical Microscopy
Preliminary screening is done using reflected-light
optical microscopy. Optical screening of each chip
allowed rapid determination of the overall quality of the
chip. That is, the optical screening allowed for
identification of a significant percentage of the chips
that, because of process issues, should not be evaluated
further. Additionally, the optical screening yields a list
of features to be investigated further — these are
normally the narrowest features present after
completing the etch — reducing the number of
structures which need to be imaged by the SEM.
Scanning Electron Microscopy
SEM is the most commonly used metrology
technique in semiconductor CD metrology; this is due
to several advantages: SEM can achieve a high
magnification (250 kX+), it can be used on nonconducting layers; e.g., photoresist, and it is generally
nondestructive
However, SEM is significantly slower than optical
metrology; in this project, an hour or more is required
to evaluate five or six features on the three chips that
may simultaneously be placed in the SEM vacuum
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chamber.
Figure 4 shows a SEM micrograph of a feature
approximately 180 nm wide. The SEM was set to
capture the image at the highest possible image capture
resolution — 2560 pixels by 1920 pixels — to allow
width determination on as large of a region of the line
as possible. To further maximize the total length
available for analysis, instead of placing the feature
horizontally in the image, the line was rotated 45° from
the horizontal so it extended from upper-left-hand
corner to lower-right-hand corner in the scan.
From these images, the widths are measured using
a commercial image analysis tool (the line is first
rendered horizontal in software). This tool gives the
width of the line at a number of locations along the line
and can identify subtle width changes. The measured
widths at various points along a single feature are
shown in Figure 5; as can be seen, more widths were
extracted in the region where the width appears to
change slightly; however, the measured width varied
only slightly as can be seen from the measurements on
the image. This process is being automated to screen a
large number of lines and determine which are the best
candidates. The best candidates are determined by a
combination of width, line edge roughness, and surface
contamination of both the field and the feature.
Atomic Force Microscopy
AFM is a technique in which a microscopic probe which may have dimensions down to the nanometer
scale - is scanned across a surface to generate a
topographic map. In conventional (or 1-D) AFM, there
is only feedback in the z-axis. Critical dimension AFM
(CD-AFM) differs from conventional AFM and is
based on technology that was developed by Martin and
Wickramasinghe in the early 90s.7 The operation of a
CD-AFM differs somewhat from a conventional AFM.
The unique aspects of CD-AFM operation are that force
sensing occurs along two axes (one vertical and one
lateral) and that flared or "boot-shaped" tips are used.
This allows imaging of near-vertical sidewalls, which is
not possible with the conical probes used in
conventional AFM. The CD-AFM used in this work is
the Veeco SXM320.
This work takes advantage of prior NIST and
ISMT research to implement CD-AFM as Reference
Measurement System (RMS) for other dimensional
measurements at ISMT.8'9 This involves establishing
both the traceability and uncertainty of measurements
performed with the AFM.
Presently, the standard uncertainties in CD-AFM
measurements are approximately 0.2 % for pitch
measurements, 0.4 % for step height measurements, and
5 nm for linewidth measurements in the sub-micrometer
range.
It should be noted, however, that the
uncertainties will have some dependence on the
particular sample measured and should be evaluated for
each case.
The linewidth uncertainty is of greatest relevance
to this project. The largest component in the linewidth
uncertainty budget is the "zeroth order" correction for
the width of the tip. The tip correction is obtained from
width measurements of a reference site on a "qual
wafer." The tip width correction is derived by
subtracting the "known" value of the reference width
from the apparent width. The methods used for
obtaining the known value has been described by one of
the authors (Dixson) in more detail elsewhere.9 This
prior work describes use of scanning characterizer
samples - which have very sharp or small features - and
performing comparisons with other measurement
techniques.
To date, this correlation has been
demonstrated with a 5 nm standard uncertainty.
It is important to note that the 5 nm standard
uncertainty represents an uncertainty relative to the SI
meter. For some applications, including this project,
the "absolute" uncertainty is of less interest than the
relative uncertainty between two given width
measurements.
This relative uncertainty can be
significantly smaller than 5 nm. It is largely dependent
on the stability of the "zeroth order" tip width correction
(i.e., the rate of tip wear) and the lateral precision of the
tool. For many circumstances, this relative uncertainty
between two width measurements will be on the order
of 1 nm. A long-term monitor history on one of the
previous generation samples at ISMT has shown a
reproducibility at approximately the 1 nm level.9
Currently, we are planning to use AFM to establish
the width values on samples for distribution. This will
be accomplished by measuring a given number of
samples relative to each other using the CD-AFM at
ISMT. Because tip wear between measurements
directly increases the relative uncertainty, it will be
essential to perform measurements on a "monitor"
sample before and after the measurement on every
target sample. After the AFM measurements have been
performed, a subset will be chosen for HRTEM
measurement. The set of AFM and HRTEM values can
then be used to refine the "zeroth order" tip correction
that we are currently using and reduce the uncertainty.
Provided that the sample uniformity is adequate and
that the HRTEM does not introduce any unanticipated
uncertainties, it should be possible to reduce the
uncertainty of the AFM tip correction to the 1 nm level.
Comparative Results
During the course of this project we have
performed some comparisons between AFM and SEM
measurements on the linewidth samples. Figure 6
shows a comparison of CD-AFM and SEM
measurements on the same feature. The width values
from each technique are compared along a 5 [im
segment of the feature. Considering the uncertainties in
both measurements, the absolute agreement is probably
fortuitous. Of greater significance is the observation
that the trends shown by both instruments correlate to
approximately the 2 nm to 3 nm level. Because the
SEM has significantly higher throughput than AFM, it
is important the SEM gives results acceptable for
screening the samples for uniformity, such as can be
observed using the AFM. The figure suggests that the
SEM can be used effectively to pre-screen the samples
for sufficient uniformity.
The sample uniformity is of importance to this
project in two major ways: First, uniformity is a
desirable property of a standard and increases the
ease-of-use for the end user, but — perhaps more
importantly — the non-uniformity increases the
uncertainty of the AFM/HRTEM comparison since it is
difficult to perform the HRTEM measurement at a
specific location on the feature.
The HRTEM
measurement window will be known to approximately
1 |im at best. Consideration of Figure 6 shows that, for
this particular feature, the worst-case error arising from
a 1 |im offset in the TEM and AFM measurement
locations is 10 nm. If this were the best result, it would
present significant difficulties in the AFM/HRTEM
analysis. However, the more uniform chips we have
observed, with non-uniformity over the central section
of the features less than 3 nm, will be acceptable.
426
300
290
280
270
1.0
2.0
3.0
5.0
4.0
Location on Segment (jam)
a
SEM / IMAGE-PRO
•
Calibrated AFM
6.0
Figure 6. Comparison of widths as extracted from a single line using SEM and CD-AFM. Note that approximately the same
variations in the linewidth are seen by both instruments. Since both instruments provide self-consistent, but non-calibrated results,
the overlay between the lines is considered serendipitous. The dimensions on the y-axis are nominally micrometers.
CONCLUSIONS
In this paper, we have described a path for
providing CD reference materials to the semiconductor
industry. These materials are expected to have
uncertainties in the range of a few nanometers, an
improvement over other CD reference materials, such
as chrome-on-glass standards, which have combined
uncertainties on the order of 40 nm, primarily due to
surface roughness.
Our previous work had focused on using electrical
metrology in the calibration procedure. However,
limitations were identified in this work that suggested
that imaging metrology was necessary to ensure that the
features met requirements for minimal contamination
and no steps in width. To achieve the goal of
acceptable sidewalls, it was determined that the process
would have to be improved substantially. This process
improvement was achieved via several modifications to
the TMAH etch procedure developed by the authors
which allow for cleaner and more uniform sidewalls.
In future work, the entire calibration loop will be
demonstrated, using the entire set of metrology
techniques needed for this work: optical, SEM, CDAFM, electrical, and HRTEM. Upon completion of this
demonstration, NIST and ISMT will seek an industrial
partner to produce these CD artifacts in the quantities
desired by the semiconductor industry. As a part of this
demonstration, modifications to the test structure design
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have been made: Widths of the test features have been
chosen to more closely mirror the industry requirements
and a new structure, which is capable of being
measured using an additional technique, scatterometry,
has been added to the design.
ACKNOWLEDGMENTS
The authors would like to thank Laurie Dennig,
Arnold Valdez, Leo Guittierez and colleagues at the
ISMT Failure Analysis Laboratory for their assistance;
Melanie Tuck of Sandia National Laboratories and
Anthony Walton of the University of Edinburgh for
providing the lithography for the two sets of wafers;
Hitachi for assisting in developing the image
acquisition protocol; Kevin Roberson of Leeds
Instruments for assisting in the development of a macro
width extraction using Image-Pro; Colleen Ellenwood
of NIST and Dave Renninger of Sandia for providing
CAD; and Jim Owen III of NIST for electrical
measurement and optical screening. This work was
supported in part by the NIST Office of Microelectronic
Programs and International SEMATECH.
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Dixson, and B.C. Teague, "Recent Developments in
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