Root-Cause Analysis and Statistical Process Control of
Epilayers for SiGe:C Hetero-Structure Bipolar
Transistors
Qianghua Xie*, Erika Duda*, Mike Kottke*, Wentao Qin*, Xiangdong Wang*,
Shifeng Lu*, Martha Erickson*, Heather Kretzschmar+,
Linda Cross +, and Sharon Murphy+
* Process and Materials Characterization Laboratory, Semiconductor Products Sector, Motorola Inc., MD EL
622, 2100 E. Elliot Road, Tempe, Arizona, 85284
+ MOS11, Semiconductor Products Sector, Motorola Inc., MD OE214, 6501 William Cannon Drive West, Austin,
Texas, 78735-8598
Abstract. The SiGe:C hetero-structure bipolar transistor (HBT) has turned into a key technology for wireless
communication. This paper describes various critical analytical techniques to bring up and maintain the SiGe:C epi-process.
Two types of analysis are critical, (1) routine monitoring SiGe base and Si cap thickness, doping dose, Ge composition
profile, and their uniformity across the wafer; and (2) root-cause analysis on problems due to non-optimized process and
variation in process conditions. A transmission electron microscopy (TEM) technique has been developed allowing a
thickness measurement with a reproducibility better than 3 A. Charge-compensated low-energy secondary ion mass
spectrometry (SIMS) using optical conductivity enhancement (OCE) allows a Ge composition measurement to a required
precision of 0.5 at. %.
INTRODUCTION
The SiGe heterojunction bipolar transistor (HBT)
has become an important technology element for a wide
range of applications [1-3]. Motorola has demonstrated a
high performance
SiGe:C HBT for wireless
communication having a f t and fmax of 80 GHz and 115
GHz, respectively [2]. Incorporating carbon in the SiGe
base has enhanced the device design and manufacturing
flexibility by reducing the out-diffusion of the base
boron [4]. One of the challenges for a high yielding
SiGe:C HBT process relies on the successful epi-layer
growth on patterned wafers with other existing devices
and features [1]. Such a BiCMOS integration of the
HBT constrains the SiGe epitaxial process window,
which renders an epi-process more susceptible to the risk
of polycrystalline growth. Additionally, the temperature
and flow uniformity over a wafer impacts the layer
thickness and composition uniformity.
This paper addresses the metrology aspects for the
SiGe epi-process control in order to ensure a shortened
research and development to production cycle and high
manufacturing yield. Two types of analyses are found to
be essential [5], (1) root-cause analysis on non-routine
problems; and (2) routine control of graded SiGe base
thickness, Ge composition profile, and their uniformity
across the wafer. The first has been effective during the
development phase as well as the manufacturing stage.
Epi-layer quality issues, such as poly-crystalline growth,
could be investigated with the identification of the root
causes. This helps us to refine the epi-related process.
The second is critical during the manufacturing stage.
This provides statistical monitoring of thickness, Ge
composition and base doping level over different stages
of the epi-manufacturing. Since the operational
frequency of the HBTs is directly correlated with the
SiGe:C base thickness, Si cap thickness and B-dopant
concentration in the SiGe:C base, the device yield is
impacted by control of these parameters over different
runs as well as uniformity on a single wafer.
EXPERIMENTAL
Si/SiGe/Si HBT structures were grown in a
temperature range of 500-650°C by reduced-pressure
chemical vapor deposition (RPCVD) epitaxial reactors
[9]. For SiGe:C structures, methlysilane (CH3SiH3) was
used as the carbon source. A transmission electron
microscope (TEM) equipped with a field emitting
electron source was employed and operating at 200 kV
was used to image the SiGe hetero-structures. TEM
specimens were prepared by focused ion beam (FIB)
CP683, Characterization and Metrology for VLSI Technology: 2003 International Conference,
edited by D. G. Seiler, A. C. Diebold, T. J. Shaffner, R. McDonald, S. Zollner, R. P. Khosla, and E. M. Secula
© 2003 American Institute of Physics 0-7354-0152-7/03/$20.00
228
standard SiGe:C HBT wafers. Typical SIMS profiles
have been reported elsewhere and have shown the
retardation of B diffusion in the SiGe base by
incorporating carbon [9]. Fig. l(a) is an AFM image
from the surface of a SiGe:C epitaxial layer with a very
small surface roughness (root mean square about 0.1
nm). Fig. 1 (b) is a cross sectional TEM image from a
SiGe:C HBT. Above the Si substrate and buffer layer, a
SiGe base having a graded portion, and a Si cap are
clearly resolved. The specimen was tilted from the [Oil]
azimuth by 3-5°, with the two (400)-type reflections
being equally excited (an exact edge-on geometry). An
intensity line profile was then taken across the layers as
depicted in Fig. l(c) with a few hundred pixels averaged
along any layer to decrease the measurement error. The
profile shows a very sharp transistion from the Si buffer
layer (right) to the SiGe base and a graded intensity
increase at the left side corresponding to the graded SiGe
layer, followed by the Si cap (far left). Defining the
interfaces (e.g. Si/SiGe) at the middle point of the
intensity transition allows a very reproducible thickness
measurement being better than the resolution limit of
TEM (10 A) under such bright field imaging conditions.
The layer thickness was obtained by averaging about 10
images along which a standard deviation (a) was
derived. The standard deviation for the SiGe base
thickness is found to center around 3 A, and ~ 6 A for
the Si-cap.
To illustrate the importance of OCE for SIMS
milling [10] as well as conventional polishing technique.
The throughput of TEM analysis has been greatly
enhanced in recent years, driven by the high demand for
TEM analysis across the semiconductor industry (the
average time for one could be as short as 1.5 hours and
the efficiency maybe further enhanced with the aid of
auto-FIB). This makes TEM a viable and costcompetitive tool for epi-layer quality control. The SIMS
analyses were performed using a quadrupole-based low
energy instrument [9]. Si and SiGe layers having low
residual carrier density could readily acquire electrical
static charge during sputtering for depth profiling. The
electrical static charging distorts the SIMS data
complicating quantitative analyses [11]. A red laser
diode (wavelength 670 nm and a spot size of ~ 2 mm)
has been implemented on our SIMS system for charge
neutralization for resistive samples. This is known as
optical conductivity enhancement (OCE), and allows Ge
composition quantification to a required precision of 0.5
at %. Atomic force microscopy (AFM) images were
obtained on an atomic force microscope in the tapping
mode. The tool has a sub-A height resolution and better
than 10 nm lateral resolution, which ensures reliable
monitoring of surface quality and defect detection. A
scan area of up to 100 jam x 100 jiim is possible.
RESULTS AND DISCUSSIONS
We first discuss SIMS/AFM/TEM data from
10
Si
Si
o
i - Si without OCE
ii -Si with OCE
Hi - Ge without OCE
|/v - Ge with OCE
X
6.0o
U
20
4.02.0-
1
10
I
I
I
20
30
40
Depth (a.u)
1
I
50
1 • • • • i ' • • • r • • • i •' •' i '
10
15
20
25
30
35
Time (min)
FIGURES 1. (a) and (b) are top-view AFM image and cross-sectional TEM image for a representative SiGeC HBT wafer,
respectively, (c) shows an intensity line profile across a SiGebase. Note the clearly defined Si/SiGe interfaces, (d) shows
the Si and Ge SIMS signals with and without OCE.
229
measurements, we depict in Fig. l(d) the SIMS signals
for Si and Ge under both OCE and non-OCE conditions
for a SiGe layer with constant Ge content. Without OCE,
it is clear that both Si and Ge signals are distorted due to
charging effects. With OCE, there are two flat plateaus in
the Si and Ge signals consistent with the expected
profile. For non-OCE conditions, the Ge content can
only be derived using a complex relative sensitivity
factor method (RSF) with sensitivity being calibrated on
reference samples [9, 11]. Under OCE conditions, the
direct ratio of Si and Ge SIMS intensities provides an
accuracy for the Ge content within 0.5 at.% compared to
reference samples measured by other independent
methods, such as Auger electron spectrometry and
Rutherford back-scattering spectrometry (RBS) [6].
SiGe:C HBTs generally have epi-layers grown on
wafers with other devices (such as MOSFET) and other
part of the HBT formed prior to the epi growth (such as
deep trench isolation and local oxidation). One constraint
is that the substrate temperature and time duration used
for the pre-bake under H2 may be limited by the thermal
budget allowed. This coupled with the temperature drift
and non-uniformity on the wafers, in many cases, may
lead to insufficient surface cleaning. One example is
The insert is a high-resolution lattice image taken for the
same sample, indicating localized amorphous areas at the
interfaces having a thickness of about 1-2 atomic layers.
SIMS profiles show a very broad Ge profile, which is a
natural result of the undefined SiGe/Si interface due to
polycrystalline growth. A significant oxygen peak was
observed roughly at the Si buffer and Si substrate
interface, which was not in the good reference sample.
The combined TEM and SIMS data clearly suggest that
insufficient surface pre-cleaning is the cause of the
polycrystalline growth problem. Fine-tuning the preclean and pre-bake processes is expected to make the
process more robust and manufacturable.
Another type of polycrystalline growth was
discovered after the CVD chamber had been used
extensively. The insert of Fig. 3(a) shows a top-down
AFM image from such a wafer revealing a high density
of particles (~109 cm"2) with a height of 20-30 nm. Fig.
3(a) shows a cross-sectional TEM image of the same
wafer, revealing polycrystalline growth starting at the
SiGe base to Si buffer interface. The most likely cause of
the problem is contamination accompanied with the SiGe
growth and thus perhaps is due to the contamination
from GeH4 source. Since the oxygen peak was hardly
visible in the sample, residual surface oxide can be
excluded as the cause. In the end, this polycrystalline
SiGe
Si
layer
m
(a)
0
10
20
30
Poly
at
40
Time (sec)
50
100
150
Depth (a.u)
200
FIGURE 2. (a) is a XTEM image of a wafer having polycrystalline growth from the Si buffer and Si substrate
interface. An amorphous layer is revealed in this area by high
resolution lattice image, (b) depicts the SIMS profile of the
wafer showing distorted Si and Ge profiles, and a high
oxygen peak at the Si buffer layer.
FIGURE 3. (a) is a representative XTEM image showing
poly-crystalline growth starting from SiGe base. The insert is
an AFM image, (b) is a SIMS profile showing low oxygen
inside the epi-structure.
shown in Fig. 2(a), where polycrystalline growth is seen
to start from the Si substrate and Si buffer layer interface.
growth was eliminated after chamber cleaning and
changing the GeH4 gas delivery tubes. The above
230
examples show the power of this type of root-cause
analysis in revealing the weak links in the process flow
and helping to define a good practice to subdue the
effects of such problems.
With establishing the TEM-based thickness
measurement approach, the thickness of various epitaxial
layers is monitored routinely. Shown in Figs. 4(a) to (c)
are the thicknesses of the SiGe base for various runs,
different reactors, and from the center and the edge of
wafers, normalized to the proprietary thickness values
(on the order of hundreds of A). The SiGe base
thicknesses (center and edge) are distributed around a
value about 5% above the nominal value with a standard
deviation of ~ 6%. The Si cap thickness (not shown) at
the center and edge is within 2% of the nominal value
over a range (standard deviation for all the wafers
measured) of 6%. As a general trend, the SiGe base
thickness is greater at the edge, but the Si cap thickness
shows the opposite trend.
Figures 4(d) through (e), show the B dose for wafers
characterized at the center and edge. The B dose again is
normalized to a proprietary value (in the 1013 cm"2
range). The values are centered around 100% and 96% of
the nominal value with a range of -15%. In Fig. 4(f), the
ratio of center/edge values is presented indicating a
slightly higher dose at the center (centered at 1.043).
From SIMS profiles shown in Fig. l(d), the Ge
composition can be also measured (not shown) with the
2
L5
I
1.4-
I
L3
3
ft
1.2
average Ge content being about 2.1% above the intended
Ge content with a range of 6.6%.
The measurements were collected from various
CVD tools and runs under various conditions, such as
standard weekly monitoring, recipe tuning, tool recommissioning and tool qualification. In manufacturing,
the control of these parameters should be within a much
tighter range. The data can be used to tune the epitaxial
growth recipe in many ways, such as (1) tuning the flow
rates (SiH4, GeH4, and B2H6) and flow duration based on
the values of SiGe base, Si cap thickness and B dose; and
(2) adjusting the thermal pattern over the wafers from the
uniformity (center-to-edge). One rather optimistic
observation is that the statistical drifts of the parameters
appear to compensate each other in our process with
regards to the electrical performance. For instance,
thicker-than-expected SiGe (towards the lower operating
frequency end) may be compensated by a higher Ge
content (higher frequency). This is important for
manufacturing, since any increase in tolerance in the
parameters could lead to higher yield of the final product
at a given cost.
SUMMARY
Through several practical examples, we have shown
here how to apply suitable analytical techniques to solve
(b)
(a)
(c)
"
1.1 1
1
0.9
0
10 20 30 40 50 60 0 10
1.41.31.2-
I
0.90.80.7- -i—r
20
0
20 30 40 50 60 0 10 20 30 40 50 60
(f)
(d)
-i—r
40
60
80
20
40
60
80 0
\
20
40
60
80
Wafer numbers
FIGURES 4. (a)-(b) normalized SiGe base thickness at the centers and the edges of the wafers, respectively, (c) shows the ratio
between the SiGe thickness at center versus at the edge, (d)-(e) are the normalized B dose at the centers and the edges sof the
wafers, respectively, (f) shows the ratio of B dose at the centers versus at the edges.
231
epi-related problems during the SiGe:C HBT
development as well as SiGe:C HBT manufacturing.
With a combined TEM and SIMS analysis, two types of
poly-growth have been identified along with the correct
solution being implemented. On the routine
manufacturing side, TEM has been used to monitor the
SiGe base and Si cap thicknesses with reproducibility
better than 1.5%. SIMS has been used to measure the Ge
composition very accurately (<0.5%). From this, we
have demonstrated that TEM and SIMS are viable
techniques for SiGe epi monitoring in manufacturing.
The cost-of-ownership and cycle time for such analysis
have been dramatically reduced in modern
semiconductor Fabs making them viable and critical for
high-yielding manufacturing.
ACKNOWLEDGEMENTS
We are grateful for the support and collaboration of
Motorola's SiGe HBT development and manufacturing
teams. From past to present, including Stefan Zollner,
Shawn Thomas, Rich Gregory, Jill Hildreth, Vilda
Ilderem, Andrew Morton, Sharon Murphy, Mark Zaleski,
Piyush Shah, Rachel Streiff, Laura Contreras, Kari
Noehring, Gordon Tarn, Lorraine Johnston, and Susan
Williamson.
REFERENCES
1.
Harame, D.L., Comfort, J.H., Cressler, J. D., Crabbe, E.F.,
Sun, J.Y. -C., Meyerson, B.S., Tice, T., IEEE
Transactions on Electron Devices, 42, p455 (1995).
2. John, J., Chai, F., Morgan, D., Keller, T., Kirchgessner, J.,
Reuter, R., Rueda, H., Teplik, J., White, J., Wipf, S., and
Zupac, D., Bipolar/BiCMOS Circuits and Technology
Meeting (BCTM), p. 193 (2002).
3. Pantelides, S.T., and Zollner, S., Silicon-GermaniumCarbon Alloys: Growth, Properties, and Applications,
(Taylor&Erancis, New York, 2002).
4. Martin, M.J., Pardo, D., and Velazquez, I.E., Semicond.
Sci. Technol 15, p277 (2000).
5. Prinz, E.J., et al, IEEE Electron Device Letters, 12, p42
(1991).
6. Chen, W. et al, "Wireless Semiconductor Technology:
Related Critical Characterization and Metrology",
presented at 2000 International Conference on
Characterization and Metrology for VLSI Technology.
7. Zollner, S., et al, "In-line optical and x-ray measurements
for manufacturing of HBTs", Workshop on Optical
Characterization of Interfaces: Status and Opportunities,
2000.
8. Zollner, S., Hildreth, J., Liu, R., Zaumseil, P., Weidner,
M., and Tillack, B., J. Appl. Phys. 88, 4102 (2000).
9. Lu, S., Kottke, M., Zollner, S., and Chen, W., in
Characterization and Metrology for VLSI Technology:
2000 International Conference, p672 (2001).
10. Schraub, D.M., and Rai, R.S., in Prog. Crystal Growth
and Characterization, 36, p99 (1998).
11. McPhail, D.S., Dowsett, M.G., and Parker, E.H.C., J.
Appl Phys. 60, 2573 (1986).
232