[ECEN 1400]
Introduction to Digital and Analog Electronics
R. McLeod
HW #5: Digital Logic and Flip Flops
This homework will walk through a specific digital design problem in all its glory that you will then
implement in this weeks lab.
1
Write the Truth Table (10 pts)
Consider a clock that included a feature that would show the month and day. This would be implemented,
presumably, by feeding the output of the hours counter to a day counter which then fed to a month counter. A
complication with this scheme is that (due to various Roman emperors egos) not all months are the same length.
Thus, to decide when to roll over the day counter, you would need to implement a function that knew the number
of days in each month. Here we will implement one portion of that circuit.
Specifically, we will create a circuit that outputs HIGH if a month has 31 days and LOW otherwise. Since
there are 12 months, we will be using a 4 bit month counter and thus have 4 unused states (24-12=16-12=4). Let
the months be numbered from 0 (January) to 11 (December) and write the truth table for the required function,(
f = month has 31 days). Be sure you get this right since every other part of the homework and the lab depends
on it.
Since A represents the least significant bit in the 74161 counter output, the truth table below will correspond
to the labels of the chip pins. Fill in the function f with 0, 1 or X for dont care. Again, double check your
work or you will have every following step wrong.
Grading:
• (0-8 pts) correct value in row 0 to row 11 (0.6 points for each)
• (0-2 pts) correct input in row 12 to row 15
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[ECEN 1400]
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Introduction to Digital and Analog Electronics
R. McLeod
Enter the Truth Table into the Karnaugh Map (5 pts)
Since the input variables are labeled D,C,B,A, its nice to have a Karnaugh map with the inputs labeled in the
same order. One is provided below. Carefully transfer the truth table to the map. Again, double check your
work since each step builds on the previous ones.
Grading:
• (0-5 pts) correct value in each block of the map (0.3 points for each)
3
Find the Minimum Implementation (10 pts)
Circle the groupings of 1s and/or Xs that give the minimum implementation. HINT: You should have 3 terms,
each of which has only two variables (although some of the variables may be inverted).
Grading:
• (3 pts) Circle the blue one
• (3 pts) Circle the red one
• (3 pts) Circle the green one
• (1 pt) Circle all three correctly (combo bonus!)
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[ECEN 1400]
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Introduction to Digital and Analog Electronics
R. McLeod
Write Your Terms as a Boolean Function (5 pts)
Write a function in a sum-of-products form that corresponds to the minimal representation you have found on
your Karnaugh map.
Grading:
• (5 pts) Find the right terms
5
Check your work (5 pts)
Evaluate each of the three product (AND) terms of your function and enter them as separate truth-tables below.
Then sum (OR) these together and confirm that you have implemented your original truth table from part 1.
Note that the dont-care states will now take on real values. Confirm that these are consistent with your Karnaugh
map use of these states.
Grading:
• (5 pts) Inputs on each row are correct
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[ECEN 1400]
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Introduction to Digital and Analog Electronics
R. McLeod
Implement Your Circuit In Multisim (15 pts)
Use a function generator as a clock input and a 74161 counter to generate the sequence 0000 to 1111. Provide
an annotated screenshot of the clock and output in your answer. Implement your circuit using the 74HC 4V
family (CMOS → 74HC 4V) AND, OR and NOT gates, specifically: 74HC04N 4V (NOT), 74HC08N 4V (AND),
74HC32N 4V (OR). Note that this last chip is near the bottom of the component list due to alphabetical ordering.
The inverter (NOT) includes 6 gates and the other chips each include 4 gates. When you place a new gate, you
will be asked if you would like to place a new chip or use an available gate on an existing chip, as is shown below:
Select an existing chip (U1 in this case) each time. You should only need one of each chip (that
is, less than or equal to 6 NOTs, 4 ANDs and 4 ORs). Below is a figure to get you started.
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[ECEN 1400]
Introduction to Digital and Analog Electronics
R. McLeod
Grading:
• (4 pts) Find the correct components (1 point for each (161 counter, or gate, not gate, and gate))
• (0-4 pts) The wiring is correct
• (0-5 pts) The three signals on the oscilloscope are correct (especially within each RCO roll over cycle, it
gives the correct pattern of the output)
• (1 pt) Label the CLK signal correctly
• (1 pt) Label the output correctly
7
Enabled SR Flip Flop
The diagram below is often given as a clocked JK flip flip that will operate on the rising edge of the clock. In this
problem, we will show that this is actually an enabled SR. That is, it is an SR flip flop that only operates when
the enable line is high. A good reference can be found here:
http://www.tutorialspoint.com/computer_logical_organization/sequential_circuits.htm
1. Show that if enable (E) is low (0), that the outputs Q and Q are stable no matter what voltages are on S
and R. Consider both possible outputs states (0,1) and (1,0).
Grading:
• (2.5 pts) Correctly show the output=(0,1) state is stable
• (2.5 pts) Correctly show the output=(1,0) state is stable
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[ECEN 1400]
Introduction to Digital and Analog Electronics
R. McLeod
2. Assume the outputs (Q and Q) = (0,1) and the inputs (S,R) = (1,0). Let the input E initially be 0, then
it changes to 1. What is the stable output state? Show this by writing the values of the intermediate states
(outputs of the 3-input NANDs), Q and Q as a function of time.
Grading:
• (3 pts) Show the state switches to (1,0)
• (2 pts) Run at least two stable cycles to demonstrate stability
• (Note) Depending on assumptions of gate timing, it is possible to get different intermediate states.
3. Why this isnt a JK: Consider the same problems as part b but now the inputs (S,R) = (1,1). Show that
when the Enable line goes high, the outputs are unstable. Remember that the (1,1) input state is what
distinguishes a JK from an SR.
Grading:
• (5 pts) Run enough states to see output changing back and forth.
• (Note) Depending on assumptions of gate timing, it is possible to get different intermediate states.
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