Matakuliah
Tahun
Versi
: H0362/Very Large Scale Integrated Circuits
: 2005
: versi/01
Pertemuan 8
Struktur Logik Gerbang CMOS-VLSI
1
Learning Outcomes
Pada Akhir pertemuan ini,
diharapkan mahasiswa akan dapat
menjelaskan struktur logik gerbang
CMOS-VLSI.
2
Mirror Circuits
Mirror circuits are based on series-parallel
logic gates, but usually faster and have
a more uniform layout
A
F
B
A
0
0
1
1
B
0
1
0
1
F
0
1
1
0
On device
nFET
pFET
pFET
nFET
F=AB
3
Mirror Circuits
VDD
VDD
a
a
b
a
b
ab
a
b
b
Rangkaian
ab
b a
Gnd
Layout
4
Mirror Circuits
Rp
Rp
Rp
Cp
Rp
Cp
Cout
Rn
Rn
Rn
 r  2.2  p
 f  2.2  n
Rn
Cn
 x  Cout (2R x )  Cx R x
Cn
 : time constant
r : rise time
f : fall time
5
Pseudo nMOS
VDD
VSGp +
Pull-up
Load
nFET
Logic
Array
VDD
f
p
Pull-down
VOL
Struktur umum pseudo nMOS
+
-
VDD
n
+
-
Pseudo nMOS inverter
6
Rangkaian Tri-state
En
f
Data
En
f
0
Z
1
Data
VDD
VDD
Mp
Data
En
M1 f
En
M2
En
Data
En
f
Mn
Gnd
Rangkaian CMOS Tri-state
Layout
7
Clocked CMOS
1

1

time
time
0
T
2T
Input valid
VDD
a
b
c
a
b
c
pFET

M1

M2
nFET

f(a, b, c)
Cout
+
-
Hi-Z
Hi-Z
Vout
Struktur clock gerbang CMOS
8
Clocked CMOS
b
a
Mp

M1

M2
a
Mn
VDD

VDD
a.b
Cout
a
b
Out
b
Rangkaian NAND2
Gnd
Layout

9
Dynamic CMOS LOGIC
A dynamic logic gate uses clocking and charge
storage properties of MOSFETs to implement
logic operations
VDD
Mp

a
b
c
d
nFET

f
Cout
Vout
Mn
Basic dynamic gate logic
Precharge
Mp ON
Mn OFF
Evaluate
Mp OFF
Mn ON
Precharge
Mp ON
Mn OFF
T
10
Dynamic CMOS LOGIC
Contoh rangkaian dynamic logik
VDD
Mp
f
Cout
a
VDD
Vout
b
f
c

Mn
Gnd
 a bc
Layout
11
Dual Rail Logic
We have been concentrating on single-rail logic
Circuits where the value of a variables is eiher
a 0 or 1 only. In dual-rail networks, both the
variable x and its complement x are used to
form the difference
fx = (x – x )
12
Dual Rail Logic
VDD
MP1
Vl
Vr
f
f
a
b
c
Latch
MP2
Sw2
Sw1
Logic tree
a
b
c
VDD
Vl
Structure of a CVSL logic gate
Vr
a.b
a.b
a
b
a
b
AND / NAND
13
RESUME
•
•
•
•
•
•
Mirror Circuiuts.
Pseudo nMOS.
Tri-state.
Clocked CMOS.
Dynamic CMOS Logic.
Dual Rail Logic.
14