Matakuliah
Tahun
Versi
: H0362/Very Large Scale Integrated Circuits
: 2005
: versi/01
Pertemuan 6
Element of Physical Design
1
Learning Outcomes
Pada Akhir pertemuan ini,
diharapkan mahasiswa akan dapat
menyebutkan element-element
dalam physiscal design proses VLSI.
2
Basic Concepts
Physical design is the actual process
of creating circuits on silicon.
Polygon in physical design
3
Layout of Basic Structure
Masking sequence
o. Start with p-type substrate
1. nWell
2. Active
3. Poly
4. pSelect
5. nSelect
6. Active contact
7. Poly contact
8. Metal 1
9. Via
10. Metal 2
11. Overglass
4
Layout of Basic Structure
n-well
Snw-nw
n-well
n-well
p-substrate
Cross-section
Wnw
Mask set
Wnw
FOX
Active
Active
Active
Wa
Silicon substrate
Cross-section
Sa-a
Active pattern
5
Layout of Basic Structure
nSelect
n+ regions:
FOX
nSelect
Active
n+
Sa-n
FOX
Wa
p
Sa-n
Cross-section
p+ regions:
Active
nSelect
Sp-nw
Active
FOX
Mask set
p+
n-well
Cross-section
nSelect
Sa-n
Wa
FOX
Sa-n
Sp-nw
Active
Mask set
6
Layout of Basic Structure
Active
nSelect
nFET:
poly
L
poly
n+
W
n+l
p
Cross-section
pFET:
dpo
Mask set
pSelect
L
poly
Active
n-well
poly
p+
W
p+l
n-well
p
Cross-section
dpo
Mask set
7
Layout of Basic Structure
select
Active
Active contact
Active contact
dac, v
Sa-ac
p+
n-well
n+
p
dac, h
Cross-section
Generl mask set
Metal 1
select
Sm1-ac
Ox
Wm1
n+
p
Cross-section
Active
Metal 1
Generl mask set
8
Cell Concepts
Logic gate as basic cells
XNOT
VDD
VDD
in
out
VSS
XNOR2
XNAND2
VSS
VDD
VDD
VDD
in1
in1
out
in2
VSS
VSS
VDD
a
f
b
VSS
out
in2
VSS
VDD
VDD
VSS
2 XNOT + XNAND2
a
f
b
VSS
Primitive cells
New complex cells
9
Cell Concepts
VDD
nWell
pFET
Pm1-m1
Dm1-m1
nFET
p-substrate
VSS
VDD
nWell
horizontal
vertical
VSS
10
Cell Concepts
VDD
D1
nWell
VDD
nWell
D2
VSS
VSS
X2
X1
Vertical FET
Horizontal FET
1
2
3
4
Larger
1
3
2
Smaller
4
11
Cell Concepts
Vertical metal 2
VDD
Logic cells
VSS
Metal 1
wiring
VDD
Logic cells
VSS
Metal 1
wiring
VDD
VSS
Logic cells
12
Cell Concepts
VDD
Logic cells
VSS
Inverted Logic cells
VDD
Logic cells
VSS
Inverted Logic cells
VDD
Metal 2
Weinberger image array
VDD
nWell
pFET
nWell
pFET
VD
D
Metal
input
Metal
output
p-substrate
VSS
p-substrate
VSS
To wiring
channel
Port placement in a cel
nFET
Logic
row
VDD
nWell
pFET
nFE
T
FET placement in Weinberger array
Logic
row
13
Physical Design Logic Gate
NOT GATE
X
X
VDD
VDD
Mp
Mp
X
nWell
X
X
X
Mn
Mn
Gnd
14
RESUME
•
•
•
•
Basic Concepts.
Layout of Basic Structure.
Cell Concepts.
Physical Design Logic Gate.
15