Matakuliah
Tahun
Versi
: H0362/Very Large Scale Integrated Circuits
: 2005
: versi/01
Pertemuan 5
Fabrikasi IC CMOS
1
Learning Outcomes
Pada Akhir pertemuan ini,
diharapkan mahasiswa akan dapat
menyebutkan proses fabrikasiIC
CMOS.
2
IC Fabrication
Sumber: http://mems.cawru.edu/shortcourse/figure/I_2.1.gif
3
Silicon Processing
Diameter
Silicon wafer
Wafer
Die sites
Sumber: http://www.amd.com
4
Material Growth & Deposition
O2 flow
XSi
Silicon oxide
SiO2 layer
Xox
Silicon wafer
Growth phase
Silicon wafer
Final structure
SiO2 molecues
CVD oxide
Substrate
5
IC Layers
Ion source
accelerator
Magnetic mass
separator
Ion implanter
Ion beam
wafer
Silicon nuclei
electron cloud
Ion
Silicon wafer
x
0
6
substrate
After oxide deposition
Glass
poly
poly
Lythography
substrate
After CMP
Pattern on underside
7
Lythography
Photoresist spray
Spinning wafer
Photoresist coating
Vcuum chuck
Resist application
Coated wafer
Edge bead
Edge bead
Flat resist
Wafer
Beading
8
Lythography
UV
Exposure step
Reticle
Projection optics
(not shown)
Reticle
shadow
Resist-coated
Wafer surface
9
Lythography
UV
Reticle
Resist
Wafer
Exposure pattern
Hardened
resist layer
Wafer
After development and rinsing
10
Lythography
Hardened
resist layer
Oxide layer
Substrate
Initial patterning of resist
Pattern oxide layer
Substrate
After etching process
11
Lythography
Arsenic ions
Substrate
Incoming ion beam
n+
n+
Substrate
Doped n-type region
12
CMOS Process Flow
p-epitaxial layer
p+ substrate
a. Starting wafer with epitaxial layer
n-well
p, Na
b. Creation of n-well in p-epitaxial layer
Nitride
n-well
p, Na
d. Silicon etch
FOX
FOX
FOX
FOX
n-well
p, Na
e. Field oxide growth
n-well
p, Na
c. Active area definition using nitride / oxide
n-well
p, Na
f. Surface preparation
13
CMOS Process Flow
poly
n-well
n-well
p, Na
p, Na
b. Gate oxide growthPoly gate deposition
& patterning
a. Gate oxide growth
Arsenic implant
Boron implant
resist
resist
n-well
n-well
p, Na
p, Na
c. pSelect mask and implant
p+ implant
n+ implant
d. nSelect mask and implant
14
CMOS Process Flow
Metal 1
n-well
p, Na
n-well
p, Na
a. After anneal and CVD oxide
W
W
W
W
W
W
c. Metal 1 coating and patterning
Ke pin IC
p, Na
n-well
b. After CVD oxide active contact, W plugs
Overglass
wire
Bond
Metal bonding pad
Bonding pad
15
Design Rules
poly
wp
Sp-p
wp
poly
Wp = minimum width of polysilicon line
Sp-p = minimum poly-topoly spacing
16
RESUME
• IC Fabrication: Flow of process.
• Silicon Processing: wafer, material growth,
deposition.
• Lythography: pattern, photoresist coating,
exposure steps, etching, n-type.
• CMOS Process flow.
• Design rules
17