Matakuliah
Tahun
Versi
: H0362/Very Large Scale Integrated Circuits
: 2005
: versi/01
Pertemuan 7
Karakteristik Kerja Rangkaian Gerbang
CMOS
1
Learning Outcomes
Pada Akhir pertemuan ini,
diharapkan mahasiswa akan dapat
menjelaskan karakteristik kerja
rangkaian logik CMOS-VLSI.
2
Delay Gerbang
VDD
CL
Gate
VSS
+
-
Vout
t
N=4
t
N=3
N=2
tr0
tf0
N=1
CL
Rise time:
tru = tr0 + pu CL
Fall time:
tfu = tf0 + nu CL
CL
N = fan-in gerbang
3
Beban Kapasitip
VDD
p
External load
+
+
Vin
n
-
CL
-
Vout
CL, d = Cin
CMOS Inverter
Large
Cin, d
+
VDD

+
Vin
-

Cin

VDD
Driving gate
-
CL
Large Large
+
Vout
-
Driving a large input capacitance gate

Konsep unit beban
4
Beban Kapasitip
Ci
1
1
R1
3
2
1
VDD
N-1
1
1
tingkat ke j
N
CL
1
+
Vout
-
tingkat ke j+1
Rj ich
j+1
Cj
Rj
idis
Cj+1
j+1
Karakteristik suatu tingkat dalam rangkaian
5
Logical Effort
Logical effort characterizes gates and how
they interact in logic cascades, and provides
techniques to minimize the delay.
VDD
r
Cin = Cref
Cout
1
Cin
g
C ref
Inverter reference untuk logical effort
6
Logical Effort
VDD
Rref
external
Cout
Cp, ref
Rref
Electrical effort h:
Rangkaian delay untuk 1X inverter
C1
1
C2
2
Inverter dua tingkat
C3
C out
h
C in
Path delay is minimized
If h1 = h2
7
BiCMOS Drivers
(C)
(C)
-
Collector
VBC
Base
(B)
(B)
+
VBE
-
n
+
p
+
n+
VBE
Emiter
(E)
Simbol
VBC
-
+
VBC
(E)
Struktur
Reverse
active
bias
Cutoff
Saturation
VBE
0
Forward
active
bias
Daerah kerja
8
BiCMOS Drivers
VDD
Inputs
Q1
Rangkaian
Logik
CMOS
Q2
Cout
+
Vout
-
VDD
Mp
Q1
Rangkain umum BiCMOS driver
M1
+
Vin
-
+
Mn
Cout
Vout
-
Q2
M2
Rangkaian inverter BiCMOS driver
9
BiCMOS Drivers
td
CMOS
BiCMOS
CL
0
Cx
Delay gerbang vs beban kapasitip
10
RESUME
•
•
•
•
Delay Gerbang.
Beban Kapasitip.
Logical Efforts.
BiCMOS Drivers.
11