Matakuliah
Tahun
Versi
: H0362/Very Large Scale Integrated Circuits
: 2005
: versi/01
Pertemuan 4
Physical Structure
1
Learning Outcomes
Pada Akhir pertemuan ini,
diharapkan mahasiswa akan dapat
menunjukkan proses physical design
pada teknologi VLSI.
2
IC Layers
Layer M1
Layer M1
Bentuk fisik
insulator
Substrate
2 materi layers terpisah
Layer M1
Layer M1
insulator
Substrate
Tampak samping
Tampak atas
3
IC Layers
Layer M1
Bentuk fisik
Layer M2
insulator
Layer M1
insulator
Layer M2
Substrate
Tampak atas
Tampak samping
t
x
l
l
y
w
Cross section area A
Geometry conducting line
1 square
w
x
y
Sheet resistance contributions
4
IC Layers
w
ox
Pengaruh capacitancy
l
Substrate
Tox
Geometry untuk menghitung line capacitancy
Next
logik gate
Signal
source
V(t)
Vs(t)
V(t)
Vs(t)
+
Vs(t)
+
Cline
Model rangkaian
-
V(t)
t

Response tegangan
5
MOSFET
Gate layer
Gate
Source layer
Drain layer
nFET layers
No connection
Drain
Source
nFET symbol
Conduction layer
G=0
G=1
Open switch
Closed switch
6
MOSFET
Gate
Source
Layers
Silicon dioxide insulator
w
Drain
L
Silicon wafer
Gate
Gate
Gate oxide
Source
Drain
L
w
Source
Drain
substrate
Tampak samping
Tampak atas
7
MOSFET
Konduksi di silicon
Silicon cristal
Elektron ( -q)
Hole ( +q)
Pembentukan pasangan elektron – hole
pada silicon
I=0
p
p
p
n
n
n
pn junction
Forward current
Reverese current
8
MOSFET
nFET dan pFET
Source
Gate
Drain
Source
Gate
Drain
Metal
n+
n+
p+
p+
n-well
p
p
nFET
pFET
9
MOSFET
Controlling current flow
nFET:
Open switch
0V
n+
p
n+
n+
n+
w
No electron
L
Closed switch
VG positip
+
n+
p
n+
n+
n+
w
electron
Kanal elektron
10
MOSFET
Controlling current flow
pFET:
Open switch
+
p+
n
p+
p+
p+
w
No hole
L
Closed switch
VG negatip
p+
n
p+
p+
p+
w
Hole (+q)
Kanal hole
11
CMOS Layers
Struktur layers
nFET
nFET
pFET
pFET
FOX
Gate
n+
n+
n+
n+
p-substrate
p+
p+
p+
p+
Gate oxide
n-well
Tampak samping
nFET
n+
nFET
n+
n+
n+
pFET
pFET
p+
p+
p+
p+
n-well
12
Tampak atas
CMOS Layers
Metal interconnection
Gate
contact Gate
Metal 2
FET
Ox3
Metal 2
Metal 1
Metal 1
Active
contact
Ox2
Metal 1
Active
contact
Ox1
n+
n+
n+
Metal 1
Contoh interkoneksi layout
n+
p-substrate
13
FET Arrays
Serial Connection
A
A
B
A
B
n+
n+
n+
n+
n+
skematik
A
n+
n+
A
C
n+
Tampak samping
B
C y
y
x
skematik
x
n+
Substrate
Surface patern
B
B
Poly (gate)
n+ / p+
Metal
Contact
Surface patern
14
FET Arrays
Paralel Connection
A
x
x
B
A
B
y
Skematik
y
Surface patern
x
x
B
A
y
Skematik
y
Surface patern
Poly (gate)
n+ / p+
Metal
Contact
15
Gate Arrays
Vdd
NAND gate using gate isolation
Vdd
A
B
PMOS
B
Out
A
Out
NMOS
Gnd
Can in principle be used by adjacent cell
Gnd
16
Gate Arrays
Check and recheck
17
RESUME
• IC Layers: bentuk dan pengaruh
kapasitansi.
• MOSFET: Simbol, layers, nFET, pFET,
controlling current.
• CMOS layers: structure, metal connection.
• FET and Gate arrays.
18