Matakuliah
Tahun
Versi
: H0362/Very Large Scale Integrated Circuits
: 2005
: versi/01
Pertemuan 10
Keandalan danTesting
1
Learning Outcomes
Pada Akhir pertemuan ini,
diharapkan mahasiswa akan dapat
menerapkan teknik pengujian dan
konsep keandalan atas produk
proses VLSI.
2
General Concepts
Probe arm
Test probe
Ke computer
Visualization of wafer testing
Infant
mortalities
Wear-out
Random failures
Bathtube realibility curve
t (hour)
3
General Concepts
N
av 
T
MTTF 
1
av
av = average failure rate
N = number of failure devices
T = number of operational hours
MTTF = mean time to failure  average life time
FIT = failure in time
1 FIT = 1 failure in 1 million parts over 1000 hours
f(t) = number of failures

MTTF   t  e
f(t)   e - t
0
t
-t
dt 
1

4
CMOS Testing
Testing problem
Testing is to tell whether
a system is good or bad.
Related fields:
Verivication: To verify the correctness
of a design
Diagnosis:
Realibility:
Controller
Test
Vector
DUT
inputs
Response
outputs
To tell the faulty site
To tell whether a good
system will work after
some time.
Correct
Response
Compare
Equal?
5
CMOS Testing
Testing problems:
•
Fault may occur anytime -
design
process
package
field
•
Fault may occur at any place
•
VLSI circuit are lage
•
I/O access is limited
6
CMOS Testing
Hasil yang baik
7
CMOS Testing
Fault models
+
ID
+
+
VGS
-
-
ID = 0
VDS
Shorted
+
VGS
-
-
VDS
Open
VDD
L
substrate
Gate
sa1
sa1
Gate sa1 fault
Gate-drain short
8
Test Generation Method
VDD
p
a
s1
B
a
b
b
Skematik NAND2
n
s0
Model logik
f
S0
s1
f
0
0
1
1
0
1
0
1
M
1
0
w0
B-logik
9
Test Generation Method
Gerbang AND:
sa1
b
f=b
sa0
b
f=0
sa1
b
f=b
sa1
b
sa0
b
f=1
sa0
b
f=0
f=b
Gerbang OR:
a
sa1
g=1
a
sa1
g=0
a
sa1
g=a
a
sa0
g=a
a
sa0
g=a
a
sa0
g=1
Pengaruh stuck-at fault pada gerbang logik
10
Test GenerationMethod
Ada keruskan, maka harus ditentukan teknik
utuk menemukan kerusakan tersebut
Contoh: Untuk identifikasi kerusakan di D, maka D harus diberi logik 1
oleh karena itu titik A dan B harus diberi nilai 1.
Untuk identifikasi menjalarnya pengaruh kerusakan ke output
maka titik E harus diberi nilai 1, jadi titik C harus 0.
Oleh karena itu test vector adalah A=1, B=1, C=0.
11
RESUME
• General Concepts.
• CMOS Testing.
• Test Generation Method.
12