Matakuliah
Tahun
Versi
: H0362/Very Large Scale Integrated Circuits
: 2005
: versi/01
Pertemuan 11
General VLSI System Components
1
Learning Outcomes
Pada Akhir pertemuan ini,
diharapkan mahasiswa akan dapat
menerapkan gerbang logik,
switching logik, dan atau struktur
deskripsi Verilog untuk membangun
rangkaian sederhana dengan level
hirarki lebih tinggi dalam CMOS
VLSI.
2
Multiplexor
Verilog HDL:
module simple_mux (mux_out, p0, p1, select) ;
input p0, p1 ;
Multiplexor 2:1
input select ;
output mux_out ;
m
n: number of input
n
=
2
always @ (select) ;
f : output
case (select)
m: number select
1’b0: mux_out = p0 ;
1’b1: mux_out = p1 ;
f = p0 . s + p1 . s
endcase
endmodule
s
Gate level multiplexor:
p0
p1
s
f
p0
f
p1
3
Multiplexor
Implementasi rangkaian multiplexor 2:1
dapat juga dilakukan dengan rangkain logic switch
sehingga Verilog HDL nya juga akan berubah.
Multiplexor 2:1
Cara lain
s
Gate level multiplexor:
s
p0
f
p0
f
p1
p1
s
4
Multiplexor
Verilog HDL:
Multiplexor 4:1
module bigger_mux (out_4, p0, p1, p2, p3, s0, s1) ;
input p0, p1, p2, p3 ;
input s0, s1 ;
output out_4 ;
assign out_4 = s1 ? (s0, p3 : p2) : (s0 ? p1 : p0) ;
endmodule
s0
Gate level multiplexor:
p0
0
p1
1
s0
p2
0
p3
1
s1
0
f
1
5
Multiplexor
Verilog HDL:
module gate_mux_4 (out_gate, p0, p1, p2, p3, s0, s1) ;
input p0, p1, p2, p3 ;
s1
s0
input s0, s1 ;
wire w1, w2, w3, w4 ;
output out_gate_4 ;
nand (w1, p_0, ~s1, ~s0),
(w2, p_1, ~s1, s0),
(w3, p_2, s1, ~s0),
(w4, p_3, s1, s0),
p0
(out_gate, w1, w2, w3, w4) ;
endmodule
Gate level multiplexor:
p0
p1
p2
p3
s0 s1
0
1
2
3
Multiplexor 4:1
Cara lain
p1
f
f
p2
p3
f = p0 . s1 . s2 + p1 . s1 . s0 + p2 . s1 . s0 + p3 . s1 . s0
6
Multiplexor
Verilog HDL:
module tg_mux_4 (f, p0, p1, p2, p3, s0, s1) ;
input p0, p1, p2, p3 ;
input s0, s1 ;
wire w0, w1, w2, w3, w_0, w_x ;
output f ;
nmos (po, w0, ~s1), (w0, w_0, ~s0) ;
nmos (p1, w1, ~s1), (w1, w_0, s0) ;
nmos (p2, w2, s1), (w2, w_0, s0),
s0
nmos (p3, w3, s1), (w3, wp_0, s0) ;
not (w_x, w_0), (f, w_x) ;
endmodule
Gate level multiplexor:
Multiplexor 4:1
Cara lain
s1
s2
s3
p0
p1
f
p2
p3
7
Binary Decoders
Verilog HDL:
module decode_4 (d0, d1, d2, d3, s0, s1) ;
input s0, s1 ;
2/4 decoder
ouput d0, d1, d2, d3 ;
do = s1 . s0 = s1 + s0
nor (d3, ~s0, ~s1), (d2, s0, s1),
(d1, s0, ~s1), (d0, s0, s1) ;
d1 = s1 . s0 = s1 + s0
endmodule
d2 = s1 . s0 = s1 + s0
Gate level multiplexor:
d3 = s1 . s0 = s1 + s0
d0 d1 d2 d3
s1
s0
2/4
s1
0 1
2
3
s1 s0
d0
d1 d3 d4
0
0
1
1
1
0
0
0
0
1
1
0
0
1
0
1
s0
0
0
0
0
0
0
0
1
d0
d1
d2
d3
8
Latch
Verilog HDL:
module d_latch (q, q_bar, d) ;
input d ;
ouput q, q_bar ;
reg q, q_bar ;
always @ (d) ;
begin
 (t_d) q = d ;
 (t_d) q_bar = ~d ;
end
endmodule
module d_latch_gates (q, q_bar, d) ;
input d ;
ouput q, q_bar ;
wire not_d ;
not (not_d, d) ;
nor  (t_nor) g1 (q_bar, q, d),
 (t_nor) g2 (q_bar, not_d) ;
endmodule
VDD
Gate level latch:
D
Q
Q
D
Q
Q
simbol
Q
Q
D
Diagram logik
Rangkaian CMOS
9
Latch
Verilog HDL:
module d_latch (q, q_bar, d, enable) ;
input d, enable ;
ouput q, q_bar ;
reg q, q_bar ;
always @ (d and enable) ;
begin
 (t_d) q = d ;
 (t_d) q_bar = ~d ;
end
endmodule
Gate level latch:
D
D
Q
En
Q
simbol
Q
En
Q
Diagram logik
10
D Flip Flop
Verilog HDL:
Master Slave D Flip-Flop
module positive_dff (q, q_bar, d, clk) ;
input d, clk ;
Positive Positive-edge
edge
ouput q, q_bar ;
reg q, q_bar ;
always @ (posedge clk) ;
1
Load
Transfer
begin
Master
t
to slave
0
q=d;
q_bar = ~d ;
0
T
end
endmodule


Gate level:
D
Q
M3
M1
Master

M2

Slave
M4

Q
11
RESUME
•
•
•
•
Multiplexor.
Binary Decoders.
Latch.
D Flip Flop
12