Matakuliah
Tahun
Versi
: H0362/Very Large Scale Integrated Circuits
: 2005
: versi/01
Pertemuan 3
Karakteristik Logik Gerbang
MOSFET
1
Learning Outcomes
Pada Akhir pertemuan ini,
diharapkan mahasiswa akan dapat
menjelaskan karakteristik logik
gerbang MOSFET.
2
Ideal Switch
a=0
a=1
y
x
y
x
tutup
buka
Hubungan seri:
Assert-high
a
b
a.1
1
(a . 1) . b
g=a.b
a
Hubungan paralel:
a.1
b
1
+
b.1
f=a+b
3
Ideal Switch
a=1
a=0
y
x
tutup
buka
Hubungan seri:
Assert-low
y
x
a
b
a.1
1
(a . 1) . b
g=a.b
a
a
Gerbang NOT:
1
0
a.1
a
+
a.0
1
0
f(x) = a . 1 + a . 0
Mux
f=a.1+a.0=a
4
MOSFET Switch
Gate
Simbol
Drain
Source
Gate
Source
Drain
pFET
nFET
VDD > 0 V
VDD
VSS
VDD
+
-
Ke chip
+
Power supply
VDD
Logik 1
+
-
Rangkaian
CMOS
VSS < 0 V
Dual power supply voltages
Tak tentu
0
Single voltage power supply
Logik 0
5
MOSFET Switch
nFET
a=0
x
a=1
y=?
x
tutup
buka
pFET
a=1
x
a=0
y=?
buka
y=x
x
tutup
y=x
6
MOSFET Switch
Ke VDD
nFET
VDD
VA
Threshold voltage
Drain
Gate
VA
+
VGSn
A = 1 Mn ON
Mn
Source
-
VDD
pFET
VSGp +
VA
-
Gate
VTn
A = 0 Mn OFF
VDD
Source
(VDD - |VTn|)
VA
A = 1 Mp OFF
Mp
Drain
Ke ground
A = 0 Mp ON
7
MOSFET Switch
Pass Characteristics
nFET
VDD
VDD
+ VTn
in
Vx = 0 V
+
+
-
-
out
Vy = 0 V
in
Vx = VDD
-
+
+
-
-
pFET
Vy = VDD - VTn
in
Vx = VDD
+
+
-
-
out
Vy = VDD
in
Vx = 0 V
out
|VTp|
+
+
+
-
-
out
Vy = |VTp|
8
Gerbang Logik CMOS
VDD
f (a, b, c)
SWn
0
Control block
inputs
b
c
VSS
tutup
f=1
buka
0
VDD
1
VDD
1
a
output
a
b
c
Control block
b
c
SWp
inputs
a
Control block
inputs
1
buka
f=0
tutup
0
VSS
VSS
9
Gerbang Logik CMOS
Pasangan complement CMOS
Ke VDD
Gerbang NOT
Mp pFET
x
x
x
Mn nFET
x
x
0
1
1
0
Ke VSS
X=0
Mp ON
VDD
Ke VDD
Ke VDD
X=1
Mp
Mp OFF
x
Mn OFF
Mn ON
Ke VSS
Ke VSS
x
Mn
10
Gerbang Logik CMOS
A
B
1
0
0
0
Gerbang NOR
0
1
0
1
2
3
Mux
VDD
A
F=A+B
B
Mpx
Mpy
A
0
0
1
1
B
0
1
0
1
F
1
0
0
0
1.A.B
0.B
Mny
F
F=A+B
0.A
Mnx
A
B
11
Gerbang Logik CMOS
A
B
1
1
1
0
0
1
0
1
2
3
Gerbang NAND
Mux
F=A.B
A
B
F
A
0
0
1
1
B
0
1
0
1
F
1
1
1
0
VDD
1.A
Mpx
Mpy 1 . B
F=A.B
Mnx
0.A.B
Mny
A
B
12
Gerbang Logik CMOS
N
Fan-out N
M
Fan-in M
13
Gerbang Logik CMOS
B
C
F
B
C
F
A
Gerbang Complex
A
VDD
F = A . (B + C)
1.B.C
= A + (B + C)
= [A + (B . C)] . 1
1.A
F = A . 1 + (B . C) . 1
= A . 1 + (B . C) . 1
F = 0 jika A = 1 AND (B+C ) = 1
A
B
C
B
A
0 . (B + C)
0 . [A . (B + C)]
VDD
C
0 . [A . (B + C)]
F
A
B
B
C
A
C
14
Clock dan Aliran Data

1
time
1

f
time
0
T
T
 t hold
2
2T
System clock



Blok
1
Blok
2
1

T

Blok
3
Block level system timing diagram
15
RESUME
•
•
•
•
Ideal Switch: assert high, assert low.
MOSFET Switch: nFET, pFET.
Gerbang logic CMOS.
Clock dan aliran data.
16