Matakuliah
Tahun
Versi
: H0344/Organisasi dan Arsitektur Komputer
: 2005
: 1/1
Pertemuan 24
Reduced Instruction Set Computer 2
1
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Menjelaskan prinsip kerja Reduced
Instruction Set Computer
2
Outline Materi
•
•
•
•
•
•
Instruction Execution Characteristics
The Use of Large Register File
Compiler-Based Register Optimization
Reduced Instruction Set Architecture
RISC Pipelining
RISC versus CISC Controversy
3
Reduced instruction set architecture
Why CISC
A desire to simplify
compilers
A large number of
instruction
A desired to improved
performance
More complex instruction
4
Reduced instruction set architecture
Code relative to RISC I
[PATT82a]
[KATE83]
[HEAT84]
11 C Programs
12 C Programs
5 C Programs
RISC I
1.0
1.0
1.0
VAX-11/780
0.8
0.67
M68000
0.9
0.9
Z8002
1.2
1.12
PDP-11/70
0.9
0.71
5
Reduced instruction set architecture
Characteristics of Reduced Instruction Set Architectures
1. One instruction per cycle
2. Register to register operation
3. Simple addressing modes
4. Simple instruction formats
6
Reduced instruction set architecture
Two comparisons of register to register and
memory to memory approaches
8
Add
16
B
16
C
16
A
Memory to memory
I = 56, D = 96, M = 152
Load
Load
Add
Store
rB
rC
rA
rA
B
B
rB rC
A
(a) A  B + C
Register to memory
(b) A  B + C, B  A + C, D  D - B
8
Add
Add
Add
16
B
A
B
16
C
C
D
Memory to memory
I = 168, D = 288, M = 456
16
A
B
D
Add
Add
Sub
rA
rB
rD
rB
rA
rD
rC
rC
rB
Register to memory
I = 104, D = 96, M = 200
(b) A  B + C, B  A + C, D  D - B
I = Size of executed instructions
D = Size of executed data
M = I + D = Total memory traffic
7
Reduced instruction set architecture
Design and layout effort for some microprocessor
Transistor
Design
Layout
(thousands)
(person months)
(person months)
RISC I
44
15
12
RISC II
41
18
12
M68000
68
100
70
Z8000
18
60
70
110
170
90
Intel iA Px-432
8
RISC pipelined
Load A  M
I
E
Load A  M
D
Load B  M
I
E
I
Load B  M
D
Add C  A + B
I
E
D
I
E
Add C  A + B
E
Store M  C
I
E
Branch X
D
I
E
Store M  C
D
I
E
I
E
Branch X
D
I
E
Noop
(a) Sequential execution
Load A  M
Load B  M
Noop
Add C  A + B
Store M  C
Branch X
I
Load A  M
D
I
E
D
Load B  M
I
E
Noop
Add C  A + B
E
I
E
D
Store M  C
I
E
Branch X
Noop
I
E
I
E1
E2
D
I
E1
E2
D
I
E1
E2
I
E1
E2
I
E1
E2
D
I
E1
E2
I
E1
E2
I
E1
Noop
Noop
(c) Three way pipelined timing
E
(b) Two way pipelined timing
E
I
I
E2
(c) Four way pipelined timing
9
Reduced instruction set architecture
Optimization of pipelined
Normal and delay branch
Address
Normal branch
Delay branch
Optimized delay branch
100
Load X, A
Load X, A
Load X, A
101
Add 1, A
Add 1, A
Jump 105
102
Jump 105
Jump 106
Add 1, A
103
Add A, B
Noop
Add A, B
104
Sub C, B
Add A, B
Sub C, B
105
Store A, Z
Sub C, B
Store A, Z
106
Store A, Z
10
Reduced instruction set architecture
Optimization
of pipelined
100 Load X, A
I
101 Add 1, A
E
D
I
E
102 Jump 105
I
103 Add A, B
E
I
105 Store A, Z
I
E
D
I
E
D
E
D
(a) Traditional pipeline
100 Load X, A
I
101 Add 1, A
E
D
I
E
102 Jump 106
I
103 Noop
E
I
106 Store A, Z
E
(b) RISC pipeline with inserted Noop
100 Load X, A
101 Jump 105
102 Noop
106 Store A, Z
I
E
D
I
E
I
E
I
(c) Reversed instructions
11