Reading summary
•
•
•
•
Chapter 1: all
Chapter 2: 2.1 to 2.8, 2.12
Chapter 3: 3.1 to 3.6
Chapter 7: all
CSE241 1
A Microprogrammed CPU
•
•
•
•
A Microprogram Sequencer (controller)
Architectures & Timing
Pipelining
Conditional Branches
CSE241 2
Current Situation
MUX
Address Register
Condition Codes
Microprogram memory
Data Path
Microinstructions
To Data Path
CSE241 3
Generic Microprogram Controlled CPU
Microprogram
Sequencer
MUX
Condition Codes
Microprogram memory
Data Path
CC Select
Next Microinstruction Select
Branch Address
Microinstructions
To Data Path
CSE241 4
Simplified Generic Microprogram Sequencer
Branch Address (Input)
clock
‘0’ (Zero)
(internal)
Microprogram Counter
multiplexer
Incrementer
Next
Microinstruction
Select Logic
Condition
Code (Input)
Next
Microinstruction
Select (Input)
Address Out
CSE241 5
Sequencer Functions
• SEQ
– Next microinstruction address is microPC (mPC)
• BZ
– Next microinstruction address is 0
• BU k
– Next microinstruction address is from branch address
field
• BC k
– Branch to k if CC is true, else next microinstruction
address is from mPC
CSE241 6
Behaviour of mPC
• Notice that
– The mPC always latches the output of the incrementer at
the start of every new clock cycle
– The output of the incrementer (combinational logic) is
always the value of the output of the device (the
minstruction address) + 1
– So the mPC at the start of the next clock cycle will
always contain the address of the minstruction located
in the next sequential memory location located
following the address of the minstruction being output
by the device
• So, if the device is emitting k, the mPC in the next clock cycle
will have the value k+1, no matter how k was chosen (Branch
address, SEQ etc).
CSE241 7
SEQ
Branch Address (Input)
clock
K
‘0’ (Zero)
(internal)
Microprogram Counter
K+1
multiplexer
Incrementer
K
Next
Microinstruction
Select Logic
Condition
Code (Input)
Next
Microinstruction
Select (Input)
K
K
Address Out
CSE241 8
SEQ
(makes certain assumptions which may not hold in practice)
mPC
MUX output
Device Output
Incrementer
Output
K+1
k (is stable, because mPC is a register)
Select mPC (== k); stable because output is from mPC
k (is stable, because mPC is a register)
Device output + 1 == k+1
K+1 latched by
mPC
CSE241 9
BZ (Branch to Zero)
Branch Address (Input)
clock
K
‘0’ (Zero)
(internal)
Microprogram Counter
0+1=1
multiplexer
Incrementer
0
Next
Microinstruction
Select Logic
Next
Microinstruction
Select (Input)
0
0
Address Out
CSE241 10
BZ (timing)
(makes certain assumptions which may not hold in practice)
mPC
MUX output
Device Output
Incrementer
Output
1
k (is stable, because mPC is a register)
0 -- MUX output is the Zero input
0
Device output + 1 == 0+1 = 1
1 latched by
mPC
CSE241 11
BU d (Branch Unconditionally to d)
Branch Address (Input)
clock
k
‘0’ (Zero)
(internal)
Microprogram Counter
d+1
multiplexer
Incrementer
d
Next
Microinstruction
Select Logic
Next
Microinstruction
Select (Input)
d
d
Address Out
CSE241 12
BU d (timing)
(makes certain assumptions which may not hold in practice)
mPC
MUX output
Device Output
Incrementer
Output
d+1
k (is stable, because mPC is a register)
d (the value on the BA field)
d
Device output + 1 == d+1
X+1 latched by
mPC
CSE241 13
BC d (Branch Conditionally to d)
Branch Address (Input)
d
clock
k
‘0’ (Zero)
(internal)
Microprogram Counter
d + 1 or k + 1
multiplexer
Incrementer
k or d
Next
Microinstruction
Select Logic
Next
Microinstruction
Select (Input)
k or d
Address Out
x or k
CSE241 14
BC d (timing)
(makes certain assumptions which may not hold in practice)
mPC
MUX output
Device Output
Incrementer
Output
X+1 or K+1
k (is stable, because mPC is a register)
Depends on value of CC; may be X (CC true) or K (CC False)
k or d
Device output + 1 == d+1 or k+1
X+1 or
K+1
latched by
mPC
CSE241 15
Architecture 1
The green box contains the “generic microprogram
sequencer.
The microinstruction contains the following
(Control Path) fields:1. Next Microinstruction Select (seq, BZ, BU K, BC K)
2. Branch Address
3. CCMUX Select
CSE241 16
Timing in Architecture 1
Start with the output of the
sequencer
2: Microinstruction Fetch
3: Simultaneous execution
of microinstrutions in Data Path
and Control Path
CSE241 17
Condition Code available to
Microprogram Sequencer
Condition
Codes
Generated
Timing of SEQ, Architecture 1
(makes certain assumptions which may not hold in practice)
mPC
Sequencer
output
incrementer
Memory
Data Path
k
k+1
k
k+1 latched by mPC
k+1
fetch minst[k]
minst[k]
executing minst[k]
CC’s
CCMUX
select
Choose CCx
SEQ
next minst
select
CSE241 18
execution finished;
CC’s valid
Is there a problem with this architecture?
• Problems (instability) occur if there is (e.g.) a
purely combinational path (no registers) through
the system
• Consider the system executing the
microinstruction
– BU k, R5-out, F=A+B, Z-in
• Suppose this instruction is located at memory
address k, and that the mPC currently contains the
value k-1 (so that the next clock cycle begins with
mPC = k
CSE241 19
The architecture (reminder)
Note:
the path(s) from
--Branch Address in
--next minst. select in
--through MUX
--through memory
--back up to sequencer
are purely combinational. No registers
are involved.
CSE241 20
BU d (timing)
mPC
Sequencer
output
incrementer
k
k+1
?
d
k
k+1
d+1
fetch minst[k]
fetch minst[d]
Memory
minst[d]
Data Path
CC’s
CCMUX
select
BU d
next minst
select
CSE241 21
?
The problem
• The problem is this:– when the minst at k is fetched, it contains the operation “BU d”
(branch unconditional to d)
– so the output of the sequencer MUX changes from the mPC (==k)
to the value on the BA field (==d)
– so the minst at k will stop executing because
– the memory fetches the minst at d; but what is the next
microinstruction select field in this minst? What if it contains BU
x?
• Generally, we need to stabilize something
• We cannot permit this uncontrolled multifetching
CSE241 22
Solution 1: Address Register
• Suppose we put an address register at the output of
the microprogram sequencer. Then,
– at the start of every clock cycle, the address register
will latch the output of the microprogram sequencer
– so the address given to memory will not change during
a microcycle
– so the microinstruction cannot change during a
microcycle
– so the system will be stable
CSE241 23
Address Based Architecture
CC Mux
Sequencer
Address Register
Microprogram memory
CSE241 24
Data Path
SEQ Timing on Address based architecture
Next microinstruction address
is generated by sequencer and
made ready at input of address CC Mux
register
Sequencer
Address Register
Start with address register
(==k)
Microprogram memory
Fetch minst[k]
minst[k] is applied to both the Control Path and Data Path
CSE241 25
Data Path
SEQ Timing
Address Reg
k
k+1
Memory
fetch minst[k]
Data Path
minst[k]
executing minst[k]
CC’s
SEQ
next minst
select
mPC
Incrementer
Output of
Sequencer
execution finished;
CC’s valid
k+1
k+2
k+2
k+1
CSE241 26
k+1 latched by
Address Register
BU X timing
Address Reg
k -- note that this is stable!!!
Memory
fetch minst[k]
d
minst[k]
Data Path
executing minst[k]
CC’s
BU d
next minst
select
mPC
Incrementer
Output of
Sequencer
execution finished;
CC’s valid
k+1
d+1
k+2
d
CSE241 27
d+1 latched by mPC
Address-Based Architecture
• Convince yourself that this is a stable architecture
• Note that the order of timing is
– fetch the microinstruction at address M[address register]
– execute this microinstruction
• So the total microcycle time T is
– T = tf + te where tf = fetch time and te = execute time
CSE241 28
Pipelined Architecture
• Important alteration in the architecture
• There are ramifications we will not bother with
(e.g., behaviour of conditional branches)
• Very important architectural construct
– pipelining is everywhere!
CSE241 29
Pipelined Architecture
CC Mux
Sequencer
Microprogram memory
Data Path
Pipeline Register
CSE241 30
Timing in the Pipelined Architecture
The sequencer chooses the next microinst address;
the Data Path executes
CC Mux
Sequencer
The memory fetches the
next microinst (the Data Path is still computing)
Microprogram memory
Data Path
Pipeline Register
Execution starts by applying the microinst. in the pipeline register to
the Control Path and the Data Path simultaneously
CSE241 31
SEQ Timing in the Pipelined Architecture
Pipeline Reg
microinstruction[t] (t is time; we don’t know where this came from
next minst
select
SEQ
mPC
k
k+1
Incrementer
Output of
Sequencer
Memory
Data Path
k+1 latched by mPC
k+1
k
Fetch minst[k]
minst[k] fetched, and can be latched
by pipeline register
minst[k] latched by
pipeline register
executing minst[t]
execution finished;
CSE241 32
Pipelining
• has
– overlapped the microinstruction fetch and execute
– thus the total microcycle time has become
• T = Max(tf , te)
– compare this to
• T = t f + te
CSE241 33