Matakuliah
Tahun
Versi
: H0344/Organisasi dan Arsitektur Komputer
: 2005
: 1/1
Pertemuan 18
Control Unit 1
1
Learning Outcomes
Pada akhir pertemuan ini, diharapkan mahasiswa
akan mampu :
• Menjelaskan prinsip kerja control unit
dalam mengeksekusi beberapa instruction
2
Outline Materi
• Micro-Operations
• Control of Processor
• Hardwired Implementation
3
Micro-operation
Constituent elements of a program execution
Instruction
cycle
Instruction
cycle
Fetch
OP
OP
Indirect
OP
OP
Instruction
cycle
Execute
Interrupt
OP
4
Micro-operation
The fetch cycle
t1 :
MAR  PC
t2 :
MBR  Memory
PC  PC + 1
t3 :
MAR
MBR
PC
IR
AC
IR  MBR
0000.0000.0110.0100
MAR
MBR
PC
IR
AC
(a) Beginning
MAR
MBR
PC
IR
AC
0000.0000.0110.0100
0000.0000.0110.0100
(b) First step
0000.0000.0110.0100
0001.0000.0010.0000
0000.0000.0110.0100
(c) Second step
MAR
MBR
PC
IR
AC
0000.0000.0110.0100
0001.0000.0010.0000
0000.0000.0110.0100
0001.0000.0010.0000
(d) Third step
5
Micro-operation
The indirect cycle
t1 :
MAR  IR(address)
t2 :
MBR  Memory
t3 :
IR(address)  MBR(address)
The interrupt cycle
t1 :
MBR  PC
t2 :
MAR  Save_address
PC  Routine_address
t3 :
Memory  MBR
6
Micro-operation
The execute cycle
Add R1, X
Isz X
t1 :
MAR  IR(address)
t2 :
MBR  Memory
t3 :
R1  R1 + MBR
t1 :
MAR  IR(address)
t2 :
MBR  Memory
t3 :
MBR  MBR + 1
t4 :
Memory  MBR
If (MBR = 0) then (PC  PC + 1)
t1 :
MAR  IR(address)
MBR  PC
Bsa X
t2 :
PC  IR(address)
Memory  MBR
t3 :
PC  PC + 1
7
Micro-operation
Flowchart for instruction cycle
11 : Interrupt
Setup
interrupt
ICC?
10 : Execute
01 : Indirect
Opcode?
Read
address
Fetch
instruction
ICC = 10
Indirect
address?
ICC = 00
Yes
ICC =
00 : Fetch
01 : Indirect
10 : Execute
11 : Interrupt
00 : Fetch
Interrupt
for enabled
interrupt?
No
No
ICC = 10
ICC = 11
Yes
ICC = 01
ICC = 00
8
Control of The processor
Model of the control unit
Instruction
register
Control signals
within CPU
Control signals
from system bus
Flag
Control unit
Clock
Control signals
to system bus
Control
bus
9
Control of The processor
Data paths and control signals
C5
M
B
R
C11
C1
C3 C4
C10
C12
PC
C8
IR
C0
M
A
R
Clock
AC
C6
C2
C7
C9
Flags
C13
ALU
Control
unit
Control
signals
10
Control of The processor
Micro-operations and control signals
Micro-operation
Timing
Fetch
t1 : MAR  PC
t2 : MBR  Memory
PC  PC + 1
t3 : IR  MBR
Active Control Signals
C2
C5, CR
C4
Indirect
t1 : MAR  IR(address)
t2 : MBR  Memory
t3 : IR(address)  MBR (address)
C8
C5
C4
Interrupt
t1 : MAR  PC
t2 : MBR  Save address
PC  Routine address
t3 : Memory  MBR
C2
C12, CW
11
Control unit
Control of the
processor
IR
PC
Internal Processor Organization
Address lines
MAR
Data lines
MBR
AC
Y
ALU
Y
12
Hardwired implementation
Instruction register
Decoder
I0
I1
I2
Ik
T1
T2
Clock
Timing
generator
T3
Control unit
Flags
Tn
C0 C1 C2
Cm
13