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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 4, NOVEMBER 1998
Simulating the Impact of Pattern-Dependent
Poly-CD Variation on Circuit Performance
Brian E. Stine, Duane S. Boning, Member, IEEE, James E. Chung, Member, IEEE,
Dennis J. Ciplickas, and John K. Kibarian
Abstract—In this paper, we present a methodology for simulating the impact of within-die (die-level) polysilicon critical dimension (poly-CD) variation on circuit performance. The methodology is illustrated on a 0.25 m 64 2 8 SRAM macrocell layout.
For this example, the impact as measured through signal skew
is found to be significant and strongly dependent on the input
address of the SRAM cell.
Fig. 1. Flow used to simulate the impact of poly-CD variation on circuit
performance in this paper.
I. INTRODUCTION
I
N THE literature, significant research has been focused on
understanding the impact of process variation on circuit performance [1]–[12], but the majority of this research assumes
process variation to be completely random and drawn from either independent or correlated normal distributions (i.e., Monte
Carlo type simulations or design centering methodologies).
This approach is adequate when assessing the impact of lot-tolot or wafer-to-wafer process variation on circuit performance
since these types of variation can often be adequately modeled
using Gaussian white noise. For pattern-dependent variation,
however, this approach is not acceptable because it essentially
assumes that the channel length of each transistor on a die can
be described by the same underlying random distribution or
perhaps with some crude degree of proximity effects included
via a correlation structure.
Previous studies have empirically observed a correlation
between poly-CD variation and circuit performance [13] for
small circuits (such as ring-oscillators), but predictive modeling of the impact of die-level variation has been difficult.
In this paper, we present and illustrate a methodology for determining the impact of pattern-dependent polysilicon critical
dimension (poly-CD) variation on circuit performance. After
describing the methodology in Section II, the methodology is
illustrated in Section III via a case study of a 64 8 SRAM
Manuscript received December 28, 1997; revised February 24, 1998. This
work was supported in part under ARPA Contracts DABT-63-95-C-0088 and
DAAH01-96-C-R904, AASERT Grant DAAHA04-95-I-0459, and an Intel
Foundation Fellowship.
B. E. Stine was with Microsystems Technology Laboratories, Department
of Electrical Engineering and Computer Science, Massachusetts Institute of
Technology, Cambridge, MA 02139 USA. He is now with PDF Solutions,
Inc., San Jose, CA 95110 USA.
D. S. Boning and J. E. Chung are with the Microsystems Technology
Laboratories, Department of Electrical Engineering and Computer Science,
Massachusetts Institute of Technology, Cambridge, MA 02139 USA (e-mail:
boning @mtl.mit.edu).
D. J. Ciplickas and J. K. Kibarian are with PDF Solutions, Inc., San Jose,
CA 95110 USA.
Publisher Item Identifier S 0894-6507(98)08363-8.
Fig. 2. Hopkins model used in aerial imaging simulators. Figure and notation
derived from [16].
macrocell. Finally, some concluding remarks are offered in
Section IV.
Poly-CD variation is especially important because it translates directly into MOS transistor channel length variation
and resulting variations in the drive current and switching
characteristics. Current lithography and etch technology can
typically achieve wafer-scale line width uniformity of approximately 5–10% (measurements of the same structure within
each chip across the wafer). Design rules typically assume
that the variation within any one chip will be smaller than
this value. However, measurements of supposedly identical
structures within the same die reveal variations on the order
of 15–20% or more [14], [15]. Clearly, additional physical
effects are coming into play at this scale and within-die polyCD nonuniformity contributes significant variance to the total
poly-CD variation budget.
0894–6507/98$10.00  1998 IEEE
STINE et al.: PATTERN-DEPENDENT POLY-CD VARIATION
553
Fig. 5. Estimated poly-CD variation across all coordinates in the cell. Aerial
imaging simulation was used to estimate the poly-CD variation.
(a)
Fig. 3. ”Ideal” as-drawn features from an SRAM cell and corresponding
aerial imaged features.
(b)
Fig. 6. (a) Drain current versus drain voltage for Vgs at the supply rail. (b)
Saturation or drive current versus channel langth for the NMOS and PMOS
devices.
Fig. 4. A 64
2 8 SRAM macrocell. Layout is approximately 180 2 140 m.
The problem of determining the impact of variation on
circuit performance is especially vexing because of the intense
coupling between design and manufacturing. A portion of
the variance that a design sees is driven by the process
(mainly lot-to-lot, wafer-to-wafer, and within-wafer), but a
large part of the variance, especially for critical parameters
such as the polysilicon critical dimension, is dependent on the
design itself as represented by the layout. In this way, the
question “what is the impact of spatial or pattern-dependent
variation on circuit performance?” cannot be answered in the
general, but must be dealt with in the specific as the answer
is necessarily different for each design. As such, this paper
offers a methodology for determining the impact of patterndependent poly-CD variation on circuit performance which can
be used on each layout of interest or on several layouts to gain
insight rather than presents a conclusive study or evaluation of
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 4, NOVEMBER 1998
Fig. 7. Simulation of the write-access behavior for the 64
data lines for this particular address.
2 8 SRAM macrocell with poly-CD variation enabled. Significant skew is seen across all
the impact of pattern-dependent poly-CD variation on circuit
performance.
II. SIMULATION METHODOLOGY
We propose the methodology shown in Fig. 1 for exploring
the impact of pattern-dependent poly-CD variation on circuit
performance. We use aerial imaging to perturb or transform
all of the polygons in the original or as-drawn layout into
the aerial imaged or “as-manufactured” layout resulting in
a new poly layer. In this way, the aerial image simulator
is modeling the manufacturing process. After simulating the
manufacturing process, a circuit net-list is extracted from the
as-manufactured layout (with the imaged poly layer used as the
gate mask) using a traditional layout-parasitic engine. Finally,
a circuit simulator is used to evaluate the performance of
the layout. By looking at the performance of the layout with
and without aerial imaging over different input conditions,
a determination can be made as to the impact of poly-CD
variation on circuit performance. Many other effects such
as lens-aberration, stepper leveling/focusing errors, and etch
loading contribute to poly-CD variation. Since these effects
are more macroscopic, the relative utility of the methodology
presented here is limited to small to medium size layouts;
however, this restriction can be removed if accurate and
calibrated models exist for these effects as a function of
extractable or tangible layout parameters.
Optical proximity components are estimated using aerial
imaging [16], [17]. Aerial imaging has been in practice for
approximately ten years and most simulators use the Hopkins
model approach [17]. In this approach (see Fig. 2), the incan be expressed as a nonlinear
tensity at the target
, the
function of the illumination lens and pupil,
projection optics
, and the mask being imaged
.
The numeric aperture of the lens (NA), the illumination
wavelength ( ), and the coherence of the imaging system
( ) are the key input parameters which shape the Hopkins
integral. Using these parameters and several assumptions of
the image/projection system [16] allow the Hopkins integral
to be expressed as a two-dimensional convolution integral
which allows the expression to be evaluated using numerically
efficient fast Fourier transforms. By taking equi-illumination
contours at the target, an estimate of the optical proximity
component of lithography variance is enabled. A sample result
is shown in Fig. 3. The “ideal” features are shown as well as
the results from aerially imaging for a sample SRAM cell.
III. SIMULATION EXAMPLE
In this section, the methodology described in Section II is
8 SRAM macrocell. In current
applied to a 0.25- m 64
technologies, SRAM finds application not only as a standalone part, but also as an embedded memory element in microprocessors and complex logic and as a process qualification
and development vehicle [18]. Also, SRAM layout typically
includes a mix of periodic structures (the cell array) and aperiodic logic components (e.g., the decoders and input-output
buffers). For these reasons, SRAM makes a suitable case study
for exploring the impact of variation on circuit performance.
The SRAM macrocell layout (see Fig. 4) is approximately
140 m in size and contains approximately 4000
180 m
transistors. The layout was originally designed for 3- m design
rules but was scaled down to 0.25- m design rules using
simple scaling.
Only aerial imaging was used to simulate the within-die
poly-CD variation. This is mainly due to the small size of
STINE et al.: PATTERN-DEPENDENT POLY-CD VARIATION
Fig. 8. Delay versus input address for the 64
555
2 8 SRAM cell. Maximum skew across all output lines depends on the address chosen.
the layout compared to the length scales of other sources of
variation (e.g., stepper leveling errors, lens aberration). Fig. 5
shows a surface plot of poly-CD, the deviation of gate length
from nominal, versus location. This figure was generated by
extracting the channel length and position of each transistor
from the netlist and interpolating on to a surface plot. The
mean channel length is approximately 0.25 m and the largest
excursions are almost 10%. In this way, we are assuming
that the stepper has been perfectly targeted (i.e., the mean
channel lengths equals the specified target). Note the presence
of periodic components in addition to larger peaks and valleys.
Interconnect variation modeling was not done due to the small
size of the layout and was only crudely modeled using an
identical load capacitor of 10 fF at each output bit to simulate
external wiring.
For circuit simulation, a 0.25 m SPICE device model was
created based on SIA roadmap specifications [19], [20] and
typical values reported in the literature. The sensitivity of
, the measured drain current when both the gate and
drain are held at the supply rail, is shown in Fig. 6. Although
the
values are slightly higher than normally expected,
the sensitivity to channel length variation is similar to results
published elsewhere (e.g., [21]).
Fig. 7 shows the result of simulating the aerially imaged
layout with the above device models. The voltage at
each output line [Fig. 7(c)] is shown for the address lines
(ADDR[0]–ADDR[5]) set to all zeros [Fig. 7(a)] and for
strobing the input data lines (In[0]–In[7]) from all ones to all
zeros [Fig. 7(b)]. Also, the write strobe is held high resulting
in a display of the write access behavior. In this case study,
we are interested in the time required to write a data word to
an address location (the write access time). In particular, the
maximum skew for all the data lines is of key interest since
this is a measure of the susceptibility of this circuit to poly-CD
variation. Since interconnect has not been included and each
input bit passes through the same number of gates, the amount
of skew for the “as-drawn” layout is near zero, but as Fig. 7
shows, there is significant skew for the write access time. The
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 11, NO. 4, NOVEMBER 1998
read access time does not show significant skew behavior and
is significantly shorter than any write access time; thus, it is
not discussed. For the case of fully bidirectional applications
(i.e., in cases where the proportion of writing data to reading
data is relatively similar) such as in microprocessors, the
slowest of the read access times or write-access times dictates
the overall performance of the part.
The skew behavior shown in Fig. 7(c) is for one particular
address location. As Fig. 8 shows, the maximum amount of
write-access time skew is heavily dependent on the input
address vector. The oscillating behavior is especially apparent
8 layout is organized
on address line Out[5]. The 64
8 with each block having separate
into two blocks of 32
decoder circuitry and hence different layout environments.
The oscillating behavior in Out[5] is most likely caused by
8 block’s
differences in the channel lengths in each 32
decoding circuitry. In this way, the results of simulating
the impact of spatial variation on circuit performance are
heavily dependent on the input test vectors used during circuit
simulation. If all possible input vectors cannot be simulated,
then careful planning and examination of test vectors is
needed. Normally, test vectors are selected to stimulate all or
most of the functional blocks in the layout. Since functional
blocks are often repeated as many instances in a layout,
stimulating just one instance of each functional block is
not sufficient since instances are likely to have different
layout environments and hence difference degrees of poly-CD
variation. For this reason, the choice of test vectors should
always include the stimulation of all instances of a particular
functional block. If the number of instances of a functional
block is very large as well, then the number of instances
stimulated should be subseted to include only those which
are furthest apart in the layout.
IV. CONCLUSION
In this paper, we have demonstrated a methodology for
determining the impact of pattern-dependent poly-CD variation on circuit performance. For a particular SRAM example,
the results indicate that pattern-dependent poly-CD variation
results in an approximately 10% skew in the write access
time. The simulated skew, however, is strongly dependent on
the input conditions and assumptions. Further work is needed
to include interconnect variation and more extensive printing
(i.e., lithography and etch) models. Further studies are also
underway using this methodology to examine the sensitivity
of functionally identical logic blocks to different design styles
(such as dynamic versus static logic).
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Brian E. Stine, for a photograph and biography, see p. 139 of the February
1998 issue of this TRANSACTIONS.
Duane S. Boning (M’91), for a photograph and biography, see p. 139 of the
February 1998 issue of this TRANSACTIONS.
James E. Chung (S’87–M’90), for a photograph and biography, see p. 140
of the February 1998 issue of this TRANSACTIONS.
Dennis J. Ciplickas, photograph and biography not available at the time of
publication.
John K. Kibarian, photograph and biography not available at the time of
publication.