SIMULATION OF SINGLE ELECTRON TRANSISTOR (SET)
CIRCUITS USING MONTE CARLO METHOD
SYABANI BIN AHMAD
A project report submitted in partial fulfillment of the
requirements for the award of the degree of
Masters of Engineering (Electrical – Electronics & Telecommunication)
Faculty of Electrical Engineering
Universiti Teknologi Malaysia
JUNE 2007
iii
ACKNOWLEDGEMENTS
I would like to express my gratitude and appreciation to my supervisor,
Assosiate Prof. Dr Razali bin Ismail, for his guidance in the execution of the project,
for keeping me on my toes, and for his kind understanding. I am especially grateful
for all the help he provided and resources he made available without which the
project would not have reached its current stage. I would also like to thank Dr
Zaharuddin bin Mohamed, for being most efficient in coordinating the project. My
acknowledgement also goes out to the project presentation assessors, PM. Dr. Abu
Khari bin A’ain and Dr. Abdul Manaf bin Hashim who have given me much advice
and guidance during the project presentation. Last but not least, I would like to thank
my family for just being there, giving me the strength and much needed moral
support.
iv
ABSTRACT
The very fast switching characteristics and very low power consumption have given
the single electron transistor (SET) promising capabilities to replace CMOS
transistors in some semiconductor applications. SET theory of operation is now well
established nevertheless the transistor is still under laboratory investigations in the
fields of fabrication and applications in Large Scale Integration (LSI). Simulation of
SET consumes a great deal of computer time, which arises a need to renovate fast
and accurate simulation algorithms. This paper presents a simple model for SET
circuits, based on the orthodox theory, which calculates carrier transfer rates from
source to drain of the transistor by utilizing statistical mechanics. The simulator that
is used for this project is MOSES version 1.2 (Monte Carlo Single Electron
Transistor Simulator) which has been developed by Ruby Chen in Year 1997. The
reason for choosing this program is because it is free and sufficient to simulate SET
circuits such as Array, Junction and SET.
v
ABSTRAK
Ciri pensuisan pantas dan penggunaan kuasa yang rendah menjadikan SET sebagai
pesaing utama bagi CMOS di dalam industri semikonduktor. Walaupun teknologi
ini masih di peringkat kajian makmal bagi menyelesaikan isu fabrikasi dan Integrasi
Skala Besar (LSI), namun teori tentang bagaimana SET beroperasi telah diterima
ramai. Simulasi SET melibatkan masa pemprosesan komputer yang lama, oleh itu
algoritma yang efficient harus diguna pakai. Kertas projek ini membentangkan
model litar SET yang ringkas berdasarkan teori ortodoks yang mengira kadar
pemindahan pembawa dari sumber ke pemungut menggunakan statistik mekanik.
Simulator yang digunakan adalah Monte Carlo Single Electron Transistor (MOSES
versi 1.2) yang telah dibangunkan oleh Ruby Chen pada tahun 1997. Ianya telah
dipilih berdasarkan lesennya yang percuma dan berkesan didalam proses simulasi
litar SET seperti Array, Junction dan SET.
vi
TABLE OF CONTENT
CHAPTER
TITLE
PAGE
DECLARATION
ii
ACKNOWLEDGEMENTS
iii
ABSTRACT
iv
ABSTRAK
v
TABLE OF CONTENTS
vi
LIST OF TABLES
x
LIST OF FIGURES
xi
LIST OF APPENDICES
1
xiv
INTRODUCTION
1
1.1 Problems Faced to Scale-down MOSFET
3
1.2 Potential Nanoelectronics Devices and Application Areas
5
1.2.1 Single electron memory [6]
5
1.2.2 High sensitivity electrometer [6]
6
1.2.3 Microwave detection [6]
7
1.2.4 Application in the Metrology Area [7]
7
1.3 Theory of SET
8
1.4 History of SET
11
1.5 Types of SETS [8]
13
1.6 Objectives of the project
15
1.7 Scope of the project
16
1.8 Motivations
16
1.9 Methodology and Report Structure
16
vii
2
MONTE-CARLO SINGLE-ELECTRONS TRANSITOR
SIMULATOR
11
2.1 Simulation Approaches of Single Electron Circuits
20
2.1.1 SPICE macro-modeling
20
2.1.2 Monte Carlo [7]
20
2.1.3 Master Equation [7]
21
2.1.4 Advantages/ Disadvantages of Monte Carlo method
23
2.2 Simulators
2.2.1 MOSES Simulator
25
2.2.2 SIMON Simulator
26
2.2.3 KOSEC Simulator
28
2.2.4 SENECA Simulator
28
2.2.5 SPICE Simulator
28
2.3 Models of SETs
3
4
24
29
2.3.1 SET Model [37]
29
2.3.2 Single Electron Tunnel Junction
31
2.3.3 Coulomb blockade Model [38]
31
2.4 Conclusion
32
METHODOLOGY
29
3.1
Introduction of SET circuit modeling using MOSES [40]
33
3.2
Minimum Hardware and Software requirement [40]
34
3.3
Installation of MOSES [40]
34
3.4
Modeling SET circuit with MOSES [40]
35
RESULTS AND DISCUSSION
4.1
Problem of Making More Powerful Chips [38]
45
4.2 SET Transistor Function [38]
46
4.3
What is the “island”?
47
4.4
Coulomb blockade [39]
49
4.5
Single electron transistor with niobium leads and aluminum
island
4.6 Junction circuit simulation results
4.6.1 IV curve of Junction circuit
51
52
53
viii
4.6.5 Spectral Densities of Island Potentials
4.7 SET circuit simulation result
60
61
4.7.1 IV curve of SET circuit
62
4.7.4 Spectral Densities of Island Potential
67
4.8 Array circuit simulation result
68
4.8.1 IV curve of Array circuit
70
4.8.5 Spectral Densities of Island Potentials
75
4.8.6 Energy of a 21-junction array
76
4.8.7 Energies of a 21-junction array with different Vds
values
77
4.9 Comparison of Spectral Densities between Junction, SET and
Array circuit.
5
CONCLUSIONS AND FURTHER WORK
5.1 Positive Conclusion
79
5.2 Further improvement for this Project
79
5.3 Future research
79
5.4 A Final Note
80
REFERENCES
Appendix A
78
81
85 - 120
ix
LIST OF FIGURES
FIGURE NO.
TITLE
PAGE
1.1
Transfer of electrons
18
1.2
Tunnel Junction
10
1.3
SET is type of switching device
10
1.4
Energy level diagram
11
1.5
Schematic drawing of a SET
12
1.6
Flowchart on Project Methodology
16
1.7
Linux on VMWare
17
1.8
MOSES in Linux environment
18
2.1
Screenshot of MOSES
26
2.2
Screenshot of SIMON graphical interfaces
27
3.1
Tunnel junction circuit
36
4.1
A single-electron transistor diagram
46
4.2
Tunnel junction capacitance
47
4.3
Characteristic for two different gate voltages
48
4.4
IV curve of Single electron transistor
49
4.5
Tunnel Junction circuit
52
4.6
IV curve of Junction circuit with default value
53
4.7
IV curve with different Temperature value
54
4.8
IV curve with different Capacitance value
55
4.9
IV curve of Junction circuit with different capacitance value
56
4.10
IV curve of Junction circuit with different Resistance value
57
4.11
IV curve of Junction circuit with different Resistance value
58
4.12
IV curve of Junction circuit with different Resistance value
59
4.13
Spectral Densities of Island Potentials for Junction circuit
60
4.14
SET circuit
61
4.15
IV curve of SET circuit with default value
62
x
4.16
IV curve of SET circuit with different set of Temperatures
63
4.17
IV curve of SET with different set of capacitance (C2 variable)
64
4.18
IV curve of SET with different set of capacitance (C1 variable)
65
4.19
IV curve of SET with different set of capacitance (C2=C1)
66
4.20
Spectral Densities of Island Potential for SET circuit
67
4.21
Array circuit diagram
68
4.22
IV curve of Array circuit with default value
70
4.23
IV curve of Array circuit with different Temperature value
71
4.24
IV curve of Array circuit with variable Capacitance
72
4.25
IV curve of Array with variable Capacitance (increment and
decrement order)
73
4.26
IV curve of Array circuit with different conductance value
74
4.27
Spectral Densities of Island Potentials for Array circuit
75
4.28
Energy of 21-junction array circuit
76
4.29
Energies of a 21-junction array with one extra electron on node i
77
4.30
Comparison of Spectral Densities of Island potentials for Junction,
SET and Array circuit.
78
xi
LIST OF APPENDIX
APPENDIX
A
TITLE
Monte-Carlo Single Electronics Simulator
PAGE
85
CHAPTER 1
INTRODUCTION
This project studies about the single electron transistor (SET) properties by
simulating 3 types of circuits with Monte-Carlo Single Electronics Simulator
(MOSES). Single-electron transistor (SET) is a device to amplify current in
nanoelectronics. Basically there are three types of SET circuit based on its scale. The
first one is tunnel junction which in short is called Junction, is the elementary
structure of SET. The second one is the SET itself which consists of 2 tunnel
junction. The third one consists of more than one SET (in this project is 21) and is
called Array circuit. As explained in Result and Discussion, we can see a
tremendous different among this three for IV curve, Spectrum densities and Energy.
We also simulate these circuits using different value of external factors such as
capacitance and temperatures.
Semiconductor electronics have seen a sustained exponential decrease in size
and cost and a similar increase in performance and level of integration over the last
thirty years. From computers that take up the entire room to handhelds to embedded
computers. George E. Moore, the co-founder of Intel had predicted this in what is
known as the Moore’s Law.
“The complexity for minimum component costs has increased at a
rate of roughly a factor of two per year ... Certainly over the short
term this rate can be expected to continue, if not to increase. Over
the longer term, the rate of increase is a bit more uncertain,
although there is no reason to believe it will not remain nearly
constant for at least 10 years. That means by 1975, the number of
2
components per integrated circuit for minimum cost will be 65,000.
I believe that such a large circuit can be built on a single wafer.”
Although Moore's Law was initially made in the form of an observation and
forecast, the more widely it became accepted, the more it served as a goal for an
entire industry. This drove both marketing and engineering departments of
semiconductor manufacturers to focus enormous energy aiming for the specified
increase in processing power that it was presumed one or more of their competitors
would soon actually attain. In this regard, it can be viewed as a self-fulfilling
prophecy. And Moore’s Law is expected to hold for at least the next decade.
Based on Moore’s Law, a consortium of integrated circuit manufacturers
called the Semiconductor Industry Association (SIA) produced and estimate of how
technology is expected to evolve. The following table shows a sample of the SIA
roadmap [1].
Year
Transistor
1999
2001
2004
2006
2009
2012
0.14 µm
0.12 µm
90 nm
65 nm
50 nm
35 nm
14 million
16 million
24 million
40 million
64 million
100 million
80 mm2
850 mm2
900 mm2
1000 mm2
1100 mm2
1300 mm2
gate length
Transistors
per cm2
Chip size
Table 1: A sample of the SIA Roadmap
The first row of the table indicates that the minimum gate length is
expected to reduce steadily to about 35nm by year 2012. The size of transistors
determines how many transistors can be placed in a given amount of chip area.
We can see the need for smaller transistors, hence the driving force behind the
research of SETs.
SETs have been widely studied and demonstrated due to the maturity and
variety of their process technologies. These devices based on the single-electron
charging effect, i.e., the Coulomb blockade in Si nanostructures, are promising
3
because their operation principle becomes more robust as the device size is scaled
down unlike MOSFET, which will be further explained in the following section.
Moreover, their power consumption is quite low. However, SETs are not expected to
replace the conventional CMOS logic devices because of their inherent limitations
such as a low voltage gain and current drivability. In contrast, new functionalities of
SETs, such as quantum cellular automata (QCA), binary decision diagram (BDD)
devices, and the multivalued logic, have been explored extensively [2].
1.1 Problems Faced to Scale-down MOSFET
The metal-oxide-semiconductor field-effect transistor (MOSFET, MOS-FET,
or MOS FET), is by far the most common field-effect transistor in both digital and
analog circuits. The MOSFET is composed of a channel of n-type or p-type
semiconductor material, and is accordingly called an NMOSFET or a PMOSFET
(also commonly called nMOSFET, pMOSFET, NMOS FET, PMOS FET, nMOS
FET, pMOS FET).
The MOSFET has become the basic element of all silicon integrated circuits.
The growth of digital technologies like the microprocessor has provided the
motivation to advance MOSFET technology faster than any other type of siliconbased transistor. The principal reason for the success of the MOSFET was the
development of digital CMOS logic, which uses p- and n-channel MOSFETs as
building blocks. The great advantage of CMOS logic is that they allow no current to
flow (ideally), and thus no power to be consumed, except when the inputs to logic
gates are being switched. CMOS accomplishes this by complementing every
nMOSFET with a pMOSFET and connecting both gates and both drains together. A
high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET
not to conduct and a low voltage on the gates causes the reverse. During the
switching time the voltage goes from one state to another and both will conduct.
This arrangement greatly reduces power consumption and heat generation.
4
Overheating is a major concern in integrated circuits, since ever more transistors are
packed into ever smaller chips.
The steady reduction in the minimum feature size in integrated circuits has
helped the microelectronic industry to produce products with spectacular increase in
computational capability and integration density at lower cost. Smaller transistors
operate faster than larger ones, and for a given chip technology, the cost of a chip
decreases with area rather than with the number of transistors. As scaling down of
MOSFET proceeds, we are faced with extremely shallow source and drain (S/D)
junctions with low resistances.
As for the CMOS, when its dimension is scaled to the deep nanometer arena,
in particular the channel length, the electrical barriers in the device begin to lose
their insulating properties due to thermal injection and quantum-mechanical
tunneling. This results in a rapid rise of the standby power of the chip, placing a
limit on the integration level as well as on the switching speed.
The major limiting factors are power and threshold voltage, tunneling
leakage through gate oxide, lithography, short-channel effect, high-field effects,
dopant number fluctuations, interconnect delays and electrostatic scale length. Both
the standby power and the active power of a chip will increase precipitously below
the 45nm technology generation.
Conventional scaling will no longer be sufficient to continue device
performance by creating smaller MOSFET/CMOS, it will be running into
fundamental barriers of physics. It is reported in [3] that the minimum MOSFET
structure for a power supply voltage of 1.5V has a channel length of 0.52µm and a
gate oxide thickness of 9.4 nm. Difficult challenges lie ahead in tightening process
tolerances to satisfy more stringent defect density and reliability requirements in
future generation CMOS technologies. Thus, alternatives like SETs are being
pursued.
5
1.2 Potential Nanoelectronics Devices and Application Areas
Single-electron tunneling (SET) devices have been proposed in [4] as one
promising candidate for future nanoelectronic integrated circuits. SETs have
appealing properties for implementing ultra-dense and complex signal and image
processing systems. The potential for very dense arrays of SET transistors makes
them attractive for the realization of cellular non-linear network (CNN)
circuits, where locally-connected cells may alleviate the interconnect problem
facing conventional architectures as they scale. In this paper, the use of
nanoelectronic structures in CMOS-type digital circuits and in analog CNN
architectures for potential application in future high-density and low-power
CMOS-nanodevice hybrid circuits are investigated. The simple SET-CNN cell
acts as a summing node that is capacitively coupled to the inputs and outputs of
nearest neighbour cells.
SETs are also of increasing interest for their potential in room
temperature application, high density memory and logic circuits with
conventional silicon VLSI processing techniques because of its small size, low
power consumption and high sensitivity.
It is reported in [7] that memory device is the most promising and lucrative
application of SETs, which in principle could store one bit of information with one
electron. Several companies have single-electron memory products in their roadmap
for a planned release in the 2010 to 2015 time frame.
1.2.1 Single electron memory [6]
Scientists have long been endeavored to enhance the capacity of memory
devices. If single electron memory can be realized, the memory capacity is possible
to reach its utmost limit. SET can be used as memory cell since the state of Coulomb
6
island can be changed by the existence of one electron. Chou and Chan first pointed
out the possibility of using SET as memories in which information is stored as the
presence or absence of a single electron on the cluster. They fabricated a SET by
embedding one or several nano Si powder in a thin insulating layer of SiO2, then
arranging the source and drain as well as gate around this Coulomb island. The
read/write time of Chan's structure is about 20ns, lifetime is more than 109 cycles,
and retention time (during which the electron trapped in the island will not leak out)
can be several days to several weeks.
These parameters would satisfy the standards of computer industry, so SET
can be developed to be a candidate of basic computer units. If a SET stands for one
bit, then an array of 4~7 SETs will be substantial to memorize different states. The
properties of the memory unit composed of SETs are far more advantageous than
that of CMOS. But the disadvantage is the practical difficulty in fabrication. When
the time comes for the large scale integration of SETs to form logic gates, the full
advantages of single electron memory will show. This is the threshold of quantum
computing.
1.2.2 High sensitivity electrometer [6]
The most advanced practical application currently for SETs is probably the
extremely precise solid-state electrometers (a device used to measure charge). The
SET electrometer is operated by capacitively coupling the external charge source to
be measured to the gate. Changes in the SET source-drain current are then measured.
Since the amplification coefficient is very big, this device can be used to measure
very small change of current.
Experiments showed that if there is a charge change of e/2 on the gate, the
current through the Coulomb island is about 109 e/sec. This sensitivity is many
orders of magnitude better than common electrometers made by MOSFET. SETs
have already been used in metrological applications as well as a tool for imaging
7
localized individual changes in semiconductors. Recent demonstration of single
photon detection and RF operation of SETs make them exciting for new applications
ranging from astronomy to quantum computer read-out circuitry.
The SET electrometer is in principle not limited to the detection of charge
sites on a surface, but can also be applicable to a wide range of sensitive chemical
signal transduction events as well. For example, the gate can be made coupling with
some molecules, thus can measure other chemical properties during the process.
However, as Lewis K M etc. pointed out , SETs electrometer must be designed with
care. If the device under test has a large capacitance, it is not advantageous to use
SETs as an electrometer. Since for a typical SET, CSET <1μF, the suppression factor
becomes unacceptable when the macroscopic device has a capacitance in the pF or
nF range.
Therefore, SET amplifiers are not currently used for measuring real
macroscopic devices. Other low-capacitance electrometers such as a recently
proposed quantum point contact electrometer also suffer from a similar capacitance
mismatch problem. But it is believed that if the capacitance mismatch can be solved
efficiently, SETs may find many new ultra low-noise analog applications.
1.2.3 Microwave detection [6]
If a SET is attacked black body radiation, the photon-aided tunneling will
affect the charge transfer of the system. Experiments show that the electric character
of the system will be changed even by a tiny amount of radiation. The sensitivity of
this equipment is about 100 times higher than the current best thermal radiation
detector.
8
1.2.4 Application in the Metrology Area [7]
For metrology purposes one can accept setups with cryogenic temperatures
allowing structures with dimensions in the tens of nanometers. Devices for precise
current and capacitance measurements achieved by essentially counting electrons
have been built successfully. These exhibit unprecedented accuracy over traditional
methods. Super sensitive electrometers and the use of tunnel junction arrays as
single-electron primary temperature sensors are very promising application. From an
economical point of view metrology applications will hardly be noticed. But their
development can provide important insight and fresh ideas for other single-electron
application areas.
1.3 Theory of SET
The need for fast switching and lower power consumption is the main
goal of semiconductor technology. Shrinkage in device dimensions raises
switching frequencies and reduces power consumption. In sub-micron
dimensions, quantum tunneling affects the MOSFET operation due to electron
transport by tunneling from source to drain. Recently a new transistor was
invented; the single electron transistor (SET) that operates on tunneling
phenomena. This transistor turns on when one electron tunnels from source to
drain. Figure 1.1 explains clearly the difference between SET and MOSFET.
Figure 1.1: Transfer of electrons is (a) one-by-one in SET (b) conventional
MOSFET where many electrons simultaneously participate to the drain current
9
The tunnel junction is the smallest unit cell of single electron transistor. It
consists of two conductors separated by a thin insulator. Figure 1.2 shows the
diagram of tunnel junction. The only way for electrons to move across the tunnel
junction is to tunnel through. Although tunneling is a probability distribution
function, electrons tunnel across the tunnel junction in a discrete manner.
Figure 1.2: Tunnel junction consists of 2 metals that are separated by a thin
insulator. Because of the separation, capacitance is formed and they are
represented by capacitor value in the circuit.
Connecting two tunnel junctions together forms what is known as the
Coulomb island, as this elemet is what we call as Single Electron Transistor
(SET). This is shown by Figure 1.3.
Figure 1.3: SET is type of switching device that uses controlled electron
tunneling to amplify current
No electron can reside on the island unless its kinetic energy exceeds the
Coulomb energy of the island, Ec, which is known as the Coulomb blockade.
10
where, C is the total capacitance of the island. The island is capacitively coupled
to the gate electrode by a thick insulating layer to prevent tunneling between the
island and the gate. With zero voltage applied to the gate, the island's Coulomb
energy blocks the current from drain to source until the drain-source voltage
exceeds the threshold voltage, Vth
The gate voltage controls the charging energy of the island and
consequently it controls the Coulomb blockade. Applying an appropriate value of
gate voltage can thus eliminate the Coulomb blockade.
Figure 1.4: Energy level diagram
Single electron transistor operation can be explained by the orthodox
theory. In this theory the tunneling rate across each tunnel junction of the
transistor is calculated. The tunnel rate is derived from the Fermi golden rule
taking into consideration the change in free energy of the system. The free energy
is equivalent to the energy change caused by a tunnel event in the orthodox
theory. The Fermi golden rule states that the transition rate (tunnel rate) is highest
when the change in free energy before and after the tunnel event is minimal. The
change in free energy is the difference between the electrostatic energy of the
system and the work done by voltage sources before and after the tunnel event.
11
The change in free energy can be simply derived by the method of critical
voltage.
Utilizing the orthodox theory with statistical mechanics develops the
master equation. It computes the time dependent occupation for each state in the
system. The drain-source current of the transistor is computed using the results of
the master equation. [5]
1.4 History of SET
The effects of charge quantization were first observed in tunnel junctions
containing metal particles as early as 1968. Later, the idea that the Coulombb
blockade can be overcome with a gate electrode was proposed by a number of
authors, and Kulik and Shekhter developed the theory of Coulomb-blockade
oscillations, the periodic variation of conductance as a function of gate voltage.
Their theory was classical, including charge quantization but not energy
quantization. However, it was not until 1987 that Fulton and Dolan made the first
SET, entirely out of metals, and observed the predicted oscillations. They made a
metal particle connected to two metal leads by tunnel junctions, all on top of an
insulator with a gate electrode underneath. Since then, the capacitances of such
metal SETs have been reduced to produce very precise charge quantization. The
first semiconductor SET was fabricated accidentally in 1989 by Scott-Thomaset
in narrow Si field effect transistors. In this case the tunnel barriers were produced
by interface charges.
12
Figure 1.5: Schematic drawing of a SET. Wires are connected to source
and drain contacts to pass current through the 2DEG at the
GaAs/AlGaAs interface. Wires are also connected to the confining
electrodes to bias them negatively and to the gate electrode that
controls the electrostatic energy of the confined electrons.
Shortly thereafter Meirav et al. made controlled devices of the kind
depicted in Fig. 1.5, even though with an unusual heterostructure with AlGaAs
on the bottom instead of the top. In these and similar devices the effects of
energy quantization were easily observed. Only in the past few years have metal
SETs been made small enough to observe energy quantization. Foxman et al. also
measured the level width Γ and showed how the energy and charge quantization
are lost as the resistance decreases toward h/e2. In most cases the potential
confining the electrons in a SET is of sufficiently low symmetry that one is in the
regime of quantum chaos: the only quantity that is quantized is the energy. In this
case there is a very sophisticated approach, based in part on random matrix
theory, for predicting the distributions of peak spacings and peak heights for data.
There are challenging problems in this arena that are still unsolved. In particular,
there is great interest in how the interplay of exchange and level spacing
determines the spin of a small metal SET. Another way to eliminate the
scattering that destroys angular momentum conservation is to apply a magnetic
field perpendicular to the 2DEG. At sufficiently M. A. Kastner, Single electron
transistor and artificial atoms 893 high fields elegant patterns are seen in the
single-electron-peak positions as a function of field. The evolution of Coulomb
charging peaks with magnetic field have been interpreted with various degrees of
sophistication, imitating the development of the theory of atoms. First one tries
the “constant interaction model” in which electrons are treated as independent
13
except for a constant Coulomb charging energy. This gives only a qualitative
picture of the physics. In order to be quantitative, one needs to at least treat the
electron-electron interactions self-consistently (analogous to the Thomas-Fermi
model), and for some cases one needs to include exchange and correlations. In
particular, it is found that electrons in an SET undergo a series of phase
transitions at high magnetic field. One of these is well described by Hartree-Fock
theory, but others appear to require additional correlations. [5]
1.5 Types of SETS [8]
Single-electron transistors can be made using metals, semiconductors, carbon
nanotubes, or single molecules. Aluminum SET's made with Al/AlOx/Al tunnel
junctions are the SET's that have been used most often in applications. This kind of
SET is used in metrology to measure currents, capacitance, and charge. They are
used in astronomical measurements and they have been used to make primary
thermometers. However, many fundamental single-electron measurements have
been made using GaAs heterostructures. The island of this kind of SET is often
called a quantum dot. Quantum dots have been very important in contributing to our
understanding of single-electron effects because it is possible to have just one or a
few conduction electrons on a quantum dot. The quantum states that the electrons
occupy are similar to electron states in an atom and quantum dots are therefore
sometimes called artificial atoms. The energy necessary to add an electron to a
quantum dot depends not just on the electrostatic energy of Eq. 2 but also on the
quantum confinement energy and the magnetic energy associated with the spin of
the electron states. By measuring the current that flows thorough a quantum dot as a
function of the gate voltage, magnetic field, and temperature allows one understand
the quantum states of the dot in quite some detail.
The SET's described so far are all relatively large and have to be measured at
low temperature, typically below 100 mK. For higher temperature operation, the
SET's have to be made smaller. Ono et al. [9] used a technique called pattern
14
dependent oxidation (PADOX) to make small silicon SET's. These SET's had
junction capacitances of about 1 aF and a charging energy of 20 meV. The silicon
SET's have the distinction of being the smallest SET's that have been incorporated
into circuits involving more than one transistor.
Specifically, Ono et al. constructed an inverter that operated at 27 K. Postma
et al. [10] made a SET that operates at room temperature by using an AFM to buckle
a metallic carbon nanotube in two places. The tube buckles much the same way as
a drinking straw buckles when it is bent too far. Using this technique, a 25 nm
section of the nanotube between the buckles was used as the island of the SET and a
conducting substrate was used as the gate. The total capacitance achievable in this
case is also about 1 aF.
Pashkin et al. [11] used e-beam lithography to fabricate a SET with an
aluminum island that had a diameter of only 2 nm. This SET had junction
capacitances of 0.7 aF, a charging energy of 115 meV, and operated at room
temperature.
SET's have also been made by placing just a single molecule between closely
spaced electrodes. Park et al. [12] built a SET by placing a C60 molecule between
electrodes spaced 1.4 nm apart. The total capacitance of the C60 molecule in this
configuration was about 0.3 aF. Individual molecules containing a Co ion bonded
to polypyridyl ligands were also placed between electrodes only 1-2 nm apart to
fabricate a SET. [14] In similar work, Liang et al. [13] placed a single divanadium
molecule between closely spaced electrodes to make a SET. In the last two
experiments, the Kondo effect was observed as well as the Coulomb blockade. The
charging energy in the molecular devices was above 100 meV.
One of the conclusions that can be drawn from this review of SET devices is
that small SET's can be made out of a variety of materials. Single electron transistors
with a total capacitance of about 1 aF were made with aluminum, silicon, carbon
nanotubes and individual molecules. It seems unlikely that SET's with capacitances
smaller than the capacitances of the molecular devices can be made. This sets a
15
lower limit on the smallest capacitances that can be achieved at about 0.1 aF.
Achieving small capacitances such as this has been a goal of many groups working
on SET's. However, while some of the device characteristics improve as a SET is
made smaller, some of the device characteristics get worse as SET's are made
smaller. For some applications, the single molecule SET's are too small to be useful.
As SET's are made smaller, there is an increase in the operating temperature,
the operating frequency, and the device packing density. These are desirable
consequences of the shrinking of SET devices. The undesirable consequences of the
shrinking of SET's are that the electric fields increase, the current densities increase,
the operating voltage increases, the energy dissipated per switching event increases,
and the power dissipated per unit area increases, the voltage gain decreases, the
charge gain decreases, and the number of Coulomb oscillations that can be observed
decrease.
The future of research on SETs looks very bright. There are strong efforts
around the world to make the artificial atoms in SETs smaller, in order to raise
the temperature at which charge quantization can be observed. These involve
self-assembly techniques and novel lithographic and oxidation methods whereby
artificial atoms can be made nearly as small as natural ones. This is, of course,
driven by an interest in using SETs for practical applications. However, as SETs
get smaller, all of their energy scales can be larger, so it is very likely that new
phenomena will emerge. [5]
1.6 Objectives of the project
•
To study nanoelectronics devices in particular SET
•
To simulate Single Electron Transistor (SET) circuits using Monte Carlo
method
•
To study functions of MOSES in simulating SET circuits.
16
1.7 Scope of the project
Due to the time constraint of Project 1 and 2, three SET circuits: Array,
SET and Junction circuits are simulated. The areas of the simulation are mainly
on IV curve, Spectral densities and Energies, and observations are made on the
circuit behaviour when the value of capacitance and temperature change.
1.8 Motivations
SET is of increasing interest not only from the fundamental point of view
but also for their potential room-temperature application to very high density
memory and logic circuits with conventional silicon VLSI processing techniques.
As in the case of the conventional CMOS circuit design, the modeling of devices
and the simulation of the circuit would be a key step to design the SET circuits.
In the case of the conventional circuit, the compact simulators such as MOSES
are used to simulate the characteristics of the given circuit topology.
1.9 Methodology and Report Structure
VMWare 5.0, Redhat Linux 8.0 and MOSES installation
Decide on SET circuits to simulate, external factors
Simulate SET circuits on IV curve, Spectrum densities and
Energy with different factors
Conclusion on findings
Figure 1.6: Flowchart on Project Methodology
17
Prior to MOSES installation, having Linux installed in the system is
compulsory since it only runs on Linux environment. Since there is no budget to
have dedicated PC to run specifically on Linux, I have decided to turn my PC to
run two operating systems by installing VMWare. VMWare, as its name stands
for Virtual Machine allows more than one operating system to run on the same
machine. Figure 1.7 shows Linux in Windows environment using VMWare.
Figure 1.7: By using VMWare, it is possible to have more than one OS in the
same machine
After installing VMWare, Linux and MOSES, it is time to decide on what
types of SET circuits to be simulated. For this purpose three SET circuits have
been finalized: Array, SET and Junction circuits. These circuits are selected since
there are varieties on IV curve, Spectrum densities and Energy results among
them.
18
Figure 1.8: MOSES in Linux environment
After the raw results are displayed, they are then transferred to Microsoft
excel for graph plotting, since this function is having problem in MOSES
application.
Finally, there is a discussion on what have the result shown based on
comparison with current SET research community, especially from IEEE Xplore
on the net.
CHAPTER 2
SINGLE-ELECTRONICS TRANSISTOR SIMULATORS & MODELS
The first observations of the Coulomb blockade and thus single electronics
were made by Gorter in 1951. He studied granular thin-film structures, and
discovered a low-voltage suppression of the dc conductivity. He already identified
the reason for the conductivity suppression due to charging of grains with single
electrons. In the past decade, knowledge and understanding of single electronics
grew, due to the available production processes for small structures. It was then for
the first time possible to study a single grain or small tunnel junction, and thus one
did not have to deal with averaged characteristics of granular films consisting of
thousands of grains. A theory explaining quantitatively charging effects and the
Coulomb blockade appeared at the end of the past decade [15]–[17]. Today, we see
more and more publications dealing with the circuit level of single electronics [18]–
[20], and the first applications have been developed [21], [22].
To support circuit level design, some simulators have been implemented or
are under construction. Among them are SENECA by Fonseca et al. [23] at Stony
Brook State University of New York, MOSES by Chen et al. [24] at Stony Brook
State University of New York, Ancona at Naval Research Laboratory, Washington
[20], Kirihara et al. [25] at Osaka University, Fukui et al. [19] and Amakawa at
Tokyo University, Kuwamura et al. [26] at Osaka University, Kautz at NIST
Colorado and Ferry at Arizona State University, Masu and Tsubouchi at Tohoku
University, Amemiya at Hokkaido University, and Simon [36] at TU-Vienna.
20
2.1 Simulation Approaches of Single Electron Circuits
There are three fundamentally different approaches to the simulation of single
electron circuits: SPICE macro-modeling, Monte Carlo based and Master Equation
based. This project uses Monte Carlo based simulation.
2.1.1 SPICE macro-modeling
One can model the IV characteristic of a single-electron transistor the same
way a bipolar or MOSFET transistor is modeled in SPICE [27]. The advantage is
that SPICE is significantly faster than the typical single-electron simulator based on
the Monte Carlo method or the Master Equation. This opens the potential to simulate
very large single-electron circuits. The big disadvantage is that it does not capture
any Coulomb interaction between adjacent transistors, which in many cases is very
important for a correct circuit analyses. This deficiency could be remedied with a
pre-processing step, which resolves all global dependencies before the actual singleelectron simulation is performed [28].
2.1.2 Monte Carlo [7]
The Monte Carlo approach starts with all possible tunnel events, calculates
their probabilities, and chooses one of the possible events randomly, weighted
according to their probabilities. This is done many times to simulate the transport of
electrons through the network. Tunnel events are considered to be independent and
exponentially distributed.
The orthodox single-electron theory yields a tunnel rate equation for any
junction in a large circuit [29]:
21
where ΔF is the change in free energy when an electron passes through the tunnel
junction. RT is the tunnel resistance and Γ the tunnel rate. The change in free energy,
which can be loosely understood as the change in system energy, has to be taken
from the entire circuit. The calculation of ΔF can be efficiently done through the
system capacity matrix [28].
If this tunnel rate is coupled into a Poisson process the fundamental building
blocks for a Monte Carlo based simulation are assembled. The Poisson distribution
can be rearranged to yield
where r is an evenly distributed random number from the interval [0,1] and τ is the
time at which an electron tunnels through the junction.
The Monte Carlo procedure is then as follows. Starting from a list of all
possible tunnel events with their particular tunnel rates under present biasing
conditions, concrete random tunnel times τi are computed for all events. The event
with the smallest τ will happen first and is taken as the winner of the Monte Carlo
step. Charges and voltages are updated on all circuit nodes. New tunnel rates are
calculated and a new winner is determined through stochastic sampling. If this
procedure is done many times, the macroscopic behavior of the circuit can be
calculated.
As with any Monte Carlo simulation it warrants to think about appropriate
random number generators as well as possible variance reducing algorithms.
Correlations in pseudo-random numbers can dangerously alter simulation results
[30].
22
One of the most effective variance reducing algorithms for single-electron
simulation purposes is a scheme developed by the father of Monte Carlo methods,
Stan Ulam [31]. The large variance in simulation results stems from the fact, that
some tunnel junctions exhibit a very low tunnel rate. This means that one would
have to simulate a large number of tunnel events to get an accurate electric current
reading through these rarely tunneled junctions. A quite simple remedy to this
problem is to spread out the elementary charge according to all tunnel rates of events
the electron could follow. This means that for every event even the very low
probability transport channels get some tiny contribution to their current average.
This smearing of the charge is only possible for current averaging. The node charge
progression still has to be done by elementary charges, otherwise the Coulomb
blockade would not be simulated correctly.
2.1.3 Master Equation [7]
The Monte Carlo method achieves its results by stochastic integration. Many
events are taken together in average to yield the correct result. Alternatively one can
find a set of equations to describe the charge transport processes in single-electron
circuits, which can be solved deterministically.
where Γij denotes the transition rate from charge state j to state i and Pi(t) is the time
dependent occupation probability of state i. This equation system is referred to as the
Master Equation.
The solution of above Master Equation is formally very easy. It is a matrix
exponential. However, numerically it is quite difficult to evaluate a matrix
exponential accurately for a general case. Very good and sophisticated methods are a
Krylov subspace method and a Schur-Fréchet algorithm [28]. Simpler methods, such
as Padé approximations seem to work sufficiently well for the
single-electron case [32].
23
The calculation of tunnel rates is done in the same way as with the Monte
Carlo method. The major problem however with the Master Equation approach is
that in order for one to write down the system of equations one has to know all
relevant states a circuit can occupy. Since the number of possible states is infinite
one has to find the ones that matter most. And this is for most circuits impossible to
do a priory, either because any simple scheme would yield too many states making
the matrix too large, or the few states which matter are unknown. One has to apply
an adaptive scheme where one starts with a set of states or just one state and
progressively searches the state space for more relevant states [32].
For very small circuits the Master Equation has its advantages over the
Monte Carlo method. It is faster and has no problems resolving very rare events.
Nevertheless, the number of states necessary to include in ones analyses grows
exponentially with the size of the circuit and renders a Master Equation very quickly
infeasible.
2.1.4 Advantages and Disadvantages of Monte Carlo method
Monte Carlo method is superior to other approaches because of the following
advantages. That is it can be observed that most simulators (e.g. MOSES, SIMON
and KOSEC) use the Monte Carlo Method to simulate single electron circuits.
It gives better transient and dynamic characteristics of SET circuits because
it models the underlying microscopic physics in a very direct manner. In real SET
circuits, electrons tunnel from island to island as simulated by the Monte Carlo
method. The master equation deals with average probabilities and transition rates,
which paint a more macroscopic picture. It is not required to find the relevant states
before one can start with the actual simulation as in the case of a master equation.
For an unknown circuit, no a priori knowledge about relevant states is available.
Thus, in the case of the master equation approach, one needs to include many more
than relevant states to correctly simulate the circuit. Considering more states means
24
longer simulation time and decreased numerical stability.
It is easy to trade accuracy with simulation time, and therefore one can
quickly achieve approximate results of very large circuits. To speed up the solution
of the master equation, one can only limit the considered states. Because of the lack
of knowledge of which states are dominating the behavior of the circuit, a reduction
of states is very often impossible.
Nevertheless, there is one major disadvantage of the Monte Carlo method.
When it comes to simulating cotunneling, a plain Monte Carlo approach has its
limitations. Cotunneling is a very rare process which is difficult to resolve by a
Monte Carlo method. It demands very long simulation times.
Disregarding the long simulation time, [7] opined that Monte Carlo is still
the most suitable and versatile method for the analysis of single electron circuits.
2.2 Simulators
The commonly used simulators are MOSES, SIMON, and KOSEC. These
simulators have procedures to calculate the charge states of all the Coulomb islands
altogether to take into account of the interaction between neighboring Coulomb
islands. These procedures are usually based on the Monte Carlo technique and
require a huge amount of computation time because the Monte Carlo method
requires the calculation of the average charge states in each step and complete
bookkeeping of all the steps are essential. Other simulators include SENECA,
SPICE, etc.
25
2.2.1 MOSES Simulator
MOSES (Monte-Carlo Single-Electronics Simulator) is a single-electron
tunnel device and circuit simulator that is based on a Monte Carlo method. It
allows transient and stationary simulation of arbitrary circuits consisting of tunnel
junctions, capacitors, and voltage sources of three kinds: constant, piecewise linearly
time dependent, and voltage controlled. Cotunneling can be simulated either with a
half Monte Carlo method or with a full Monte Carlo method.
Features of the current version of MOSES include: [33]
• Simulation of single-electron dynamics
• Handling of arbitrary single-electron circuits consisting of tunnel junctions,
capacitors, resistors and signal sources (DC, harmonic and/or pulsed)
• Calculation of DC IV curves, energy profiles, Coulomb blockade values, as well
as charge distributions reducing the Coulomb blockade to zero
• Account of suppression of quasiparticle currents in the superconducting case
• Graphical point-and-click circuit design tool "Kmoses"
• GIF-based motion picture generation for 1D and 2D arrays for direct observation
of electron/hole motion
• Calculation of spectral densities for DC currents at zero frequencies as well as at
finite frequencies
The follow figure shows a screenshot of the command line interface of
MOSES. MOSES runs on RedHat LINUX operating system and requires the KDE
graphical windows to run KMOSES, which provides a graphical user interface for
easier circuit design. MOSES is freely distributed in the Internet.
26
Fig. 2-2: Screenshot of MOSES
2.2.2 SIMON Simulator
SIMON is a single-electron tunnel device and circuit simulator that is based
on a Monte Carlo method. It allows transient and stationary simulation of arbitrary
circuits consisting of tunnel junctions, capacitors, and voltage sources of three kinds:
constant, piecewise linearly time dependent, and voltage controlled. Cotunneling can
be simulated either with a plain Monte Carlo method or with a combination of the
Monte Carlo and master equation approach. SIMON tackles the problem of long
simulation time taken when simulation uses Monte Carlo method by providing the
27
option to simulate the cotunnel using a combination of Monte Carlo and Master
Equation approach [34].
A graphic user interface allows the quick and easy design of circuits with
single-electron tunnel devices [34]. The graphical circuit editor allows a drag-anddrop assembly of SET circuits. Parameters can be changed interactively, and
simulation results can be looked at in graphical form. Also, all simulation
parameters, such as simulation mode, cotunnel order, and ambient temperature, are
modifiable. For screen shots of SIMON, see Fig. 2-1.
Fig. 2-1: Screenshots of SIMON graphical interface
28
SIMON is also freely available on the web and runs on SUSE Linux
operating system.
2.2.3 KOSEC Simulator
KOSEC (KOrea Single Electron Circuit simulator) is developed in
Nanoelectronics Laboratory, Korea University, Seoul, Korea. KOSEC employs the
Monte Carlo method as well. KOSEC is among the widely used simulator.
However, not much information could be found on the web, which most probably is
because its literature is in Korean language.
2.2.4 SENECA Simulator
SENECA is another important simulator for single electron circuits.
SENECA directly solve the master equation for the population probability of
Coulomb islands.
2.2.5 SPICE Simulator
SPICE stands for Simulation Program Integrated Circuits Especially.
The program originates from the University of California, Berkeley. SPICE is used
to provide a reasonably detailed analysis of circuits containing active components
such as bipolar transistors, field effect transistors, diodes and lumped components
such as resistors, capacitors and inductors.
SPICE simulation of SET circuits is possible by the macro modeling of
SETs. The macro modeling scheme is compatible with the standard method of
29
SPICE simulation, consisting of the device modeling using an equivalent circuit,
parameter extraction and subsequent circuit simulation. However, it is limited to the
simulation of steady-state conditions and it is not clear whether such an equivalent
circuit modeling scheme by handling each SET independently is also suitable for the
transient case [35].
Another development stream of SET/CMOS hybrid circuit simulator is the
SET-SPICE and the CAMSET. In these schemes, the SET is considered as a black
box and the state of the black box is determined by solving the steady-state or the
time-dependent master equation at a given bias condition. The routine for the
solution of the master equation is incorporated by the programming capability of
recent circuit simulators such as the Smart-Spice. Such simulators successfully
predict the transient response of SET circuits in a timescale of microseconds where
steady-state modeling can provide almost accurate simulation results [35].
2.3 Models of SETs
The basic working principle of single electronics is that one needs Coulomb
energy to charge a grain (island) with an electron where is the overall capacitance of
the grain. If this Coulomb energy is larger than the available thermal energy, one can
control the movement of electrons by controlling the available energy supplied by
voltage sources. In this project, Single-electron Tunnel (SET) circuits are
investigated. Other model of SET includes the Coulomb blockade Model.
2.3.1 SET Model [37]
The main quantum property of the SET device is the phenomenon of electron
tunneling. Tunneling deals with the penetration of a potential barrier, if the kinetic
energy of an electron approaching the barrier is smaller than the potential energy
30
height of the barrier. In case of tunneling there is a finite possibility, of finding the
electron at the other side of the barrier.
Fig.2-4: Model of the SET junction: (a) the SET junction symbol (b) the junction
modeled as a capacitance parallel to a discrete current source
Any circuit including SET devices can be described by a discrete charge
transfer through the tunnel barriers coexisting with a continuous charge transfer
along the rest of the circuit. In addition to the orthodox theory of single-electronics
that basically describes the circuit behavior in terms of the in physics well-defined
free energy, we recently proposed a model based on (electronic) network concepts.
In this model we describe tunneling through the SET device as a discrete charge
transfer:
that is coexisting with continuous (and discrete) transfer through the rest of the
circuit. The condition for tunneling is based on, again, an energy argument.
Tunneling may occur when energy is lost at the tunnel junction, eδ, between the time
immediately before and the time immediately after the tunnel event. Tunneling may
also take place when the energy loss is zero. The tunnel condition now becomes:
Uj,a, and Uj,b are the voltages over the junction after and before the tunnel event,
respectively. Immediately from Equation 2 it follows that we can rewrite the tunnel
condition into:
31
in which δqj is the change in charge after redistribution at the junction. The δqj is
only known after the simulation of a possible tunnel event; Simulation of a tunnel
event will therefore be an iterative process. The fraction δqj /Cj is efined as the
critical voltage U"' if the following condition holds:
Based on this SET model, a model for the tunnel junction, suitable for the MOSES
simulator, is proposed. The model for the junction is valid for temperatures T for
which holds: kT << Ec, Ec is the Coulomb energy.
2.3.2 Single Electron Tunnel Junction
SET circuits consisting of islands that are arbitrarily connected with tunnel
junctions and capacitors and which are driven by voltage sources are investigated.
Voltage sources are considered to be ideal; thus, their internal resistance is zero.
Electrons tunnel independently from island to island through tunnel junctions,
changing the charge distribution in the circuit. Electron states are localized on islands.
To assure this, all tunnel resistances must be larger than the fundamental resistance
2.3.3 Coulomb blockade Model [38]
The Coulomb blockade Model, or sometimes just simply referred as the
Coulomb Island is a simple model that explains why a small region of electron gas,
separated by tunnel junctions from its leads, has a conductance that oscillates with
density. It was developed by Zeller and Giaever in the 60s. The following figure
illustrates the Coulomb blockade System.
32
Fig. 2-3: Sketch of Coulomb blockade System. The top part shows electrons tunnel
from one lead onto a metal particle and subsequently off the particle onto the other
lead. The bottom part shows the energy level spectrum for this system, showing
filled (hatched) and empty (shaded) levels. The metal particle has a gap of width
e2/C in its tunneling density of states.
For a tunnel barrier containing a metal particle, as shown above, it would
have been thought that electrons could tunnel from one plate of the capacitor onto
the metal particle and subsequently to the other plate of the capacitor. However, due
the Coulomb interaction between electrons residing on the particle this does not
happen. Current flow requires the addition of an electron or hole to the particle.
Adding an electron therefore requires a Coulomb energy e2/C, which is what we
refer to as an energy gap in the tunneling density of states. For an electron to tunnel
onto the particle it must have an energy above the Fermi energy in the contact by
e2/C , and for a hole to tunnel it must have an energy below the Fermi energy by the
same amount, so the gap has width e2/C.
2.4 Conclusion
Certainly there is no absolute method to model SET, and since this project
tries to limit the cost as low as possible, MOSES is a reasonable choice. As far as
Monte Carlo method is concern, there is no cotunneling pheomena included in
MOSES package.
CHAPTER 3
SET CIRCUIT MODELLING AND SIMULATION
3.1
Introduction of SET circuit modeling using MOSES [40]
MOSES 1.2 is an extension of MOSES 1.1 by Ruby Chen, created so far
only for UNIX. Original 1.1 version has been a useful tool for the past 6 years for
most researchers in the field of single electronics. However, as the field of research,
as well as user expectations advanced, it became more and more necessary to update
some parts. Update of the text based simulation program was mainly undertaken by
Daniel Kaplan during 1999-2001. Also, MOSES 1.1 had an intuitive and powerful
text based interface, but it did not give you the option to see the circuit graphically,
which made it hard to work with large circuits. Out of these concerns grew Kmoses
–the graphical circuit design tool- the work of Özgür Türel. MOSES 1.2 package
unites these two projects and includes;
1. The updated text based simulation program, "ms".
2. The graphical interface, "Kmoses".
3. 1D and 2D array circuit generation programs, "cgen.f" and "cgen2.f"
4. The executable required for making movies, "gifmerge"
5. File for generating the time-independent movies, "mergeframes"
6. A program that generates "tmerge" - the equivalent of "mergeframes" for
time-dependant movies, "mg.f".
The text based package, the one that I use in this project, consists of the following
archive files:
1. Sources: src.tar.gz,
2. Binaries: msbin.tar.gz,
3. Sample setup files (.crc and .set): samples.tar.gz,
34
4.
Support files: ms12sup.tar.gz,(includes cgen.f, cgen2.f, gifmerge,
mergeframes, mg.f)
3.2
Minimum Hardware and Software requirement [40]
The text based simulation program, ms, is written in Fortran 77 and C. Any
decent Fortran 77 and C compiler should be able to compile it, though it is only
tested on RedHat Linux 6.2 with g77 gcc. We can download the compilers free of
charge from this website:
http://www.gnu.org
The graphical front end, Kmoses, is written in C++ and requires the graphical
interface libraries kdelibs > 2.1 and qt > 2.3.0. Both of these libraries can be
obtained free of charge from:
http://www.kde.org
http://www.trolltech.com
3.3
Installation of MOSES [40]
In order to install this program, you need to have kdelibs version 2.2 and qt-
2.3.1. These two libraries are needed to compile MOSES.
Once you have the libraries installed, first untar and unzip the archive,
kmoses0.1.tgz
The LINUX command to untar:
tar zxvf kmoses0.1.tgz
Then, in the directory kmoses, in order to install the program.
./configure
After this step, type this command to compile the program.
35
make
make install
3.4
Modeling SET circuit with MOSES [40]
MOSES is capable to simulate SET circuit using Monte carlo method to
generate IV curve, spectrum densities and Energy plot. It is vital to have a strong
fundamental knowledge of Single electronics prior to simulation the circuit to enable
to understand terms used in the programs.
To start the program, in the Linux command prompt, type:
ms
This brings up MOSES startup information:
36
To examine IV curve of SET circuit, first we need to model a circuit by
inserting all the parameters. Start by entering the circuit: (This example is to model a
tunnel junction circuit, as shown by figure)
Figure 3.1: Tunnel junction as represented by electronics circuit
As we can see from Figure, the node between the resistor and the tunnel junction is
an island; then there are two externals, one on each end of the circuit. Insert this
information into MOSES
37
Let the resistor connect external 1 and island 3, and the tunnel junction, island 3 and
external 2. Then:
Now enter settings to plot the IV characteristic of the tunnel junction:
38
To calculated IV curves, we'll need to use Multiple Runs, which sweeps some
external potential amplitude(s); potential values set here are ignored for externals
whose potentials amplitudes are so varied.
We'll be varying potential on external 1, with external 2 grounded. So let's just set
all the amplitudes to zero. The fastest way to do this is to choose to enter DC
potentials only, because then only the amplitudes U must be entered (the others
default to zero)
The DC Method is the method used for determining when tunneling events occur, in
circuits with nly DC potentials. The reduced method, in which tunneling is made to
occur every 1/(sum of tunneling rates through all junctions), is not recommended for
circuits with Ohmic resistors.
39
The current settings are often displayed next to the menu item (This is true of all
menus).
The timer is now set to determine when to end each simulation by counting number
of tunneling events. Change the timer mode to "time" instead:
Note how the current mode description in parentheses changed in the menu.
Change the degree of time discretization:
This upper limit ensures that the charge transfer due to Nyquist noise in any one
time step is small.
The time step we should use to keep the total charge dq transferred is actually much
smaller. In general it's a good idea to keep
dq << e
40
Say, dq Η 0.03. Then if the bias potential U(1) Η 1, the current will be U(1)/Rload
Η 1/3 = 0.3. So dt = dq/I = 0.1.
Then we need to choose circuit points to follow:
41
This will give us the average voltage across the tunnel junction, since external 2 is
grounded.
42
Entering the nodes in this order sets the current direction to be from node 3 to node 2,
so that currents are positive for positive U(1).
The beginning of each run is marked by a dot on the screen:
To view the results:
43
This is a table of averages that have been calculated.
44
The standard error of the mean calculated for a time-average is a measure of the
correctness of the calculated average. (You can also view the standard deviation,
which is a measure of the dispersion of time-averages-over-single-timer-periods for
the run. So, for example, if each run had lasted for one period only, the standard
deviations would all be zero.)
CHAPTER 4
RESULTS AND DISCUSSION
4.1 Problem of Making More Powerful Chips [38]
Intel co-founder Gordon Moore predicted that the number of transistors on a
chip will approximately double every 18 to 24 months. This observation refers
to what is known as Moore’s Law. This law has given chip designers greater
incentives to incorporate new features on silicon.
The chief problem facing designers comes down to size. Moore's Law works
largely through shrinking transistors, the circuits that carry electrical signals. By
shrinking transistors, designers can squeeze more transistors into a chip.
However, more transistors mean more electricity and heat compressed into an
even smaller space. Furthermore, smaller chips increase performance but also
compound the problem of complexity.
To solve this problem, the single-electron tunneling transistor - a device that
exploits the quantum effect of tunneling to control and measure the movement of
single electrons was devised. Experiments have shown that charge does not flow
continuously in these devices but rather in a quantized way.
46
Figure 4.1: A single-electron transistor diagram
The single-electron tunneling (SET) transistor consists of a gate electrode that
electrostaticaly influences electrons traveling between the source and drain
electrodes. The electrons in the SET transistor need to cross two tunnel junctions
that form an isolated conducting electrode called the island. Electrons passing
through the island charge and discharge it, and the relative energies of systems
containing 0 or 1 extra electrons depend on the gate voltage. At a low sourcedrain
voltage, a current will only flow through the SET transistor if these two charge
configurations have the same energy
4.2 SET Transistor Function [38]
The key point is that charge passes through the island in quantized units. For an
electron to hop onto the island, its energy must equal the Coulomb energy e2/2C.
When both the gate and bias voltages are zero, electrons do not have enough energy
to enter the island and current does not flow. As the bias voltage between the source
and drain is increased, an electron can pass through the island when the energy in
the system reaches the Coulomb energy. This effect is known as the Coulomb
47
blockade, and the critical voltage needed to transfer an electron onto the island,
equal to e/C, is called the Coulomb gap voltage.
4.3 What is the “island”?
Figure 4.2: (a) When a capacitor is charged through a resistor, the charge on the
capacitor is proportional to the applied voltage and shows no sign of quantization.
(b) When a tunnel junction replaces the resistor, a conducting island is formed
between the junction and the capacitor plate. In this case the average charge on the
island increases in steps as the voltage is increased (c). The steps are sharper for
more resistive barriers and at lower temperatures.
48
Figure 4.3: I-(Va )-characteristic for two different gate voltages. Solid line VG=
e/2CG, dashed line VG =0
The most important property of the single-electron transistor is that the threshold
voltage, as well as the source-drain current in its vicinity, is a periodic function of
the gate voltage, with the period given by
∆Qe = e, ∆U= e/C0 = const.
The effect of the gate voltage is equivalent to the injection of charge Qe = C0U into
the island and thus changes the balance of the charges at tunnel barrier capacitances
C1 and C2, which determines the Coulomb blockade threshold Vt. In the orthodox
theory, the dependence Vt (U) is piece-linear and periodic.
49
Figure 4.4: IV curve of Single electron transistor
At a certain threshold voltage Vt the Coulomb blockade is overcome, and at
much higher voltages the dc IV curve gradually approaches one of the offset linear
asymptotes:
I -> (V +sin(V)´e/2C∑)/(R1+R2). On its way, the IV curve exhibits quasi-periodic
oscillations of its slope, closely related in nature to the Coulomb staircase in the
single-electron box, and expressed especially strongly in the case of a strong
difference between R1 and R2.
Source-drain dc IV curves of a symmetric transistor for several values of the Qe,
i.e. of the gate voltage
4.4 Coulomb blockade [39]
In physics, a Coulomb blockade is the increased resistance at small bias voltages
of an electronic device comprising at least one low-capacitance tunnel junction.
A tunnel junction is, in its simplest form, a thin insulating barrier between
two conducting electrodes. If the electrodes are superconducting, Cooper pairs with
a charge of two elementary charges carry the current. In the case that the electrodes
50
are normal conducting, i.e. neither superconducting nor semiconducting, electrons
with a charge of one elementary charge carry the current. The following reasoning is
for the case of tunnel junctions with an insulating barrier between two
normalconducting electrodes (NIN junctions).
According to the laws of classical electrodynamics, no current can flow
through an insulating barrier. According to the laws of quantum mechanics, however,
there is a probability for an electron on one side of the barrier to reach the other side.
When a bias voltage is applied, this means that there will be a current flow. In firstorder approximation, that is, neglecting additional effects, the tunnelling current will
be proportional to the bias voltage. In electrical terms, the tunnel junction behaves as
a resistor with a constant resistance, also known as an ohmic resistor. The resistance
depends exponentially on the barrier thickness. Typical barrier thicknesses are on
the order of one to several nanometers.
An arrangement of two conductors with an insulating layer in between not
only has a resistance, but also a finite capacitance. The insulator is also called
dielectric in this context, the tunnel junction behaves as a capacitor.
Due to the discreteness of electrical charge, current flow through a tunnel junction is
a series of events in which exactly one electron passes (tunnels) through the tunnel
barrier (we neglect events in which two electrons tunnel simultaneously). The tunnel
junction capacitor is charged with one elementary charge by the tunnelling electron,
causing a voltage buildup U = e / C, where e is the elementary charge of 1.6×1019 coulomb and C the capacitance of the junction. If the capacitance is very small,
the voltage buildup can be large enough to prevent another electron from tunnelling.
The electrical current is then suppressed at low bias voltages and the resistance of
the device is no longer constant. The increase of the differential resistance around
zero bias is called the Coulomb blockade.
In order for the Coulomb blockade to be observable, the temperature has to
be low enough so that the characteristic charging energy (the energy that is required
to charge the junction with one elementary charge) is larger than the thermal energy
of the charge carriers. For capacitances below 1 femtofarad (10-15 farad), this
51
implies that the temperature has to be below about 1 kelvin. This temperature range
is routinely reached for example by dilution refrigerators.
4.5 Single electron transistor with niobium leads and aluminium island
To make a tunnel junction in plate condenser geometry with a capacitance
1 femtofarad, using an oxide layer of electric permeability 10 and thickness one
nanometer, one has to create electrodes with dimensions of approximately 100 by
100 nanometers. This range of dimensions is routinely reached for example by
electron beam lithography and appropriate pattern transfer technologies, like the
Niemeyer-Dolan technique, also known as shadow evaporation technology.
Another problem for the observation of the Coulomb blockade is the relatively large
capacitance of the leads that connect the tunnel junction to the measurement
electronics.
52
4.6 Junction circuit simulation results
Figure 4.5: Tunnel junction circuit
Tunnel junction is a basic element of SET circuit and consists of 2 metallic
substances that are separated with thin insulator between them. Capacitance is
formed because of the separation of 2 metallic substances, while Resistance is
formed because there is a possibility of electron movement from one side of metallic
to the other side of metallic. The major difference between tunnel junctions with
other two of SET circuits is the neighboring effect non-existence.
The IV result of tunnel junction to be discussed will consider different
operating temperature value, junction capacitance, resistance, source-drain voltage
and gate voltage.
Here is the list of default parameter values that are used for the simulation.
Temperature: 0 K
Junction capacitance: 1 Farad
Resistance: 20 Ohm
Source-drain voltage Vds: Variable
Source-drain current Ids: Variable
Voltage gate Vg : 0 V
53
4.6.1 IV curve of Junction circuit with default value
I-V curve of Junction circuit
0.20
0.18
0.16
0.14
0.12
I
0.10
0.08
0.06
0.04
0.02
0.00
0.00
0.10
0.20
0.30
0.40
0.50
-0.02
V
Figure 4.6 IV curve of Junction circuit with default values
Discussion: From Figure 3.2, the Coulomb blockade happens at Vsd=0.50 mV and
the value of current reverse until the voltage reaches Vsd=0.28 mV, where after this
value Isd increases linearly with the increment of Vsd. The reversal of the Vsd
value is due to the single capacitance effect that discharge, resulting voltage
decrement. It means that within this range, the decrement of Vsd will affect the
increment of Isd value.
0.60
54
4.6.2 IV curve of Junction circuit with different Temperature value
I-V curve of Junction circuit with different Temperature value
0.20
0.18
0.16
0.14
0.12
I (e/RC)
0.10
0.08
0.06
0.04
T=0.04
0.02
T=0.02
-0.10
0.00
0.00
0.10
T=0.01
0.20
0.30
T=0.001
0.40
T=0
0.50
-0.02
V (e/C)
Figure 4.7: IV curve of Junction circuit with different Temperature value
Discussion: From Figure 3.3, it shows that by increasing the operating temperature
of Junction circuit, it affects the shape of the IV curve and also at the same time
decrease the value of Coulomb blockade. The maximum operating temperature
allowable in Moses is 0.04 K and we can see from the graph that the shape of IV
curve is almost linear. And at this temperature value, Coulomb blockade is almost
non-existence which means that the current increase whenever there is source-drain
voltage. Theoretically, by increasing the value of operating temperature in Junction
circuit, it also provides energy to the electron at the source to move towards the
drain. That explains why the Coulomb blockade decreases when we increase the
temperature. Until at certain level, where in our case is T=0.04 K, Coulomb
blockade does not exist which means number of electrons that cross from source to
drain increases by increasing the source-drain voltage.
4.6.3 IV curve of Junction circuit with different Junction Capacitance value
0.60
55
I-V curve of Junction circuit with different capacitance value
0.20
C=50 C=10
C=100
C=5C=4
C=3
C=2
C=1
C=0.5
C=500
0.15
I (e/RC)
0.10
0.05
0.00
0.00
0.20
0.40
0.60
0.80
1.00
-0.05
V (e/C)
Figure 4.8: IV curve of Junction circuit with different Junction capacitance value
Discussion: To discuss about the effect of Junction capacitance, we have to base our
discussion by comparing the graph with different capacitance value with the one that
has the default value, which in our case is 1 Farad. On the right side of default IV
curve, is IV curve with Capacitance= 0.5 Farad. This IV curve has Coulomb
blockade at Vsd = 1.00 mV, which is double than the default IV curve, 0.50 mV. So
we can conclude that by decreasing the capacitance value, it has a reverse effect on
Coulomb blockade. Meanwhile on the leftward of default IV curve, there a few IV
curve with higher Capacitance value. As expected, by increasing the capacitance
value, the Coulomb blockade drops and at the same time change the shape of IV
curve from a “hook” shape to linear. The interesting part is after Capacitance is 50
Farad, by increasing more on the capacitance does not do much changes on IV curve,
which has already become linear. Theoretically, by increasing capacitance it
increases the storage of electrons in the circuit, thus increase the probability of
electron crosses from source to drain. This certainly decreases the Coulomb
blockade until at one point (C=50 F), it totally eliminate it. After this capacitance
1.20
56
value, the IV curve has become linear which means the increment of Vsd result the
increment of Isd.
I-V curve Junction circuit with different capacitance value
0.20
C=0.7
C=0.8
C=0.9
C=1.0
C=0.
0.16
C=0.4
C=0.5
C=0.
0.18
C=0.2
0.14
I (e/RC)
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.00
0.50
1.00
1.50
2.00
2.50
-0.02
V (e/C)
Figure 4.9: IV curve of Junction circuit with different Junction capacitance
value
Let’s move on smaller value of Capacitance, and base our discussion on default
capacitance value which is 1 Farad. It clearly shows that by decreasing Capacitance
value result the increment of Coulomb blockade. As mentioned earlier, by
decreasing the capacitance will decrease the probability of electrons to cross from
source to drain, thus increasing the Coulomb blockade.
3.00
57
4.6.4 IV curve of Junction circuit with different Resistance value
I-V curve of Junction circuit with diffferent Resistance value
0.40
0.35
0.30
I (e/RC)
0.25
0.20
0.15
0.10
0.05
R=50
0.00
0.00
R=20
R=10
0.10
0.20
0.30
0.40
0.50
0.60
-0.05
V (e/C)
Figure 4.10: IV curve of Junction circuit with different Resistance value
Discussion: For this topic, we change the value of Resistance and maintain the
capacitance value at 2 Farad. From the graph, we can see that by increasing or
decreasing the value of resistance, give no effect to the Coulomb blockade where the
value still maintains at 0.25 mV. The only thing that is affected is the shape of IV
curve where by increasing the resistance results in sharpening the “hook”, while
decreasing the resistance has the reverse effect. Theoretically, the ohmic resistance
value has no effect on Coulomb blockade because it does not increase the
probability of electron movement from source to drain. Thus, even though high
resistance means electron movement is more rigid, but it still maintain a specific
point where electron start to move from source to drain. To explain about the shape
changes on the “hook”, one needs to understand clearly the fundamental of
electronics. Imagine high resistance as the wire which has narrower width, while for
lower resistance, wire that has wider width. At higher resistance, electrons move
0.70
58
more slowly, thus result in slowing discharge of capacitance and make the “hook”
sharper, while in lower resistance, electrons move faster and result the discharge
process faster, and make the “hook” less sharp.
I-V curve of Junction circuit with different Resistance value
4.00
R=0.1
R=0.2
3.50
R=0.3
3.00
I (e/RC)
2.50
2.00
1.50
1.00
0.50
0.00
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
V (e/C)
Figure 4.11: IV curve of Junction circuit with different Resistance value
Now we change the value of capacitance to 500 Farad and observe that IV curve has
become linear and as expected the Coulomb blockade is zero. Similar with previous
result, changes on Resistance does not give any effect on IV curve.
4.00
59
I-V curve of Junction circuit with different Resistance value
0.60
R=5
0.50
0.40
R=10
I (e/RC)
0.30
R=15
0.20
R=20
R=25
0.10
R=50
0.00
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
-0.10
V (e/C)
Figure 4.12: IV curve of Junction circuit with different Resistance value
The smaller value of capacitance is then tested, C= 0.5 Farad, and IV curve for
different resistance values are simulated. It is then clearly shows that the similar
result occur where different resistance value has no effect on Coulomb blockade.
1.60
60
4.6.5 Spectral Densities of Island Potentials
Spectral Densities of Island Potentials
8
7
6
S(f)
5
4
3
2
1
0
0
0.01
0.02
0.03
0.04
0.05
0.06
Frequency (1/RC)
Figure 4.13: Spectral Densities of Island Potentials for Junction circuit
Discussion: From Figure 3.5, the maximum value for Spectral Densities happens at
Frequency value of 0.015 Hz. As the frequency increases after this value, spectral
densities decrease. The maximum value of Spectral densities significantly
overpasses the maximum value of SET and Array circuit as it does not receive any
neighboring effect from other Tunnel junction. (Refer to the last page of Result and
Discussion chapter for Spectral densities comparison between Junction, SET and
Array circuit).
0.07
61
4.7 SET circuit simulation result
Figure 4.14: SET circuit
SET circuit consists of 2 tunnel junctions and a gate electrode. The movement of
electron from source to drain is very much dependant on Voltage gate (Vg) and
Voltage source to drain (Vsd). This movement of electron from source to drain is
what has formed current source to drain (Isd). Not only the Isd is dependant on Vsd
and Vg, but it is also dependant on other external factors like operating temperature
and junction capacitance, which can be observed from the simulation result.
The IV result of tunnel junction to be discussed will consider different operating
temperature value, junction capacitance, resistance, source-drain voltage and gate
voltage.
Here is the list of default parameter values that are used for the simulation.
Temperature: 0 K
Junction capacitance 1-3 (C1): 1 Farad
Junction capacitance 2-3 (C2): 1 Farad
Resistance: Non- existense
Source-drain voltage Vds: Variable
Source-drain current Ids: Variable
Voltage gate Vg : 0 V
62
4.7.1 IV curve of SET circuit with default value
IV curve of SET circuit w ith default value
0.35
0.30
0.25
I (e/RC)
0.20
0.15
0.10
0.05
0.00
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
-0.05
V (e/C)
Figure 4.15: IV curve of SET circuit with default value
Discussion:
Given all the default parameters like operating temperature= 0 Kelvin,
Capacitance1 and 2 = 1 Farad, we can see that Coulomb blockade for SET circuit is
at 0.25 V. Starting from this value, the junction current (I) increase with the
increment of junction potential (V).
63
4.7.2 IV curve of SET circuit with different Temperature value
IV curve of SET circuit w ith differrent T value
0.06
T=10 K
0.05
T=3 K
0.04
T=0 K
I
0.03
0.02
0.01
0.00
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
-0.01
V
Figure 4.16: IV curve of SET circuit with different set of Temperatures
Discussion: With the same value of background charge Q0(i)= 0, and changes of
operating temperatures, the above behavior of IV curve is observed. This clearly
explains the effect of slight increment of temperature on the SET circuit. The higher
operating temperature is on the SET, the lower Coulomb blockade is. For example
for T= 3 K, the Coulomb blockade for the circuit is 0 mV which means that with any
increment of Vds will effect the increase of Ids. This is different when the operating
temperature is 0 K, where Coulomb blockade is at 0.25 V. The explanation of this
behavior is by adding temperature to SET circuit increase the energy of electrons,
thus resulting the tunneling events to occur in lower Vds. Even though the different
is only 3 K but the impact is quite significant. From this simulation we can also see
that for T=10 K, it gives similar result as T=3 K but it comes without a solid line.
This is just a limitation of MOSES where operating temperature that is more that 3
K is not supported.
64
4.7.3 IV curve of SET circuit with different Junction Capacitance value
IV curve of SET circuit w ith variable C2
0.60
C1=1
C2=50
0.50
C1=1
C2=5
0.40
C1=1
C2=1
I (e/RC)
0.30
0.20
0.10
C1=1
C2=0.0
C1=1
C2=0.1
0.00
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
-0.10
V (e/C)
Figure 4.17: IV curve of SET circuit with different set of junction
capacitance (C2 variable, C1 fixed)
Discussion: There are two junction capacitances that involve in SET circuit. (refer
to Figure 4.14: SET circuit) above. We refer C1 as junction capacitance between
node 1 and 2 while C2 is junction capacitance between node 2 and 3. For the first
condition, we vary the value of C2 while fixing the value of C1. As shown in the
Figure 4.17 above, we can make conclusion that as C2 increases, the value of
Coulomb blockade decreases. This is obvious especially when C2=50 Farad, where
the IV curve become a straight line, and has zero Coulomb blockade, which means
there is immediate occurrence of Ids with the increment of Vds. For the second
curve that is C2=5 Farad, the Coulomb blockade exist at value around 0.02 V and
IV curve that is formed has lower rate until V=0.15 V, where after this value the rate
is similar with C2= 50 Farad. The default IV curve in this case is C2= 1 Farad,
where in this case Coulomb blockade is around 0.25 V. The simulation also takes
place for smaller C2 where we consider two values for this area, 0.1 Farad and 0.01
Farad. For C2=0.1 Farad, we can see that the IV curve change its shape to “hook” as
65
similar to IV curve of Junction circuit. Similar thing occur for C2= 0.01 Farad but
the IV curve has lower Coulomb blockade value. The reason of this phenomenon is
due to smaller capacitance effect at node 2-3 (C2) than in node 1-2 (C1) and this
creates almost similar condition with Junction circuit, as discussed earlier.
IV curve of SET circuit w ith variable C1
0.60
C1=100
C2=1
C1=50
C2=1
0.50
C1=5
C2=1
0.40
C1=1
C2=1
0.30
I (e/RC)
C1=0.1
C2=1
0.20
C1=0.01
C2=1
0.10
0.00
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
-0.10
V (e/C)
Figure 4.18: IV curve of SET circuit with different set of junction
capacitance (C2 fixed, C1 variable)
Discussion: Our discussion continues with varying the value of C1 while fixing C2.
Similar with previous result, IV curve of SET circuit becomes linear when C1 is at
50 Farad and greater, and at the same time Coulomb blockade is zero. We then
reduce the value of C1 to 5 Farad and observe that Coulomb blockade is around 0.08
Farad. Reducing C1 to 0.1 and 0.01 Farad has interesting result where it shows that
IV curve become linear, unlike the previous simulation, where the IV curve turn to
“hook” shape. As for C1=0.1 Farad, there is even no Coulomb blockade while for
C1= 0.01 Farad, Coulomb blockade is at 0.05 V. Even both of IV curve for C1= 0.1
and 0.01 Farad is linear, but the rate of change is much lower than C1= 50 and 100
Farad. The reason why Coulomb blockade is zero at C= 50 and 100 Farad is similar
with other previous simulation, where increment of capacitance means higher
66
probability of tunneling event. But as why Coulomb blockade is also decrease when
C1 is lower than C2 is merely because the total capacitance value in the SET circuit.
IV curve of SET circuit w ith sim iliar C1 and C2
0.60
C1=50
C2=50
0.50
C1=5
C2=5
0.40
C1=1
C2=1
I (e/RC)
0.30
0.20
C1=0.1
C2=0.1
0.10
C1=0.01
C2=0.01
0.00
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
-0.10
V (e/C)
Figure 4.19: IV curve of SET circuit with different set of junction
capacitance (C2=C1)
Discussion: This time we make sure that the value of both C1 and C2 are similar.
As expected for C1=C2=50 Farad, a linear IV curve is shown, while Coulomb
blockade is zero. This is because the high capacitance of junction results in higher
probability of tunneling events. For C1=C2= 5 Farad, Coulomb blockade is at 0.05
Farad and at the same time IV curve is linear. As for lower capacitance value at 0.1
and 0.01 Farad, Coulomb blockade exist both at 0.25 V and rate of change is higher
for 0.1 than 0.01. This is merely because the similar value of C1 and C2 form the
balance total junction capacitance of SET circuit, thus maintaining the value of
Coulomb blockade point.
67
4.7.4 Spectral Densities of Island Potential
Spectral Densities of Island Potentials
1.2
1
S(f)
0.8
0.6
0.4
0.2
0
0
0.01
0.02
0.03
0.04
0.05
0.06
frequency (1/RC)
Figure 4.20: Spectral Densities of Island Potential for SET circuit
Discussion: From Figure 3.10, the maximum spectral densities of island potential
for SET circuit are at Frequency value 0 Hz. This value decreases as the frequency
value increases. The maximum of Spectral densities value is significantly lower than
what is in Array circuit. (Refer to the last page of Result and Discussion chapter for
Spectral densities comparison between Junction, SET and Array circuit).
0.07
68
4.8 Array circuit simulation result
Figure 4.21: Array circuit diagram
Basically Array circuit consists of more than one tunnel junction and in this case is
21 tunnel junctions. By arranging more than one tunnel junction, we can observe the
neighbouring effect towards the IV curve, energy and spectrum densities.
The IV result of tunnel junction to be discussed will consider different operating
temperature value, junction capacitance, resistance, source-drain voltage and gate
voltage.
Here is the list of default parameter values that are used for the simulation.
Temperature: 0 K
20 Junction capacitances
Junction capacitance 1-3: 1 Farad
Junction capacitance 22-2: 1 Farad
Junction capacitance 3-4 : 1 Farad
Junction capacitance 4-5: 1 Farad
Junction capacitance 5-6: 1 Farad
Junction capacitance 6-7: 1 Farad
Junction capacitance 8-9: 1 Farad
Junction capacitance 9-10: 1 Farad
69
Junction capacitance 10-11: 1 Farad
Junction capacitance 11-12: 1 Farad
Junction capacitance 12-13: 1 Farad
Junction capacitance 13-14: 1 Farad
Junction capacitance 14-15: 1 Farad
Junction capacitance 15-16: 1 Farad
Junction capacitance 16-17: 1 Farad
Junction capacitance 17-18: 1 Farad
Junction capacitance 18-19: 1 Farad
Junction capacitance 19-20: 1 Farad
Junction capacitance 20-21: 1 Farad
Junction capacitance 21-22: 1 Farad
Resistance: Non- existense
Source-drain voltage Vds: Variable
Source-drain current Ids: Variable
Voltage gate Vg : 0 V
70
4.8.1 IV curve of Array circuit with default value
IV curve of Array circuit w ith default value
0.20
C= 1
0.18
0.16
0.14
0.12
I (e/RC)
0.10
0.08
0.06
0.04
0.02
0.00
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
-0.02
V (e/C)
Figure 4.22: IV curve of Array circuit with default value
Discussion: Given all the default parameters like operating temperature= 0 Kelvin,
Capacitance1 until 22 = 1 Farad, we can see that Coulomb blockade for Array
circuit is at 0.05 V. Starting from this value, the junction current (I) increase
exponentially with the increment of junction potential (V). Observe that the IV curve
of Array circuit is different from the previous two simulation result of Junction and
SET circuit, due to the large neighboring effect of the 20 capacitances.
71
4.8.2 IV curve of Array circuit with different temperature value
IV curve of array circuit w ith different tem perature value
0.50
T= 3 K
0.40
0.30
I (e/RC)
T= 0.1
0.20
T= 0 K
0.10
0.00
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
-0.10
V (e/C)
Figure 4.23: IV curve of Array circuit with different Temperature value
Discussion: We then move on to simulate Array circuit with different operating
temperature. As previous simulation result shown with other SET circuit, a slight
changes on temperature bring significant impact to the Array circuit. Comparing
with default IV curve that uses T= 0K, a slight increment to 0.1 result in Coulomb
blockade value to zero, but with similar rate of change on IV curve. However an
increment to 3 K result in higher rate of IV curve with similar zero Coulomb
blockade. We can also see that for T=3K, MOSES has started to scatter its plotting,
but still an overall straight line is formed. This is merely a limitation of this program
and the problem gets worse for value T is more than 3 K. As a conclusion, a slight
increment on temperature brings energy to the electron, thus cause higher
probability of tunneling event.
72
4.8.3 IV curve of Array circuit with different junction capacitance value
IV curve of Array circuit w ith variable Capacitance
0.50
C= 100
C= 10
0.40
C= 3
I (e/RC)
0.30
0.20
C=1
0.10
C= 0.1
0.00
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
-0.10
V (e/C)
Figure 4.24: IV curve of Array circuit with variable Capacitance
Discussion: From the observation of the Figure above, let’s start our discussion with
the default IV curve which has 20 Junction capacitances value= 1 Farad. We then
increase this value to 3 Farad, and can see that the Coulomb blockade is now 0.08
Farad instead of 0.10 Farad. Another increment of Capacitance to 10 Farad resulting
Coulomb blockade to 0.02 Farad and eventually when C= 100 Farad, the Coulomb
blockade is zero. We can also see that there is slight increment on rate of change of
the IV curve as we increase the value of capacitance. As we reduce the value of
capacitance to 0.1 Farad, as expected, increase the value of Coulomb blockade and
decrease the rate of change of IV curve.
73
IV curve of Array circuit w ith variable Capacitance value
0.50
C increment
C decrement
0.40
I (e/RC)
0.30
0.20
0.10
0.00
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
-0.10
V (e/C)
Figure 4.25: IV curve of Array circuit with variable Capacitance
value (increment and decrement order)
Since Array circuit comprises of 20 Junction capacitances, there a lot of possibilities
in terms of capacitance neighboring effect. One simulation that is interesting to see
is whether the value arrangement of these 20 capacitances will affect its IV curve.
Thus, for the first simulation, we arrange 20 capacitance values with the increment
order while the other is in decrement order. The result shows that for the IV curve
with increment order, there is no Coulomb blockade and the curve is a straight line.
While for IV curve with capacitance arranged in decrement order, has Coulomb
blockade at 0.02 V, but still maintains a straight line for its IV curve.
74
4.8.4 IV curve of Array circuit with different conductance value
IV curve of Array circuit w ith different conductance value
20.00
G= 100
18.00
16.00
14.00
12.00
I (e/RC)
10.00
8.00
6.00
4.00
G= 10
2.00
G= 1
0.00
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
-2.00
V (e/C)
Figure 4.26: IV curve of Array circuit with different conductance value
Discussion: We then simulate the Array circuit on different conductance value. The
default value of the conductance is 1 MHO. We can see that as we increase the value
of the conductance, we also increase the rate of change of IV. This is because an
increment of conductance results in increment of tunneling events, thus more
electrons pass through the tunnel junction and are represented by an increment of Ids.
75
4.8.5 Spectral Densities of Island Potentials
Spectral Densities of Island Potentials
1.2
1
S(f)
0.8
0.6
0.4
0.2
0
0
0.01
0.02
0.03
0.04
0.05
0.06
Frequency (1/RC)
Figure 4.27: Spectral Densities of Island Potentials for Array circuit
Discussion: From Figure 3.12, the highest value of spectral densities for Array
circuit happens at Frequency value 0.009 Hz. This value decreases exponentially
after this point with the increment of Frequency.
0.07
76
4.8.6 Energy of a 21-junction array
Energy of 21-junction array
0.9
0.8
In simulating the BPSK transmission schemes under different
0.7
E (e2/C)
0.6
0.5
0.4
0.3
0.2
0.1
0
0
5
10
15
20
circuit node number, i
Figure 4.28: Energy of 21-junction array circuit
Discussion: From Figure 3.13, Energy is at the maximum from node number 10
until 15 of 21-junction Array circuit. This effect is because of the energy build-up
towards the center of the array circuit. (Refer to the last page of Result and
Discussion chapter for Spectral densities comparison between Junction, SET and
Array circuit).
25
77
4.8.7 Energies of a 21-junction array with different Vds values
Energies of a 21-junction array with one extra electron on node i
3
Vds= 3mV
2.5
Vds= 2.5mV
2
E (e2/C)
Vds= 2mV
Vds= 1.5mV
1.5
Vds= 1mV
1
Vds= 0.5mV
0.5
Vds= 0mV
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
circuit node number, i
Figure 4.29: Energies of a 21-junction array with one extra electron on node i
Discussion: This figure clearly shows that by increasing the Vds value, the energy
at the region near the source is also increase. But towards the drain, it gradually
decreae and finally at the point of 22, the value is similar for all values for Vds
78
4.9 Comparison of Spectral Densities between Junction, SET and Array circuit.
Spectral Densities of Island Potentials
8
7
6
Junction circuit
S(f)
5
4
3
Array circuit
2
SET circuit
1
0
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
frequency (1/RC)
Figure 4.30: Comparison of Spectral Densities of Island potentials for Junction, SET
and Array circuit.
Discussion: As the Figure display, it clearly shows that Spectral densities of
Junction circuit are the highest. This is because there is no neighboring effect
received, since it is the only capacitance source of the circuit.
CHAPTER 5
CONCLUSIONS AND FURTHER WORK
5.1 Positive Conclusion
The project went rather well. This project has outlined several properties of
SET using MOSES. It shows that factor like number of tunnel junction, capacitance
value and temperature give signifanct impact toward the IV curve, Energy and
Specral Densities of the SET circuit.
5.2 Further improvement for this Project
Satisfactory results were obtained.
However, there is still room for
improvements. Given more time, I would like simulate the SET with more user
friendly software like SIMON which support graphical interface, or at least get the
KMOSES which is graphical version of MOSES to work. Thus it will easier to plot
number of SET circuit like inverter, oscillator and flip-flop and compare it with the
circuit that uses CMOS.
5.3 Future research
Given enough time to further this research, I would like to simulate other SET
circuit with different types of parameters and settings. This can surely enhance my
80
knowledge with the behavior of SET circuit and prepare me to continue with the
fabrication process later.
5.4 A Final Note
This project has been interesting and challenging for a newcomer in the
nanotechnology field like me. I have achieved all the objectives stated but most
importantly, I have learnt more on single electron transistor and MOSES simulation.
This project is a stepping stone for me to embark in the R&D for the
nanotechnologies.
81
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