vii
TABLE OF CONTENT
CHAPTER
1
2
TITLE
PAGE
TITLE
i
DECLARATION
ii
DEDICATION
iii
ACKNOWLEDGEMENT
iv
ABSTRACT
v
ABSTRAK
vi
TABLE OF CONTENT
vii
LIST OF TABLES
x
LIST OF FIGURES
xi
LIST OF ABBREVIATION
xiv
LIST OF APPENDICES
xv
INTRODUCTION
1
1.1 Introduction
1
1.2 Objectives
4
1.3 Scope of Project
4
1.4 Project Plan
5
1.5 Organization of the Report
6
LITERATURE REVIEW
7
2.1 Introduction
7
viii
2.2 Planar MOSFET
2.2.1 Works on planar MOSFET
2.3 Vertical MOSFET
2.3.1 Vertical MOSFETs based on selective
8
9
13
15
epitaxy
2.3.2 Vertical MOSFETs with etched sidewalls
17
2.3.3 Works on vertical MOSFET
18
2.4 Characteristics of an NMOS transistor
22
2.5 Short channel effects
23
2.6 MOS device physics in short-channel regime
23
2.7 Threshold voltage
26
2.7.1 Threshold reduction
3
27
2.8 Leakage current
28
2.9 Subthreshold characteristic
30
2.10 VT roll-off
32
2.11 Summary
33
METHODOLOGY
34
3.1 Process simulation
34
3.2 Process development
36
3.2.1 Work area
36
3.2.2 Adding silicon base region
37
3.2.3 Creating gate oxide
39
3.2.4 Adding contacts for source/drain
41
3.2.5 Adding substrate contact
42
3.2.6 Polysilicon gate formation
43
3.2.7 Source/drain doping
45
3.2.8 Creating mesh
49
3.2.9 Final device
51
3.3 Device simulation
54
3.3.1 Output characteristic
55
3.3.3 Transfer characteristic
56
ix
4
3.4 Summary
56
EXPERIMENTAL RESULTS AND ANALYSIS
57
4.1 Results
57
4.1.1 Output characteristic
57
4.1.2 Transfer characteristic
59
4.1.3 Threshold voltage
60
4.1.4 Leakage current
61
4.1.5 Subthreshold slope
62
4.1.6 Drain saturation slope
63
4.2 Analysis
4.2.1 Varied gate oxide thickness
64
4.2.1.1 Threshold voltage
64
4.2.1.2 Subthreshold slope
65
4.2.1.3 Leakage current
66
4.2.1.4 Conclusion
67
4.2.2 Varied body doping concentration
5
64
68
4.2.2.1 Threshold voltage
68
4.2.2.2 Subthreshold slope
69
4.2.2.3 Leakage current
70
4.2.2.4 Conclusion
71
4.3 Summary
72
CONCLUSION AND FUTURE WORK
73
5.1 Conclusion
73
5.2 Suggestion for Future Works
74
REFERENCES
75
APPENDICES
78
x
LIST OF TABLES
TABLE NO
3.1
TITLE
Summary of NMOS process flow
PAGE
35
xi
LIST OF FIGURES
FIGURE NO
TITLE
PAGE
1.1
Moore’s Law on increasing performance
3
1.2
Moore’s Law on decreasing cost
3
2.1
Cross section of a planar NMOS.
8
2.2
Simulation structure of the symmetrical MOSFET
9
with design parameters
2.3
Simulation structure for the asymmetric MOSFET
10
2.4
Schematic images of the device-design concepts for
11
the lateral S/D-junction control techniques. (a)
Conventional. (b) Thick offset spacer. (c) Notch,
offset spacer and reverse S/D
2.5
Schematic device cross section in the simulations: (a)
12
the asymmetric Schottky barrier MOSFET (ASB
structure); (b) the conventional Schottky Barrier
MOSFET (CSB structure)
2.6
Vertical MOSFET
13
2.7
Schematic cross section of VFET
15
2.8
Schematic cross section of VOXFET
16
2.9
Cross-section showing the concept of dielectric pocket
17
in a vertical MOSFET
2.10
Schematic cross sections of vertical nMOSFETs (a)
18
with deep drain junction and (b) with shallow drain
junction.
2.11
Structure of bVMOS
19
xii
2.12
Schematic cross section of a surround-gate vertical
21
MOSFET fabricated with the FILOX process
2.13
Transfer characteristic of an NMOS transistor
22
2.14
Drain current family of characteristic of an NMOS
22
transistor
2.15
Depletion region of an NMOS
27
2.16
Sources of current leakage in an n-channel MOSFET
29
2.17
(a) ID-VG curve and (b) inverse ID-VG that shows
31
subthreshold slope, S
3.1
Flow of process simulation
35
3.2
Work area’s depth and length values for (a) planar
36
NMOS and (b) vertical NMOS
3.3
Workspace for planar NMOS
37
3.4
Silicon region for (a) planar NMOS and (b) vertical
38
NMOS
3.5
Base impurity, boron, added to the silicon
39
3.6
SiO2 layer for (a) planar NMOS and (b) vertical
40
NMOS
3.7
Contacts for (a) planar NMOS and (b) vertical NMOS
41-42
3.8
Substrate electrode panel
43
3.9
Polysilicon gate region for (a) planar NMOS and (b)
44
vertical NMOS
3.10
Adding impurities to gate to create highly doped
45
region
3.11
Impurity added to create source for (a) planar NMOS
46
and (b) vertical NMOS
3.12
Impurity specification to create drain for (a) planar
47
NMOS and (b) vertical NMOS
3.13
Net doping for (a) planar NMOS and (b) vertical
48
NMOS
3.14
(a) Mesh parameters and (b) refinement on mesh for
49
planar and vertical NMOS
3.15
Mesh on (a) planar NMOS and (b) vertical NMOS
50
xiii
3.16
Completed planar NMOS
51
3.17
Completed (a) single channel vertical NMOS and (b)
52
full vertical NMOS
3.18
(a) Planar NMOS and (b) vertical NMOS with
53
effective channel length of 100nm
4.1
ID-VDS curve for planar and single channel vertical
58
NMOS
4.2
ID-VGS curve for planar and single channel vertical
59
NMOS
4.3
Threshold voltage for planar and single channel
60
vertical NMOS
4.4
Leakage current for planar and single channel vertical
61
NMOS
4.5
Subthreshold slope for planar and single channel
62
vertical NMOS
4.6
Drain saturation slope for planar and single channel
63
vertical NMOS
4.7
Threshold voltage with varied gate oxide thickness for
65
planar and vertical NMOS
4.8
Subthreshold slope with varied gate oxide thickness
66
for planar and vertical NMOS
4.9
Leakage current with varied gate oxide thickness for
67
planar and vertical NMOS
4.10
Threshold voltage with varied body doping
69
concentration for planar and vertical NMOS
4.11
Subthreshold slope with varied body doping
70
concentration for planar and vertical NMOS
4.12
Leakage current with varied body doping
concentration for planar and vertical NMOS
71
xiv
LIST OF ABBREVIATION
ASB
-
Asymmetric Schottky barrier source/drain MOSFET
BTBT
-
Band-to-band tunneling
bVMOS
-
Vertical MOSFET with internal block layer
CMOS
-
Complementary MOS
CSB
-
Conventional Schottky Barrier MOSFET
DIBL
-
Drain induced barrier lowering
DITM
-
Drain-induced tunneling modulation
DOT
-
Drain on top
DT
-
Direct-tunneling
FILOX
-
Fillet local oxidation
GIDL
-
Gate-induced drain leakage
MOSFET
-
Metal-oxide semiconductor filed effect transistor
NMOS
-
N-channel MOSFET
PECVD
-
Plasma-enhanced chemical vapor deposition
PMOS
-
P-channel MOSFET
SCE
-
Short channel effect
SEG
-
Selective epitaxial growth
SOI
-
Silicon on insulator
SOT
-
Source on top
xv
LIST OF APPENDICES
APPENDIX
TITLE
PAGE
A
Family of ID-VDS curve program
78
B
ID-VGS at VDS=0.1V program
80
C
Extract results from simulation
82