A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR
LOW NOISE AMPLIFIER USING INTEGRATED ACTIVE INDUCTOR
RAFIQ SHARMAN BIN KHAMIS @ ROSLEE
Universiti Teknologi Malaysia
iii
ACKNOWLEDGEMENT
I would like to take the opportunity to thank the Almighty God, Allah, which
with His blessed, I manage to complete this thesis.
In this spirit, it is a pleasure for me to record the many archival and
intellectual debts that I have accumulated while completing this thesis. To put
everyone name on list is an impossible job. However, I would like to name some of
them whom I am deeply indebted.
Firstly, I wish to express my sincere appreciation to my respectful supervisor,
Prof Dr. Abu Khari Bin A’Ain for the advices, encouragement, guidance, critics and
friend that have helped me in completing this projectthesis. Secondly, I would like to
express my appreciation for the support and motivation that have been given to me
by my family, my friends, and not forgotten to my wife…Mrs. Noor Azreen bte
Kasmani, thank you very much for your great support to complete this thesis.
iv
ABSTRACT
Low Noise Amplifier (LNA) is a very important component in a receiver
system. It provides the smallest noise and high gain to decrease the noise of the
subsequent stages and the whole system. As System On Chip (SOC) is very
important nowadays, active inductor is an alternative to the designer to have an
integrated design. Furthermore, active inductor can be tuned to obtain the required
inductance and Q-factor values. Instead of using passive inductor such as spiral and
bonding wire which need bigger die area, active inductor can be employed to save
die area but this comes at the cost of higher current consumption and noise. This
thesis presents the study of active inductor architecture, how active inductor can
combine with LNA and evaluation on LNA performance when active inductor is
added. This will help designers to have better understanding on how to use active
inductor in their design. This research proposes the Commmon Gate LNA
architecture and is designed with 1.2 um CMOS process, operating at 850 MHz. The
voltage gain and noise factor obtained are 24.7 dB and 8.26 dB respectively. Two
active inductors are used as gain control, input and output matching of LNA.
However, the LNA consumes 163.8 mW where 75% percent of power consumption
is contributed by active inductor.
v
ABSTRAK
Penguat Hingar Rendah (LNA) adalah komponen yang amat penting dalam
sistem penerimaan. Ia menyediakan hingar yang paling rendah dan gandaan yang
tinggi untuk merendahkan hingar pada peringkat yang berikutnya dan dalam
keseluruhan sistem. Memandangkan Sistem Atas Cip (SOC) semakin penting pada
akhir-akhir ini, inductor aktif merupakan alternatif kepada pereka untuk mencapai
rekebentuk bersepadu. Lebih-lebih lagi, induktor aktif boleh diubah suai untuk
mendapatkan nilai induktor dan faktor-Q yang diperlukan. Berbanding dengan
induktor pasif seperti pusar dan wayar ikatan yang memerlukan ruang yang besar,
induktor aktif boleh digunakan untuk menjimatkan ruang ital tetapi terpaksa
memerlukan penggunaan arus dan hingar yang tinggi. Tesis ini membentangkan
induktor aktif, bagaimana induktor aktif boleh digabungkan dengan LNA dan
mengkaji LNA apabila induktor aktif digabungkan. Ini dapat membantu pereka untuk
lebih memahami bagaimana hendak menggunakan induktor aktif dalam proses
merekabentuk. Kajian ini menggunakan asas LNA Pintu Sepunya dengan proses1.2
um, beroperasi pada 850 MHz. Gandaan voltan dan faktor hingar diperolehi sebagai
24.7 dB dan 8.26 dB. Dua induktor aktif digunakan sebagai kawalan gandaan,
padanan masukan dan keluaran untuk LNA. LNA ini didapati menggunakan 163.8
mW, di mana 75% daripadanya adalah disumbangkan oleh induktor aktif.
vi
TABLE OF CONTENTS
CHAPTER
1
TITLE
PAGE
DECLARATION
ii
ACKNOWLEDGMENT
iii
ABSTRACT
iv
ABSTRAK
v
TABLE OF CONTENTS
vi
LIST OF TABLES
ix
LIST OF FIGURES
x
LIST OF SYMBOLS
xiii
LIST OF APPENDICES
xv
INTRODUCTION
1
1.1 Introduction
1
1.2 Problem Statement
2
1.3 Objective of The Research
3
1.4 Design Target
3
1.5 Methodology
3
1.6 Scope of Work
4
1.7 Thesis Outline
4
vii
2
ACTIVE INDUCTOR AND LNA ACHITECTURE STUDY
5
2.1 Introduction
5
2.2 Active Inductor
5
2.2.1
Active Inductor Motivation
6
2.2.2
Active Inductor Architecture
7
2.2.2.1
Basic Active Inductor
10
2.2.2.2
Cascode Active Inductor
11
2.2.2.3
Regulated Cascode Active Inductor
12
2.2.2.4
Differential Active Inductor
13
2.3 Low Noise Amplifier
2.3.1
3
LNA Architecture
14
15
2.3.1.1
Common Source Amplifier
15
2.3.1.2
Shut-shunt Feedback Amplifier
17
2.3.1.3
Inductive Source Degeneration Amp
18
2.3.1.4
Common Gate Amplifier
19
2.4 Comparison of LNA Architecture Performance
20
ACTIVE INDUCTOR AND LNA DESIGN
21
3.1 Introduction
21
3.2 Proposed Active Inductor
22
3.2.1
Small Signal Analysis
24
3.2.2
Active Inductor Design
29
3.3 LNA design with Active Inductor
30
viii
4
SIMULATION RESULT
34
4.1 Introduction
34
4.2 Active Inductor Analysis
35
4.2.1
Analysis on Inductance & f0 Tuning
36
4.2.2
Analysis on Q-factor
41
4.2.3
Analysis on Noise
43
4.2.4
Summary of Analysis
44
4.3 LNA with Active Inductor Analysis
5
47
4.3.1
LNA with Active Ls sweep
48
4.3.2
LNA with Sweep Active Ld
51
4.3.3
LNA with Sweep Cd
54
4.4 Final Design – LNA with Active Inductor
57
4.5 LNA Comparison – Active vs Passive/Ideal Inductor
64
4.6 Comparison of LNA design
71
CONCLUSION AND FUTURE WORK
72
5.1 Conclusion
72
5.2 Future Work
75
76
REFERENCES
Appendix A
SPICE Transistor Parameter
79
Appendix B
Active Inductor Inductance Extraction from Impedance
81
Simulation
Appendix C
Proposed LNA and Active Inductor Calculation
83
Appendix D
SPICE file for LNA with Active Inductor
97
ix
LIST OF TABLES
TABLE NO.
TITLE
PAGE
2.1
Common Source Amplifier Performance
16
2.2
Shunt-shunt feedback Amplifier Performance
17
2.3
Inductive Source Degeneration Amplifier Performance
18
2.4
Common Gate Amplifier Performance
19
2.5
Comparison between All Architectures
20
3.1
Summary of proposed active inductor analysis
28
3.2
Active inductor transistors sizes
29
4.1
Active inductor transistor size
35
4.2
Design Variable for Inductance Tuning
36
4.3
Summary of different width on M1, 2, 3 & 4
40
4.4
Summary of different W/L on M11, 12, 13 & 14
42
4.5
W = 222 um summary
46
4.6
Performance summary of LNA with active inductor
62
4.7
Comparison between LNA with active and passive
69
inductor
4.8
LNA design comparison from other research
71
x
LIST OF FIGURES
FIGURE NO.
TITLE
PAGE
2.1
Basic Gyrator-C Topology
7
2.2
Active inductor Model
8
2.3
Circuit of Basic Active Inductor
10
2.4
Circuit of Cascode Active Inductor
11
2.5
Circuit of Regulated Cascode Active Inductor
12
2.6
Circuit of Differential Active Inductor
13
2.7
LNA in a receiver
14
2.8
Common Source Amplifier Circuit
15
2.9
Shunt-shunt feedback amplifier circuit
17
2.10
Inductive Source Degeneration Amplifier Circuit
18
2.11
Common Gate Amplifier Circuit
19
3.1
Proposed active inductor
22
3.2
Small signal analysis
24
3.3
Simplified small signal analysis
25
3.4
A sample waveform of an active inductor
26
3.5
Simplified model of proposed active inductor
27
3.6
Inductive Source Degeneration with Active Inductor
30
3.7
Common Gate with Active Inductor
31
3.8
Architecture for LNA with active inductor
32
4.1
Sweep width of M1, 2, 3 & 4
37
4.2
Sweep Ibias (0.6 mA – 2.5 mA) with W=50 um
38
xi
4.3
Sweep Ibias (0.6 mA – 2.5 mA) with W=500 um
39
4.4
Q-factor improvement
42
4.5
Noise with W = 50 um
43
4.6
Noise with W = 500 um
43
4.7
Inductance result with W = 222 um
45
4.8
Noise performance with W = 222 um
45
4.9
Zin when sweep Active Ls
48
4.10
Zout when sweep ActiveLs
48
4.11
Gain when sweep ActiveLs
49
4.12
PM when sweep ActiveLs
49
4.13
Noise when sweep ActiveLs
50
4.14
Zin when sweep ActiveLd
51
4.15
Zout when sweep ActiveLd
51
4.16
Gain when sweep ActiveLd
52
4.17
PM when sweep ActiveLd
52
4.18
Noise when sweep ActiveLd
53
4.19
Zin when sweep Cd
54
4.20
Zout when sweep Cd
54
4.21
Av when sweep Cd
55
4.22
PM when sweep Cd
55
4.23
Noise when sweep Cd
56
4.24
Final Design (simplified)
57
4.25
Final Design
58
4.26
LNA with Active L (Av)
59
4.27
LNA with Active L (PM)
59
4.28
LNA with Active L (Zin & Zout)
60
4.29
LNA with Active L (NF)
60
4.30
Layout of LNA with active inductor
62
4.31
Simulation setting for LNA with Passive L
64
4.32
Av Comparison
66
4.33
PM Comparison
66
4.34
Zin Comparison
67
4.35
Zout Comparison
67
xii
4.36
NF Comparison
68
xiii
LIST OF SYMBOLS
LNA
-
Low Noise Amplifier
SoC
-
System on Chip
CG
-
Common gate
Q-factor
-
Quality Factor
f0
-
Frequency of operation
NF
-
Noise factor
Zin
-
Input impedance
Zout
-
Output impedance
Av
-
Voltage gain
dB
-
Decibel
W
-
Watt
PM
-
Phase margin
L
-
Inductance
C
-
Capacitance
R
-
Resistance
RL
-
Inductor loss
gm
-
Transconductance output
g
-
Output conductance
W/L
-
Transistor width and length
Active Ls
-
Active inductor at source
Active Ld
-
Active inductor at drain
ro
-
Output resistance
VE
-
Early voltage
xiv
ID
-
Saturation current
gds
-
Output conductance
Cgd
-
Transistor inductance value – gate to drain
Cdb
-
Transistor inductance value – drain to bulk
Cgs
-
Transistor inductance value – gate to source
xv
LIST OF APPENDICES
APPENDIX
TITLE
PAGE
A
SPICE Transistor Parameter
79
B
Active Inductor Inductance Extraction from Impedance
81
Simulation
C
Proposed LNA and Active Inductor Calculation
83
D
SPICE file for LNA with Active Inductor
97
CHAPTER I
INTRODUCTION
1.1
Introduction
System on Chip (SOC) design is becoming more popular nowadays. The idea
to integrate the whole circuits system in a single chip has given a good advantage to
the manufacturer to have smaller integrated circuit (IC) as most of the design is
becoming more complex and integrated. Furthermore, they can reduce manufacturing
cost and save die area.
Active inductor is one of the key elements to achieve smaller die area.
Moreover, its capability to tune the inductance and Q-factor values have increased
the design programmability to achieve better performance of the design. Previously,
passive inductor such as spiral and bonding wire have widely used by designers.
However, their usage have limits the performance as they need bigger die area and
provide fix values of inductance and Q-factor. Even though active inductor gives an
alternative method to provide SOC design, we need to face the drawback of active
inductor as it increases power consumption and introduces higher noise. Therefore,
careful design is very important to make sure the noise can be limited with moderate
power consumption.
2
To study the idea to integrate active inductor with other circuits, Low Noise
Amplifier (LNA) is chosen. LNA is very important in a receiver system which
receives weak signals from an antenna and amplifies the signal to the subsequent
stages. Since the signal at the antenna is comparatively weak, a good gain and Noise
Factor (NF) are necessary. The noise of the whole system is reduced by the gain of
the LNA and the noise of the LNA is injected directly into the received signal. Thus,
the LNA needs both high gain and low noise to ensure good performance of the
receiver is achieved.
To achieve better noise performance, Common-Gate (CG) architecture is
suggested. Its ability to avoid noisy component at the input signal is the main key to
integrate active inductor with LNA[1]. Moreover, as this architecture needs high
inductance value, active inductor is becoming more reliable to use rather than passive
inductor. Since noise performance is important for the LNA, a new technique is
presented to shrink the noise of the active inductor and LNA. Some of the design
issues such as discussion and analysis on how to improve the design performance,
the design trade-off and recommendation are briefly explained in this thesis.
1.2
Problem Statement
Since active inductor is a noisy circuit, a good architecture and careful design
consideration needed to achieve the required performance of LNA. A good
architecture for the LNA is also essential to make sure the active inductor can be
replaced and can work properly as the passive inductor. As active inductor is
tuneable by current, higher power consumption will be one of its drawbacks. Even
though die area can be saved, some other issues need to be studied such as frequency
and inductance tuning capability, noise optimization, impedance matching, narrowband implementation and stability. Thus the problem statement of this research is
what should the LNA architecture be if it were to be integrated with active inductor.
3
1.3
Objective of The Research
The objectives of this research are listed below:
i. To analyze and understand an active inductor.
ii. To study and analyze the performance of a LNA which uses active inductor
iii. To design and analyze performance of Complementary Metal Oxide
Semiconductor (CMOS) Common Gate LNA with On-Chip active inductor.
Design is based on 1.2 um CMOS process.
1.4
Design Target
Design target for this research are:
1.5
a. Input/Output Impedance
Æ 50 Ω
b. Gain (Av)
Æ >10dB
c. Phase Margin (PM)
Æ > 60
d. Noise Factor (NF)
Æ < 8dB
e. Power Consumption
Æ < 100mW
Methodology
The methodology of this research is listed as follows:
i.
Literature survey on CMOS LNA and active inductor architectures and
designs.
ii.
Study the noise impact for the LNA and active inductor circuit.
4
iii.
Design the circuit of active inductor using S-Edit software. The design
consideration and analysis are done.
iv.
Design the circuit of LNA using S-Edit software.
v.
All simulations and study are done using T-Spice and W-Edit software.
vi.
Integrate active inductor with LNA and study the effect of active inductor
to the LNA.
vii. Design the layout of the LNA and Active inductor using L-Edit sofware.
viii. Performance analysis on schematic and layout levels design
1.6
Scope of Work
The scopes of work of this research are as follows:
i. To study active inductor performance based on tuning range, Q-factor and
noise performance.
ii. To study the effect of active inductor to LNA performance
iii. Layout design for active inductor and LNA with performance analysis
1.7 Thesis Organization
Chapter I presents the overview of the project. Chapter II reviews active
inductor and LNA architecture. Chapter 3 proposes an active inductor design and
presents how to integrate it to the LNA. Chapter 4 analyses design the performance
based on gain, phase margin (PM), impedance matching, tuning capability and noise
optimization. Chapter 5 concludes the research and proposes the future work that
could improve the LNA performance, especially on power consumption and noise
optimization.
CHAPTER II
ACTIVE INDUCTOR AND LNA ARCHITECTURE STUDY
2.1
Introduction
This chapter presents some of active inductors and LNA architectures before
the active inductor and LNA architecture are chosen for this research.
2.2
Active Inductor
This sub section discusses on the active inductor motivation and the active
inductor architectures such as basic, cascode, regulated cascode and differential
active inductor.
6
2.2.1 Active Inductor Motivation
The main motivation to implement active inductor is to avoid using passive
inductor such as spiral and bonding wire inductor in the design. They require large
die area and have a fixed and low Q-factor value since CMOS provides a low
resistive substrate. More over, passive inductor tends to give a single-band operation
for the design since it has a fixed inductance value.
Active inductors can also achieve multi-band operation. Its capability to tune
and switch the inductance value has made them more reliable to use. Furthermore, Qfactor value can be tuned to achieve the design specification. Even though we can
have smaller die area and programmable capability, we need to pay their trade off by
introducing a higher noise and power consumption in our design. Therefore, a good
consideration needs to be made to make sure our design performance can be
achieved with active inductor as an alternative to avoid passive inductor.
7
2.2.2 Active Inductor Architecture
Active inductor is designed by using the gyrator-C topology to provide the
inductance. Gyrator-C is developed by using two amplifiers which are connected
back-to-back. This topology is capable of transforming the intrinsic capacitance from
the amplifier to an inductive behavior. The gyrator-C topology is depicted in
Figure2.1 [1]
Figure 2.1 – Basic Gyrator-C Topology
Based on Figure 2.1, there are 4 main components which are total
tranconductance of amplifier1, gm1, transconductance of amplifier2, gm2, parasitic
capacitance of amplifier1, C1 and parasitic capacitance of amplifier2, C2. Based on
this architecture, the inductance and the resonant frequency, fr of the active inductor
can be introduced by these equations [2]:
L=
C2
g m1 g m 2
Æ (2.1)
fr =
g m1 g m 2
C1C 2
Æ (2.2)
Based on Equation 2.1, it shows that we can tune the inductance value by
tuning the gm1 and gm2 rather than tuning C2 as its value are fixed by the length and
width of the transistors. To increase the inductance value, we need to decrease the
current as this will decrease gm1 and gm2. Therefore, to have smaller inductance value,
8
a higher current need to be supplied to increase gm1 and gm2.The same method can be
applied to increase the fr by referring to Equation 2.2. This will increase power
consumption of the design if smaller inductance value and higher resonant frequency
are required.
To have design simplicity, an active inductor model can be used to have
better understanding on how it can be implemented in main circuit. Furthermore, we
can also study the behaviors of active inductor by reviewing at the model, as depicted
in Figure2.2 [3]
Figure 2.2 – Active inductor Model [3]
As we can see, active inductor can be modeled as four passive components,
C, R, L and RL. The main component that we want is L. RL represents the loss of
inductor, which is the main factor to control Q-factor. C and R are the parasitic
components at the input. Below are the equations for the rest of the components, C, R
and RL.
C=
RL =
R=
1
2C 1
2g 2
g m1 g m 2
g1
2
Æ (2.3)
Æ (2.4)
Æ (2.5)
where g1 and g2 are output transconductance of gm1 and gm2 respectively. Based on
equation 2.4, we can have a high Q-factor by lowering the g2, rather that increasing
9
the current. This could be done by having a bigger length of gm2. All these
components will be explained briefly in the next chapter.
From the model, a series of C and R will produce a high-pass filter and a
parallel of L and RL will produce a low-pass filter. Therefore, a combination of highpass and low-pass amplifier will act like a band-pass filter, one of the behaviors of
active inductor. Even though active inductor can act as a filter, their very narrow
behavior is not suitable for filter purposes.
There are four active inductors’ architecture discussed next, namely
i. Basic active inductor
ii. Cascode active inductor
iii. Regulated cascode active inductor
iv. Differential active inductor
10
2.2.2.1 Basic Active Inductor
Based on the active inductor architecture, the simplest way to design an
active inductor is by using joining two amplifiers back-to-back. The simplest
amplifier is actually the transistor itself. The circuit of basic active inductor is
depicted in Figure 2.3 [4]:
Figure 2.3 – Circuit of Basic Active Inductor [4]
As shown in Figure 2.3, M1 and M2 are amplifier1 and amplifier2
respectively. The parasitic capacitance of both transistors will provide C1 and C2 to
this circuit. However, this architecture has limited Q-factor values as the output
transconductance at V1 is quite big.
11
2.2.2.2
Cascode Active Inductor
To improve the previous architecture, a cascode technique can be used to
reduce the output transconductance at V1 [5]. Therefore, transistor M3 is introduced to
increase Q-factor values, as shown in Figure 2.4. M3 will be biased by external Vbias.
Even though we have reduced output transconductance at V1, a new problem occurs
as M3 will limit the resonant frequency.
Figure 2.4 – Circuit of Cascode Active Inductor [5]
12
2.2.2.3
Regulated Cascode Active Inductor
To improve the cascode active inductor, a regulated cascode active inductor
is introduced. The circuit of this architecture is shown in Figure 2.5 [2],[3]. This
circuit has the same architecture as before, but has additional transistor M4 and new
current source, I3. The reason we add M4 is to increase the resonant frequency and to
increase the Q-factor. Even though we have M3 to control the output conductance,
but the appearance of M4 has increased the Q-factor value. Furthermore, this
architecture does not need an external Vbias for M3 as it is provided by V3.
The main drawback of this architecture is it increases the power consumption
of our design as we need to introduce another current source, I3.
Figure 2.5 - Circuit of Regulated Cascode Active Inductor [2], [3]
13
2.2.2.4
Differential Active Inductor
This topology introduces a differential type of active inductor. A differential
architecture can provide a high transconductance, thus this design can achieve
smaller inductance value. As noise is one drawback of active inductor, a differential
architecture can improve noise performance by rejecting the common-mode noise.
Based on Figure 2.6, two current sources, IQ1 and IQ2 are introduced to
improve Q-factor value by using M3, M4, M7 and M8 as negative resistance resistor
[1],[4]. Furthermore, these current sources can be used to tune the Q-factor value.
This architecture provides more programmability to the designers by having an
inductance and Q-factor tuning.
Figure 2.6 – Circuit of Differential Active Inductor [1],[4]
14
2.3
Low Noise Amplifier
The first stage of a receiver is typically a LNA [6], whose main function is to
provide enough gain to overcome the noise of subsequent stages. LNA receives a
signal from the antenna and will amplify by the LNA. Apart from providing this
gain, LNA should also introduce as little noise as possible. Frequently, LNA should
present specific impedance such as 50 Ω to the input and output source.
Figure 2.7 – LNA in a receiver
As depicted in equation 2.6, the total noise of a system can be reduced by
making the first stage of amplifier to have high gain and low noise factor [6], [7], [8]
NFtotal = NF1 +
where
NF n − 1
NF 2 − 1 NF3 − 1
+
+ ... +
Av1
Av1 Av 2
Av1 Av 2 Av 3 ... Avn −1
NF1 ≈ LNA noise of stage 1
NF2 ≈ LNA noise of stage 2
NF3 ≈ LNA noise of stage 3
NFn ≈ LNA noise of stage n
Av1 ≈ LNA voltage gain of stage 1
Av2 ≈ LNA voltage gain of stage 2
Av3 ≈ LNA voltage gain of stage 3
Avn ≈ LNA voltage gain of stage n
Æ (2.6)
15
2.3.1
LNA Architecture
To design a good LNA, there are several common goals. These include
minimizing the noise figure of the amplifier, providing gain with sufficient linearity
and providing a stable 50 Ω input impedance to terminate an unknown length of
transmission line which delivers signal from antenna to the amplifier [9].
With these goals in mind, we will first focus on the requirement of providing
stable input impedance. To present known resistive impedance to the external part of
the circuit, four architectures will be discussed in this chapter, they are:
i. Common source amplifier
ii. Shunt-shunt feedback amplifier
iii. Inductive source degeneration amplifier
iv. Common gate amplifier
2.3.1.1
Common Source Amplifier
The first architecture that will be discussed is common source amplifier. The
basic circuit of this architecture is depicted in Figure 2.8:
Figure 2.8 - Common Source Amplifier Circuit
16
where
Vs
≈ Signal input from antenna
Zs
≈ Total impedance of LNA
Zin
≈ Input impedance of LNA
Ls
≈ Source Inductor
RL
≈ Resistor load
As illustrated in Figure 2.8, input signal will flow into the gate of the
transistor and then will be amplified by the overall gain of this circuit. To have a
better understanding of this circuit performance such as input impedance, noise
factor (NF) and voltage gain (Av), all the equations are listed in Table 2.1:
Table 2.1 - Common Source Amplifier Performance
Performance
Equation
Z in = Rs +
Input Impedance
1
⎛
1
j ⎜⎜ϖC gs −
ϖL s
⎝
⎞
⎟⎟
⎠
Rs is Inductive Loss of Ls
Noise Factor
NF = 2 +
Gain
Av =
4λ
; λ is
g m Rs
− g m RL
2
Based on Table 2.1, the reason we used LS is to cancel out the imaginary
component introduced by transistor parasitic capacitance of gate to source, Cgs of the
transistor. Hence, Zin will be equal to Rs. To get Zin = 50 Ω by Rs itself is quite
unreasonable because inductive loss value is very small. We can use a shunt resistor
to achieve 50 Ω. Furthermore, by increasing the shunt resistor we can reduce the NF.
As this resistor has no relation to Av, we can have a higher Av by increasing the
current
to
increase
gm
and
to
have
bigger
RL.
17
2.3.1.2
Shunt-shunt feedback Amplifier
This topology is the same with the previous topology but feedback resistor,
RF is introduced as a feedback component. This topology is depicted in Figure 2.9.
Figure 2.9 - Shunt-shunt feedback amplifier circuit
To study the performance of this topology, we will refer to Table 2.2.
Table 2.2 - Shunt-shunt feedback Amplifier Performance
Performance
Equation
Z in =
Input Impedance
RF + RL
1
+
1 + g m RL
⎛
1
j ⎜⎜ϖC gs −
ϖL s
⎝
Noise Factor
R
NF = 1 + S
RF
Gain
Av = − g m RL
⎛
1
⎜⎜1 +
g m RS
⎝
⎞
⎟⎟
⎠
2
⎞
λ
⎟⎟ +
g m Rs
⎠
The main reason we add the feedback component is to improve the Zin.
Furthermore, Av is increased by factor of 2 and can be used to shrink the NF. Thus,
this
topology
is
better
than
Common
Source
Amplifier
architecture.
18
2.3.1.3
Inductive Source Degeneration Amplifier
This architecture does not use resistor as its main component to control Zin.
That is why Lg is introduced as a matching component to cancel out Cgs. RF in
previous circuit has increased the NF. Therefore, this architecture should have better
NF and can also provide specific Zin without degrading the noise performance of the
amplifier. The circuit for this architecture is shown in Figure 2.10. Table 2.3 shows
the performance of this architecture.
Figure 2.10 - Inductive Source Degeneration Amplifier Circuit
Table 2.3 - Inductive Source Degeneration Amplifier Performance
Performance
Equation
Input Impedance
Z in =
Noise Factor
NF = 1 +
Gain
Av =
⎛
1 ⎞⎟
g m LS
+ j ⎜ϖ (Lg + LS ) −
⎜
C gs
ϖC gs ⎟⎠
⎝
γ
g m RS
(2ϖ
RS C gs )
2
0
− g m RL
2ϖ 0 R S C gs
Even though this architecture has improved the design performance, our
calculation is becoming more complex.
19
2.3.1.4
Common Gate Amplifier
This topology receives signal at the source of the NMOS, as illustrated in
Figure 2.11. Similar to inductive source degeneration architecture, there is no resistor
introduced. This is because the matching component is controlled by the
transconductance of the transistor itself. Therefore, a proper selection of device size
and bias current can provide the input matching.
Figure 2.13 - Common Gate Amplifier Circuit
To study the performance of this architecture, we can refer the list in Table
2.4.
Table 2.4 - Common Gate Amplifier Performance
Performance
Input Impedance
Equation
Z in =
1
1
+
gm
⎛
1
j ⎜⎜ϖC gs −
ϖL s
⎝
Noise Factor
NF = 1 + γ
Gain
Av = g m R L
⎞
⎟⎟
⎠
20
2.4
Comparison of LNA Architecture Performance
To study the comparison between all of the architectures, some example
parameters are set. These are γ = 2, gm = 20 mS, Qin = 2, RS = 50 Ω and RF = 500 Ω.
These parameters are set to have better comparison on different LNA architecture
implementations. Table 2.5 shows the performances for each architecture describe in
subsection 2.3.1.1 to 2.3.1.4, with Qin =
1
2ϖ 0 R S C gs
Table 2.5 – Comparison between all architectures
Arch.
Common
Source
Feedback
Amplifier
Inductive
Source
Degeneration
Common
Gate
Zin
NF50Ω
RS
2+
RF + RL
1 + g m RL
R
1+ S
RF
g m LS
C gs
1+
1
gm
1+ γ
Av
4λ
g m Rs
⎛
1
⎜⎜1 +
⎝ g m RS
γ
g m RS
(2ϖ
(example)
− g m RL
2
10 dB
− g m RL
5.9 dB
− g m RL
2ϖ 0 R S C gs
1.8 dB
g m RL
4.7 dB
2
⎞
λ
⎟⎟ +
⎠ g m Rs
R S C gs )
2
0
NF
Based on Table 2.5, inductive source degeneration architecture provides the
best NF. The worst case of NF is introduced by common source amplifier.
CHAPTER III
ACTIVE INDUCTOR AND LNA DESIGN
3.1
Introduction
Based on the previous chapter, we have reviewed some architectures for
active inductor and LNA. Their advantage and disadvantages were also studied to
make sure the best architecture is selected and can be implemented to achieve the
design specification.
In this chapter, active inductor and LNA design are proposed, reviewed and
discussed briefly. The analysis consists of why they are chosen for this design. A
method to integrate active inductor with LNA is also presented. Both design is based
on
1.2
um
CMOS
process.
Process
file
is
shown
in
Appendix
A.
22
3.2
Proposed Active Inductor
Since one of the design goals is to achieve lower noise, differential active
inductor is chosen because differential architecture can reject the common mode
signal. Furthermore, this architecture is capable to have wider tune ability of
inductance and Q-factor values. This will help designer to tune their circuit to suit the
design goals. However, a modification to differential active inductor’s architecture
needs to be done compared to what is discussed in subsection 2.2.2.4. This is to
provide better performance of active inductor on the LNA itself. The proposed
differential active inductor is shown in Figure 3.1.
Figure 3.1 – Proposed active inductor [4]
23
The main modification of the proposed active inductor is done by removing
IQ1 and IQ2. The reasons for this modification are listed below:
•
Ensure Lower Power Consumption
-
As active inductor is tuned by current, this will introduce higher power
consumption. By removing IQ1 and IQ2, we have saved the current of
active inductor to ensure lower power design. As a result of this
technique on power saving, Q-factor cannot be tuned easily.
-
For this case, it is important to make sure Q-factor is set to be as high as
possible. By theory, smaller Rout tends to increase the Q-factor value. In
order to achieve this, the length of M11, M12, M13 and M14 must have
smaller values.
•
Reduce Noise
-
Transistor is known as a noise introducer. Therefore, additional current
source should be eliminated in order to sustain noise-free circuit. This
can improve the noise performance of the active inductor.
As depicted in Figure 3.1, M5, M6, M7, M8 and M9 represent current source, IL
is shown in Figure 2.6. The inductance value can be tuned by providing current
through IX. VX also needs to be given a DC voltage for biasing purpose of M9. After
removing IQ1 and IQ2, M11, M12, M13 and M14 also need to be biased. This is the
reason why M10 is introduced by sharing the same current source with IX. As a result,
the inductance and Q-factor values are controlled only by IX. Even though we lost
free-tuning capability on Q-factor by removing IQ1 and IQ2, IX can be used to control
Q-factor value. However, as IX play a major rule to tune inductance value, IX only
introduces a small effect on Q-factor value. The technique to tune inductance and Qfactor values will be explained in section 3.2.1.
24
3.2.1
Small Signal Analysis
To have a better understanding on how active inductor works, it is very useful
to study the behavior of active inductor by using small signal analysis [9]. From this
analysis, the performance of the active inductor can be studied. The small signal
analysis for proposed circuit is shown in Figure 3.2.
Figure 3.2 – Small signal analysis [2]
g1
≡ Effective output conductance at the drain node for amplifier stage 1
g2
≡ Effective output conductance at the drain node for amplifier stage 2
gm1
≡ Transconductance of the differential pair of stage 1
gm2
≡ Transconductance of the differential pair of stage 2
C1
≡ Effective capacitance between one of the drain nodes of the
transconductance amplifier stage 1 and Gnd.
C2
≡ Effective capacitance between one of the drain nodes of the
transconductance amplifier stage 2 and Gnd.
25
The small signal analysis from Figure 3.2 can be simplified as differential
mode equivalent circuit which is half of the active inductor as shown in Figure 3.3.
Figure 3.3 – Simplified small signal analysis
Based on Figure 3.3, input impedance, Zin of the active inductor is depicted :
Z in =
=
U IN
U '
=2 1
I IN
I1
[ g m1 g m 2
2[ g 2 + sC 2 ]
+ g1 g 2 ] + s[ g1C 2 + g 2 C1 ] + s 2 [C1C 2 ]
Æ (3.1)
where,
g1
= gds1 + gds11
Æ (3.2)
g2
= gds3 + gds13
Æ (3.3)
gm1
= gm1 or gm2
Æ (3.4)
gm2
= gm3 or gm4
Æ (3.5)
C1
= Cdb11 + Cgd11 + Cgd1 + Cdb1 + Cgs3
Æ (3.6)
C2
= Cdb13 + Cgd13 + Cgd3 + Cdb3 + Cgs4
Æ (3.7)
26
Figure 3.4 is an example of the impedance waveform of active inductor.
Calculation to find out inductance value is shown in Appendix B.
Figure 3.4 – A sample waveform of an active inductor
27
From equation 3.1, the simplified model of the proposed active inductor
component, C, R L and RL can be extracted based on active inductor model depicted
in Figure 3.5.
Figure 3.5 – Simplified model of proposed active inductor
The components can be computed using the formulation:
L=
2C 2
g m1 g m 2
Æ (3.8)
RL =
2g 2
g m1 g m 2
Æ (3.9)
C=
C1
2
Æ (3.10)
R=
1
2 g1
Æ (3.11)
From equations (3.8) to (3.11), the frequency of operation, f0, and Q-factor, Q
for an active inductor are found as:
f0 =
Q=
1
2π LC
=
g m1 g m 2
C1C 2
X L 2πf 0 C 2
=
RL
g2
Æ (3.12)
Æ (3.13)
28
Based on the equations (3.8) to (3.13), the tuning capability can be studied. In
this case, Ix is the main control for tuning the inductance and resistor loss value. By
increasing Ix, gm1 and gm2 will increase and tends to reduce the inductance value, and
vice versa if Ix is reduced. As a result, power consumption of active inductor
becomes worse if lower inductance value is needed. Even though transconductance
can be increased by having bigger width, this method will limit the tuning range of
the inductance value.
The same problem will occur if higher f0 is needed. Based on equation (3.12),
the only component to tune the frequency are gm1 and gm2 since C1 and C2 have the
fix values based on width and length of the active inductor. Therefore, f0 will change
each time we tune the current.
In order to achieve better Q-factor value, it is quite important to study
equation (3.13). C2 and g2 are the only parameters that can be considered to control
Q-factor value. Parasitic capacitance is hard to tune as it has a complex connection
with the device itself. Therefore, g2 is the easy way to ensure better Q-factor value.
This matter can be done by providing the smallest length to the related transistors to
g2. Although f0 can be used to control Q-factor, the changes can affect the inductance
value.
Based on Figure 3.1, active inductor can be connected to a system by
connecting input of the system to active inductor point (F+) and active inductor point
(F-) to the next point of the system. If active inductor is connected series with the
input signal of system, the signal need to go through active inductor. In this case,
active inductor is not suggested to be used in the line signal because the signal will
be distorted by the active inductor itself. Furthermore, since active inductor is a noisy
circuit, it is not suggested to implement active inductor in low noise application.
29
Although it is stated to prevent using active inductor in a low noise
application, it is very important to study the impact of active inductor in the low
noise device. This is the reason why LNA is being chosen as a medium to study the
effect of its performance. Therefore, new method needs to be introduced to block or
shrink noise from active inductor. This technique will be discussed in Chapter IV.
Table 3.1 summarize the advantages and disadvantages of the analysis of the
proposed active inductor.
Table 3.1 – Summary of proposed active inductor analysis
Advantage
Disadvantage
•
Reduce power consumption
•
Reduce Q-factor tuning dependency
•
Reduce noise performance
•
Bigger Q-factor
•
Smaller layout area
Simulation result of active inductor based on analysis describe in this
subsection
will
be
presented
in
Chapter
IV.
30
3.2.2 Active Inductor Design
Based on equations (3.8) to (3.13) and small signal analysis, the active
inductor is designed. Table 3.2 shows the width and length (W/L) for each transistor
in the active inductor. Each transistor size is calculated for a specific value of current
to make sure all the transistors are in the saturation region. This active inductor is
supplied by 0.6 mA to 2.5 mA. The current outside this range will drive some
transistors to be in the triode region. The simulation and result analysis of active
inductor with transistor sizes shown in Table 3.2 will be studied in Chapter IV.
Table 3.2 – Active inductor transistors sizes
Transistor
Width(μm) Length(μm) Transistor
Width(μm) Length(μm)
M1
222
1.2
M8
98.4
1.2
M2
222
1.2
M9
98.4
1.2
M3
222
1.2
M10
67.2
1.2
M4
222
1.2
M11
67.2
1.2
M5
196.8
1.2
M12
67.2
1.2
M6
196.8
1.2
M13
67.2
1.2
M7
98.4
1.2
M14
67.2
1.2
31
3.3
LNA design with Active Inductor
In Chapter II, inductive source degeneration is shown to be the best
architecture that can give the lowest Noise Factor value. Since we planned to use all
active inductors in our design, adding active inductor in the input path may introduce
higher noise to LNA and might change input signals. Figure 3.6 shows the active
inductors implementation to inductive source degeneration architecture.
Figure 3.6 - Inductive Source Degeneration with Active Inductor
Based on Figure 3.5, Lg and Ls need to use active inductor. Since signal will
flow from Lg, any noise generated by Lg will be seen by LNA and will be amplified.
With active inductor applied to Lg, noise generated by active inductor itself will
increase the noise of LNA. Furthermore, the proposed active inductor is not designed
to connect to ground signal. In this case, proposed active inductor should not be used
for Ls.
Since noise performance of LNA is very important, inductive source
degeneration architecture is not the best architecture to be used for this research.
Adding a noisy circuit on input line might initiate worst noise performance
eventhough this architecture shows to have lowest NF in Chapter II. To ensure better
noise performance, the architecture that does not require active inductor in series
with LNA input will be the best choice.
32
As common gate architecture will not use active inductor in series with LNA
input signal, this architecture will be the best option to improve noise factor
performance of the LNA. Eventhough the noise factor of common gate architecture
is bigger than inductive source degeneration, it still has the second lowest noise
factor. Figure 3.7 shows the modified version of common gate architecture with
active inductor.
Figure 3.7 – Common Gate with Active Inductor
Based on Figure 3.7, Figure 3.8 shows the proposed architecture for LNA
with active inductor implementation.
Figure 3.8 – Architecture for common gate LNA with active inductor
33
In this architecture, M2 and M4 provide biasing value to M1 and M3. M1 and
M3 is the amplifier stage on LNA. This design proposed to use two active inductor,
Active Ls and Active Ld. Active Ls is used to tune to control Zin while Active Ld is
used to tune output impedance, Av and f0. Additional capacitance, Cd is added to
block DC to Active Ld and used to minimize noise. Cd also improves phase margin,
PM of the LNA.
Calculation to achieve transistors sizes and active inductor requirement are
shown in Appendix C.
CHAPTER IV
SIMULATION RESULT AND ANALYSIS
4.1
Introduction
This chapter presents the simulation results obtained from active inductor and
LNA designs discussed in Chapter III. Based of these results, analysis is done to
summarize the advantage and disadvantages when we integrate active inductor and
LNA.
The analysis will be focused on the impact of an active inductor to LNA and
how to achieve design target.
35
4.2
Active Inductor Analysis
It is important to analyze active inductor and to understand the active
inductor behavior before we finalize the design. The study will be based on these
parameter:
i. Inductance tuning
ii. Frequency response
iii. Q-factor
iv. Noise
To study these parameters, active inductor transistors sizes used W/L values
as shown in Table 3.2. These transistors are sweep from 50 um to 500 um. Table 4.1
shows the proposed W/L for active inductor study.
Table 4.1 – Active inductor transistor size
Transistor
Width(μm) Length(μm) Transistor
Width(μm) Length(μm)
M1
500/50
1.2
M8
98.4
1.2
M2
500/50
1.2
M9
98.4
1.2
M3
500/50
1.2
M10
67.2
1.2
M4
500/50
1.2
M11
67.2
1.2
M5
196.8
1.2
M12
67.2
1.2
M6
196.8
1.2
M13
67.2
1.2
M7
98.4
1.2
M14
67.2
1.2
36
4.2.1 Analysis – Inductance and f0 Tuning
Based on Chapter III, inductance equation is stated as
L=
2C 2
g m1 g m 2
Æ (3.8)
From Equation 3.8, there are two design variables that designers can vary, parasitic
capacitance and transconductance.
Table 4.2 – Design Variable for Inductance Tuning
Design Variable
Parasitic caps
Transconductance
Low Inductance
High Inductance
Smaller W/L
Bigger W/L
Bigger current
Lower current
Smaller VGS1/2/3/4
Bigger VGS1/2/3/4
Bigger W/L
Smaller W/L
Since we are able to use current to sweep inductance value, and VGS is
affected by the applied current, only transistor size can be tweaked. Since there is
mismatch between low and high inductance for transistor size (refer to Table 4.2), we
would define which variable that is dominant to inductance tuning.
37
Figure 4.1 shows the simulation result when the widths of M1, M2, M3 and
M4 are swept from 50 um to 500 um. Ibias is set constant to 1.5 mA. Since the result
is based on impedance value, calculations have to be carried out in order to get
inductance value. These are shown in Appendix A.
Figure 4.1 – Sweep width of M1, M2, M3 and M4
From Figure 4.1, inductance and f0 value when W is swept from 50 um to 500
um are L(W=50mu) = 39.5 nH with f0 = 3.6 GHz and L(W=500mu) = 18.5 nH with f0 =
1.85 GHz. These values are within the inductance targeted value, 22.4 nH. Figure 4.1
also shows that tranconductance is dominant compared to parasitic capacitance.
Bigger width tends to provide lower inductance value. However, bigger W will have
lower inductance but will reduce f0. This is expected based on equation (3.12). For
with smaller widths, when inductance value decrease, f0 decrease. Bigger width also
tends to increase Q-factor value since it reduces output resistance.
38
Next analysis is to check inductance value when Ibias is changed and
transistor width is set to 50 um and 500 um. The purpose of the analysis is to
determine the width that can provide wider tuning capability and higher f0.
Figure 4.2 shows the simulation result when widths of M1, M2, M3 and M4
are set to 50 um. Ibias is swept from 0.6mA to 2.5mA. The purpose of this check is
to find out whether small transistor width will give higher f0 and lower inductance.
Figure 4.2 – Sweep Ibias (0.6 mA to 2.5 mA) with W=50 um
From Figure 4.2, inductance and f0 when width is 50 um and Ibias is swept from
0.6mA to 2.5mA are L(0.6mA) = 86.6 nH with f0 = 2.45 GHz and L(2.5mA) = 24.3 nH
with f0 = 4.5 GHz. It shows that smaller width has wider range and has higher f0. The
results also show that higher current will increase f0 at a cost of lower inductance
value and worse Q-factor value.
39
Figure 4.3 shows the simulation when widths of M1, M2, M3 and M4 are set
to 500 um. Ibias is swept from 0.6 mA to 2.5 mA. The purpose of this analysis is to
determine the impact of f0 and inductance value with different transistor width.
Figure 4.3 – Sweep Ibias (0.6 mA to 2.5 mA) with W=500 um
Based on Figure 4.3, inductance and f0 when width is 500 um and Ibias is swept
from 0.6mA to 2.5mA are L(0.6mA) = 39.8 nH with f0 = 1.33 GHz and L(2.5mA) = 13.1
nH with f0 = 2.1 GHz. The result shows that higher width will have narrow
inductance range and lower f0. The result also shows that higher current will increase
f0 at a cost of lower inductance value and worse Q-factor value
40
Table 4.3 shows the result summary on 50 um and 500 um width for
transistors M1, M2, M3 and M4. The result shows that lower width for M1, M2, M3
and M4 will have wider range of inductance tuning capability and higher frequency.
Smaller width is suggested for application that needs high f0 with bigger inductance
value. However, Q-factor for lower width is small but bigger width provides better
Q-factor. Applications that need lower inductance value need bigger area and vice
versa for bigger inductance.
Table 4.3 – Summary of different width on M1, M2, M3 and M4
Inductance(L)
f0
Q-factor
Smaller Width (50 um)
Bigger Width (500 um)
86.6 nH to 24.3 nH
39.8 nH to 13.1 nH
2.45 GHz to 4.5 GHz
1.33 GHz to 2.1 GHz
8 to 28
36 to 94
41
4.2.2 Analysis of Q-factor
From the analysis presented in subsection 4.2.1, higher widths for M1, M2,
M3 and M4 are able to provide higher Q-factor value. However, it will minimize
inductance to be tuned in a wider range. Another variable that can be tuned to have
bigger Q-factor is the output resistance.
Below is the equation for Q-factor (as in equation (3.13))
Q=
X L 2πf 0 C 2
=
RL
g2
Æ (4.1)
r0 =
VE L
ID
Æ (4.2)
g2 = gds3 + gds13
Æ (4.3)
From the equation (4.1) to (4.3), we can have higher Q-factor value by
increasing the transistor lengths of M11, M12, M13 and M14. To prove this method
can increase Q-factor value, the simulation is run again based on W=50 um but with
double sizes of W/L of M11, M12, M13 and M14. Ibias is swept from 0.6 mA to 2.5
mA. Results are shown in Figure 4.4. Table 4.4 shows the summary of active
inductors performance width different sizes of W/L of M11, M12, M13 and M14
42
Figure 4.4 – Q-factor improvement
Table 4.4 – Summary of different W/L on M11, M12, M13 and M14
L = 1.2 um, W = 67.2 um
L = 2.4 um, W = 134.4 um
86.6 nH – 24.3 nH
288 nH – 26.2 nH
2.45 GHz – 4.5 GHz
1.2 GHz – 4.25 GHz
8 - 28
68 - 43
Inductance(L)
f0
Q-factor
From Figure 4.4 and Table 4.4, Q-factor value, inductance and f0 range
increase with double sizes of W/L. These proved that bigger W/L has increased Qfactor value. However, bigger W/L for M11, M12, M13 and M14 tend to move
transistors to the triode region.
43
4.2.3
Analysis on Noise
Since noise is a big concern for LNA, it is important to study noise that are
generated by active inductor. Studies that will be done are based on previous analysis
where we set width for M1, M2, M3 and M4 to 50 um and 500 um and Ibias is swept
from 0.6 mA to 2.5 mA. Figures 4.5 and 4.6 show the noise simulation results.
Figure 4.5 – Noise with width of M1, M2, M3 and M4 as 50 um
Figure 4.6 – Noise with width of M1, M2, M3 and M4 as 500 um
44
Based on the results in Figure 4.5 and 4.6, noise performance can be
improved when bigger widths for M1, M2, M3 and M4 are used on active inductor
design. The overall output noise is bigger on lower width. The highest output noise is
found on the lowest and highest currents. To minimize noise impact, Ibias should be
in the middle range.
4.2.4
Summary of Analysis
Based on the previous analyses on sections 4.2.1, to 4.2.3, M1, M2, M3 and
M4 with bigger widths will narrow inductance range, increase higher Q-factor and f0.
The results also show that higher width will have higher noise performance.
As a result, the widths of M1, M2, M3 and M4 are set to 222 um. This width
number is based from the middle number of 50 um and 500 um, to ensure wider
inductance range with higher Q-factor value. Figures 4.7 and 4.8 are the results of
active inductor that will be used in this design.
45
Figure 4.7 – Inductance result with W = 222 um
Figure 4.8 – Noise performance with W = 222 um
46
Table 4.5 shows the performance summary of active inductor design with W
= 222 um on M1, M2, M3 and M4. Ibias is swept from 0.6 mA to 2.5 mA
Table 4.5 – W = 222 um summary
W = 222 um
Inductance(L)
96.46 nH – 24.71 nH
f0
1.1 GHz – 1.84 GHz
Q-factor
Output noise
119.9 - 22
Max = 35
Min = 19
Based on Table 4.5, it shows that wider range is achieved from 24.71 nH to
96.46 nH. Q-factor value can be achieved from 22 to 119.9. The result on Figure 4.8
shows that output – input noise is 16 uV/Rt[Hz]. This result shows the lower noise
on proposed active inductor and can minimize noise impact.
47
4.3
LNA with Active Inductor Analysis
For this section, we will analyze LNA behavior when we combine active
inductors. To meet LNA spec, we will tune Active Ls and Active Ld to meet:
•
Zin
= 50 Ohm
•
Zout
= 50 Ohm
•
Av
> 15 dB
•
NF
< 10 dB
•
PM
> 60
•
Power < 100mW
LNA transistor sizes are based on calculations in Appendix C. Active
inductor transistors sizes are based on the study in section 4.2.3.
The analyses for LNA with active inductor are based on parameters as shown
below:
i.
LNA with Active Ls sweep
ii.
LNA with Active Ld sweep
iii.
LNA with Cd sweep
48
4.3.1
LNA with Active Ls sweep
Figures 4.9 to 4.13 show the results when Ibias of Active Ls is swept from
0.6 mA to 2.9 mA. Ibias of Active Ld is set to have constant 2.9 mA and Cd = 2pF.
Figure 4.9 – Zin when sweeping Active Ls
Figure 4.10 – Zout when sweeping ActiveLs
49
Figure 4.11 – Gain when sweeping ActiveLs
Figure 4.12 – PM when sweeping ActiveLs
50
Figure 4.13 – Noise when sweeping ActiveLs
Based on the results depicted in Figures 4.9 to 4.13, we can summarize that
Active Ls will only impact on Zin performance.
51
4.3.2
LNA with sweep Active Ld
Figures 4.14 to 4.18 show the results when Ibias of Active Ld from is swept
0.6 mA to 2.9 mA. Ibias of Active Ls is set to have constant 1.5 mA and Cd = 2pF
Figure 4.14– Zin when sweeping ActiveLd
Figure 4.15– Zout when sweeping ActiveLd
52
Figure 4.16– Gain when sweeping ActiveLd
Figure 4.17– PM when sweeping ActiveLd
53
Figure 4.18– Noise when sweeping ActiveLd
Based on Figures 4.14 to 4.18, we can summarize that changes on Active Ld
value will give impact to all LNA performance. The result also shows that Zout is able
to achieve. Higher ibias current on active Ld will provide higher Av and improve
PM. Best noise performance required on lower ibias current. However, low current
will cause lower Av and lower f0. Since our target is to achieve high f0, we may have
bigger noise to compensate with high f0.
54
4.3.3
LNA with sweep Cd
Figures 4.19 to 4.23 show the results when Cd is swept from 1 pF to 6 pF.
Ibias for Active Ls is set to 1.5mA and for Active Ld is 2.9mA.
Figure 4.19– Zin when sweeping Cd
Figure 4.20– Zout when sweeping Cd
55
Figure 4.21– Av when sweeping Cd
Figure 4.22– PM when sweeping Cd
56
Figure 4.23– Noise when sweeping Cd
Based on the results of Figures 4.19 to 4.23, we can summarize that higher
Cd value will improve glitch in Zin and Zout, better PM and noise performance. The
drawback of higher Cd value will cause lower f0 and lower Av. Since this research is
targeted to operate in higher frequency, lower Cd is needed. In this case, 2 pF will be
used for this research.
57
4.4 Final Design – LNA with Active Inductor
Figure 4.24 shows the final design of LNA with Active Ls and Active Ld.
Figure 4.24 – Final Design (simplified)
This design is targeted to have:
•
High Av
> 10db
•
Good PM
> 60
•
Good input/output impedance matching
~50 Ohm
•
Noise Factor
< 10 dB
•
Power Consumption
< 100mW
58
Figure 4.25 shows to final design of LNA with active inductor circuit.
Figure 4.25 – Final Design
Final LNA with active inductor design required ibias for Active Ls is 1.5 mA,
ibias for Active Ld is 2.9 mA and Cd is 2pF. Figures 4.26 to 4.29 show the
performance of common gate LNA with active inductor. Spice file for LNA with
active inductor is shown in Appendix D.
59
Figure 4.26 – LNA with Active L (Av)
Figure 4.27 – LNA with Active L (PM)
60
Figure 4.28 – LNA with Active L (Zin & Zout)
Figure 4.29 – LNA with Active L( NF)
61
Power Consumption
LNA is designed based on 3.3V power supply. Total current consumption by
LNA is 7.6 mA. Active Ls and Active Ld is powered by Vcc = 3 V and Vss = -3V.
Both inductors are biased with different value. Active Ls consumes 9 mA and Active
Ld consumes 14.5 mA. Total power for this design is total of LNA, Active Ls and
Active Ld power.
LNA
= 7.6 mA x 3.3 V
= 22.8 mW
Active Ls
= 9 mA x (3 V + 3 V)
= 54 mW
Active Ld
= 14.5 mA x (3 V + 3 V)
= 87 mW
Total Power
= 22.8 mW + 54 mW + 87 mW
= 163.8 mW
62
Layout for LNA with Active Inductor is shown in Figure 4.30. Table 4.6
shows the performance summary of LNA with active inductor.
Figure 4.30 – Layout of LNA with active inductor
Layout area
= 480um x 600um
= 0.288mm2
Table 4.6 – Performance summary of LNA with active inductor
Technology
1.2 um CMOS
Gain
24.7 dB
f0
850 MHz
Input Impedance
48.87 ohm
Output Impedance
53.36 ohm
Phase Margin
140 degree
NF
8.26 dB
Power
163.8 mW
Area
0.288 mm2
63
Based on Table 4.6, this research has meet design target on Av, PM and NF.
Input and Output impedance value are in the 10% range of 50 ohm target. Power
consumption is higher than what is targeted. This proved that active inductor requires
higher
power
consumption
in
this
research.
64
4.5 LNA Comparison - Active vs Passive Inductor
The purpose of this comparison is to analyze the performance difference
between active and passive inductors. From the LNA with active inductor result,
value for Ld and Ls are calculated to have 49.3 nH and 31.1 nH respectively.
Simulation setting for LNA with passive inductor is show in Figure 4.31.
Figure 4.31– Simulation setting for LNA with Passive L
65
On the1.2 um CMOS process, there is no passive inductor model ready yet. It
is hard to compare active and passive inductors for this process. To solve this
problem, ideal inductor is used for passive inductor. Eventhough this method is not
good to represent passive inductor, ideal inductor react well as passive inductor
compared to active inductor the parameters below:
i. No additional current needed for biasing.
ii. Inductance and Q-factor value are fixed
Passive inductor is well known for area hunger, bigger inductance value will
need more area to draw bigger inductance. From the calculations, inductance value
for Ls and Ld are big, example for this design are 49.3 nH and 31.1 nH respectively.
These inductance numbers will need bigger area to fit in. With active inductor, big
inductance value is not a problem. Furthermore, those values can be achieved by
only one active inductor solution, by using different Ibias. This research proves that
active inductor can achieve wider inductance value but requires higher power
consumption.
66
Figures 4.32 to 4.36 show simulation results for LNA with active and
passive/ideal inductor:
Figure 4.32 – Av Comparison
Figure 4.33– PM Comparison
67
Figure 4.34 – Zin Comparison
Figure 4.35 – Zout Comparison
68
Figure 4.36 – NF Comparison
69
Table 4.7 shows the comparison of LNA with active and ideal inductors.
Table 4.7 – Comparison between LNA with active and ideal inductor
Active Inductor
Passive Inductor
Av (dB)
24.7
23.4
f0 (Hz)
850 M
630 M
Zin (ohm)
53.35
58.21
Zout (ohm)
48.87
64
NF (dB)
8.26
3.3
Power (mW)
163.8
22.8
Area (mm2)
0.288
NA
From Table 4.7, big differences are observed on f0, NF and power
consumption. f0 difference between active and ideal inductor may cause by the active
inductor itself.
If we would like to estimate area needed for passive/ideal inductor, we can
use [2] summary for area estimation. Paper on [2] has stated that each active inductor
will save ~25% of area needed. Since two active inductor are used for this project,
50% area saving is expected. This research requires 0.288 mm2 of area. With
passive/ideal inductor, we may need 0.432 mm2 of area. This area may differ on real
passive inductor since this is an estimation based on [2]
However, higher NF from active inductor implementation is expected. It
increases ~5 dB compared to passive inductor. Additional 5 dB noise is introduced
by active inductor itself. NF might be worst from this research if the designer does
not follow the design consideration for noise optimization that was discussed earlier
in this chapter.
70
LNA with active inductor consumes huge power consumption. As shown in
section 4.4, both Active Ls and Ld consume 141 mW compared to 163.8mW for the
whole research. This shows that 75% of power is consumed by the active inductor
circuits. Compared to ideal/passive inductor, it consumes 22.8 mW. Therefore, it is
not suggested to use active inductor for low power system.
71
4.6
Comparison of LNA design
Table 4.8 shows the performance comparison with other projects to this
research work.
Table 4.8 – LNA design comparison from other research
Compared to other designs, this research has the worst power consumption
and NF. The main difference from other research is this project used all active
inductor for matching purposes. This implementation introduces huge NF and higher
power consumption. Other parameter that need to considered is this research is based
on 1.2 um CMOS process, where it required bigger area is needed with 1.2 um
process and higher voltage supply is used.
However, this research proves that LNA can combine with active inductor
but need to consider on higher NF and higher power consumption.
CHAPTER V
CONCLUSION AND FUTURE WORK
5.1
Conclusion
Differential Active Inductor is used for this design to minimize noise
performance since differential architecture is able to reject common mode noise.
Modification is done compared to [1] by removing Q-factor tunability to reduce
power consumption. With this removal, other component on proposed active
inductor is considered to improve Q-factor value. Analysis is done to ensure the
proposed active inductor will take care of Q-factor value.
LNA and active inductor are able to be combined and able to have high gain
and meet impedance matching. This is done by choosing the best architecture that
can fit in the active inductor block without totally degrading LNA performance.
However, this design consumes a lot of power and has poor NF value due to active
inductor integration.
A total of 75% of overall power consumption is consumed by the active
inductor itself. More over, this research uses two active inductors and uses high Ibias
73
to ensure we can meet high f0 and lower inductance value. If better CMOS process
can be used in this research, power consumption can be improved.
In this active inductor design, it is designed to have higher f0. However, the
active inductor behavior is change when we combine them with LNA. If we need to
support higher f0, we will need higher current to compensate with frequency loss due
to LNA. We also might be able to have higher f0 and save more die area if we apply a
good layout. This design uses basic layout techniques. It is recommended to apply
more layout technique to have better performance.
Compared to other designs, this research totally uses active inductor for
matching and gain control. Since active inductor is well known to have higher noise,
it is expected to introduce big NF ~8dB. The increase of NF that is consumed by
active inductor is proven in section 4.5 when we did comparison on active and
passive/ideal inductor LNA implementation. Active inductor introduces was found to
introduce extra ~5dB to LNA. NF might be worst if noise optimization parameters
are not considered in the design.
Eventhough we have changed the architecture from inductive source
degeneration to common gate architecture, active inductor is still connected to signal
line but not totally flow on input signal path like in inductive source degeneration
architecture. There is a possibility that active inductor has amplified noise and
causing poor NF for LNA. It is recommended to concentrate more on noise reduction
or optimization of active inductor. This poor NF is not seen by other designs such as
[2], [3], [10], [12], [13] and [14] since they used passive inductor on input signal for
noise optimization. Based on this NF result, it is not recommended to use active
inductor in the input stage and for low noise implementation. However, active
inductor is good for input/output impedance matching and for one design solution
that is capable to have multiple inductance values.
From die area point of view, active inductor is expected to save the die area.
However, it is hard to have exact area saving for this process since there is no option
74
for spiral or bonding wire model for 1.2 um CMOS process. [2] shows that ~25%
area saving for each active inductor that being used.
From the analysis, we have better understanding on the impact of active
inductor to LNA performance. Instead of using spiral or wire bonded inductance,
active inductor shows a good start for future implementation that can improve on
noise and power consumption. More researches are needed to overcome active
inductor disadvantages to ensure better performance can be achieved.
75
5.2
Future Work
There are a few items that can be studied for future work. They are mainly to
enhance active inductor performance to ensure better result to the integrated system.
It is suggested as follows:
i.
Low power active inductor that is able to reach lower inductance
value with high f0. Existing design shows that higher power consumes
needed to reach lower inductance value and high f0. This study should
also enhance inductance range for better tuning capability.
ii.
Use better CMOS process that is able to support passive inductor.
Better comparison can be done if passive inductor can be used. Better
CMOS process also will need lower voltage supply, this will help to
reduce power consumption
iii.
Better understanding on noise generated by active inductor. This will
improve noise performance of design and help designer to do more
optimization.
iv.
Layout optimization to ensure active inductor performance is not
degraded compared to schematic.
v.
Floating active inductor is able to be connected to any source. This
will improve active inductor connectivity to any source. Existing
design required DC block to ensure active inductor internal node will
not impacted due to DC value on introduce by the system.
76
REFERENCES
[1]
Grozing M, Pascht A, Berroth M, “A 2.5V CMOS Differential Active
Inductor with Tuneable L and Q for Frequency up to 5 GHz”, Radio
Frequency Integrated Circuits (RFIC) Symposium 2001, pp.271-274, May
2001
[2]
Pascht,A , Ficher, J, Berroth, M, “A CMOS Low Noise Amplifier at 2.4 GHz
with Active Inductor Load”, Silicon Monolithic Integrated Circuits in RF
Systems, 2001, pp.1-5, Sept 2001
[3]
Zhuo W, De Gyvez, JP, Sanchez-Sinencio, E, “Programmable Low Noise
Amplifier with Active Inductor Load”, ISCAS ‘98, pp.365-368, June 1998
[4]
Thanachayanont, A, “Low Voltage CMOS Fully Differential Active Inductor
and It’s Application to RF Bandpass Amplifier Design”, VLSI Technology,
Systems, and Applications 2001, pp.125-128, April 2001
[5]
Yue Wu, X Ding, Ismail M, Olsson, H, “CMOS Active Inductor and It’s
Application in RF Bandpass Filter”, Radio Frequency Integrated Circuits
(RFIC) Symposium 2004, pp.655-658, June 2004
[6]
Bosco Leung, VLSI for Wireless Communication, New Jersey, Prentice Hall
Inc, 2002
[7]
Kenneth R. Laker & Willy MC Sansen, Design of Analog Integrated Circuits
and Systems, Hightstown, McGraw-Hill, 1994
77
[8]
Gray, Hurst, Lewis and Meyer, Analysis and Design of Analog Integrated
Circuits, New York, John Wiley & Sons, Inc, 2001
[9]
Sharaf K, “2-V, 1 GHz CMOS inductorless LNA’s with 2-3 dB NF”, ICM
2000, pp.379-383, Nov 2000
[10]
Akbhari Dilmaghani, R Payne, A, Toumazou, C, “A High Q RF CMOS
Differential Active Inductor”, ICECS 1998, pp157-160, Sept 1998
[11]
Jhy-Neng Ynag, Yi Chang Cheng, Terng-Yin Hsu, Tneg-Ren Hsu, Chen Yi
Lee, “A 1.75 GHz Inductor-less CMOS Low Noise Amplifier with High-Q
Active Load”, MWSCAS 2001, pp 816 – 819, Aug 2001
[12]
Sui kei Tnag, Cheong-Fat Chan, Chiu Sing Choy, Kong Pang PUN, “ A 1.2V,
1.8 GHz CMOS Two Stage LNA with Common Gate Amplifier as An Input
Stage”, ASIC 2003, pp 1042 – 1045, 2003
[13]
R. Mukhopadhyay, SWYoon Y.Park, CH Lee, S.Nuttick & J.Laskar,
“Investigation of inductors for digital Si-CMOS technologies”, Atlanta,
ISCAS 2006, pp3750 – 3753, 2006
[14]
D.K Shaffer , TH Lee, “A 1.5V, 1.5 GHz CMOS Low Noise Amplifier”,
Electrical and Computer Engineering, 2003. (ICECE 2003), pp 745-759, May
1997
[15]
A N Karanicholas, “ A 2.7V 900MHz CMOS LNA and Mixer”, ISCE 1996,
pp 1934 – 1944, Dec 1996
[16]
Shin Y J, Bult K, “ An Inductorless 900 MHz RF Low Noise Amplifier in 0.9
um CMOS”, Custom Integrated Circuits Conference 1997, pp 513 – 516,
1997
78
[17]
Ler Chun Lee; Abu Khari bin A'ain; Albert Victor Kordesch, “A 2.4-GHz
CMOS Tunable Image-Rejection Low-Noise Amplifier with Active
Inductor”, APCCAS.2006, Page(s):1679 - 1682
APPENDIX A
SPICE Transistor Parameter
*N97N SPICE LEVEL1 PARAMETERS* TECHNOLOGY: SCN12
FEATURE SIZE: 1.2 microns
*COMMENTS: American Microsystems, Inc. 1.2 micron ABN.
* DATE: Sep 13/99
* LOT: n97n
WAF: 04
.MODEL NMOS NMOS LEVEL=3 PHI=0.700000 TOX=3.0500E-08
XJ=0.200000U TPG=1
+ VTO=0.6063 DELTA=4.7620E-01 LD=1.2100E-07 KP=7.6456E-05
+ UO=675.3 RSH=6.8720E+01 GAMMA=0.6693
+ NSUB=1.7300E+16 NFS=5.9080E+11 VMAX=2.0890E+05
+ KAPPA=3.8640E-01 CGDO=2.0549E-10 CGSO=2.0549E-10
+ CGBO=4.4943E-10 CJ=2.8197E-04 MJ=5.3962E-01 CJSW=1.3603E-10
+ MJSW=1.0000E-01 PB=9.9000E-01 KF=2.0E-15
* Weff = Wdrawn - Delta_W
* The suggested Delta_W is 1.4000E-06
.MODEL PMOS PMOS LEVEL=3 PHI=0.700000 TOX=3.0500E-08
XJ=0.200000U TPG=-1
+ VTO=-0.9084 DELTA=2.1300E+00 LD=9.0910E-10 KP=2.0436E-05
+ UO=180.5 RSH=2.3050E+01 GAMMA=0.3597
+ NSUB=4.9960E+15 NFS=5.9090E+11 VMAX=1.2600E+05
+ KAPPA=5.6030E+00 CGDO=5.0000E-11 CGSO=5.0000E-11
+ CGBO=4.2631E-10 CJ=3.1189E-04 MJ=4.4543E-01 CJSW=1.7631E-10
+ MJSW=1.0000E-01 PB=7.6608E-01 KF=5.0E-17
* Weff = Wdrawn - Delta_W
* The suggested Delta_W is 1.2920E-06
APPENDIX B
Active Inductor Inductance Extraction from Impedance Simulation
Below is example of impedance result from active inductor simulation
Based on Equation 3.8, there are three main components which are C
All these component value is extracted from output simulation result.
directly taken from simulation output file.
After have all extracted data, apply Equation 3.8 to get inductance value
APPENDIX C
Proposed LNA and Active Inductor Calculation
LNA calculation
Active inductor will be using existing design that is discussed on active
inductor topic. Calculation result might differ from what it is being targeted, however
we can used tune the active inductor to meet our target specification.
General Information
Zin(real)
= 1/gm1
Zin(imaginary)= 1/[sCgs1 + (1/sLs)]
f0
= 1/2π sqrt [1/(Cgs1 Ls)]
Av
= gm1/(gds1 + gds2)
Assumption
f0
= 1.7GHz
Out, Vx
= 1.5 V
In
=0V
Vdd
= 3.0 V
Circuit Calculation
ω02
= 1/ (Cgs1 Ls)
Cgs1
= CGSO W + 0.67 WL Cox
Æ1
= W(CGSO + 0.67 L Cox)
= W[205.49p + 0.67(1.2u)(1.132m)]
Æ Assume L = 1.2u and
= (1.111n)W
Æ2
Cox = 1.132m
Zin
= 1/gm1
= L1/KW1(Vgs1 – Vt)
Æ3
As Zin = 50 Ω
From 3,
50
= L1/KW1(Vgs1 – Vt)
W1
=1.2u/[50(76.456u)(1.5 – 0.6063)
=1.5V, Vt =0.6063
= 351.6u
(W/L)1 = (W/L)2
= 351.6u/1.2u
From 2,
Cgs1
= 1.111n(351.6u)
= 390.6 fF
ID
= KW1(Vgs1 – Vt)2/2L1
= 76.456u(351.6u)(1.5 – 0.6063) 2/2(1.2u)
= 8.95 mA
≈ 9.0 mA
Æ K = 76.456u,Vgs1
(W/L)3 = (W/L)4
= 2ID/K(Vgs3 – Vt)2
= 2(9m)/[20.436u(1.5 – 0.9084) 2
= 2516.6
≈ 3020.4u/1.2u
Ls
= 1/(ω02 C gs1)
= 1/[(2π*1.7G)2 (1.111n*351.6u)
= 22.4 nH
Ls = 22.4 nH is targeted value to meet design requirement. This value will be
achieved by active inductor.
Ld value is taken by sweeping Ibias to find out the best performance that our
design could met.
APPENDIX D
SPICE file for LNA with Active Inductor
* Circuit Extracted by Tanner Research's L-Edit V8.11 / Extract V8.11 ;
* TDB File: C:\Documents and Settings\AfiQ & AyieN\Desktop\My
Design\Layout\CG LNA with ActiveL.tdb
* Cell: Cell0 Version 1.69
* Extract Definition File: C:\Program Files\Tanner EDA\L-Edit
Pro\tech\mosis\mamin12.ext
* Extract Date and Time: 06/26/2006 - 15:05
* WARNING: Node/Element Name Conflicts Found. The following are the
*
Node/Element names that have been renamed.
* Node B has been modified to B_1
* Node C+ has been modified to C+_1
* Node C- has been modified to C-_1
* Node E has been modified to E_1
* Node F has been modified to F_1
* Node Gnd has been modified to Gnd_1
* Node in has been modified to in_1
* Element M1 has been modified to M1_1
* Element M10 has been modified to M10_1
* Element M11 has been modified to M11_1
* Element M12 has been modified to M12_1
* Element M13 has been modified to M13_1
* Element M14 has been modified to M14_1
* Element M2 has been modified to M2_1
* Element M3 has been modified to M3_1
* Element M4 has been modified to M4_1
* Element M5 has been modified to M5_1
* Element M6 has been modified to M6_1
* Element M7 has been modified to M7_1
* Element M8 has been modified to M8_1
* Element M9 has been modified to M9_1
* NODE NAME ALIASES
*
12 = Vss (1180,25)
*
17 = Gnd (784,187)
*
19 = Vdd (1182,120)
*
21 = in_1 (510,239)
*
22 = C+_1 (786,226)
*
23 = C-_1 (778,218)
*
24 = F (864,184)
*
25 = E_1 (725,184)
*
26 = B (232,231)
*
28 = X (59,184)
*
29 = C- (772,76)
*
30 = F_1 (858,42)
*
31 = Gnd_1 (778,45)
*
32 = in (504,97)
*
33 = E (719,42)
*
34 = C+ (780,84)
*
35 = B_1 (226,89)
*
37 = G (53,42)
Cpar1 1 0 859.47525p
* Warning: Node 2 has zero nodal parasitic capacitance.
* Warning: Node 3 has zero nodal parasitic capacitance.
* Warning: Node 4 has zero nodal parasitic capacitance.
* Warning: Node 5 has zero nodal parasitic capacitance.
Cpar2 6 0 430.82761p
* Warning: Node 7 has zero nodal parasitic capacitance.
* Warning: Node 8 has zero nodal parasitic capacitance.
* Warning: Node 9 has zero nodal parasitic capacitance.
* Warning: Node 10 has zero nodal parasitic capacitance.
Cpar3 11 0 58.98551p
Cpar4 Vss 0 266.24758p
* Warning: Node 13 has zero nodal parasitic capacitance.
Cpar5 14 0 426.65336p
* Warning: Node 15 has zero nodal parasitic capacitance.
* Warning: Node 16 has zero nodal parasitic capacitance.
Cpar6 Gnd 0 46.558967p
Cpar7 18 0 41.355893p
Cpar8 Vdd 0 143.07548p
* Warning: Node 20 has zero nodal parasitic capacitance.
Cpar9 in_1 0 63.755931p
Cpar10 C+_1 0 44.698333p
Cpar11 C-_1 0 60.248598p
Cpar12 F 0 49.497539p
Cpar13 E_1 0 49.497539p
Cpar14 B 0 24.907968p
* Warning: Node 27 has zero nodal parasitic capacitance.
Cpar15 X 0 12.111782p
Cpar16 C- 0 85.479287p
Cpar17 F_1 0 49.497539p
Cpar18 Gnd_1 0 46.558967p
Cpar19 in 0 60.465792p
Cpar20 E 0 49.497539p
Cpar21 C+ 0 44.698333p
Cpar22 B_1 0 24.907968p
* Warning: Node 36 has zero nodal parasitic capacitance.
Cpar23 G 0 12.111782p
M1 6 6 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m AS=1.8018n
PS=1.2072m
M2 6 3 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m AS=1.8018n
PS=1.2072m
M3_1 6 2 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m AS=1.8018n
PS=1.2072m
M4_1 6 5 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m AS=1.8018n
PS=1.2072m
M5 6 4 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m AS=1.8018n
PS=1.2072m
M6_1 14 6 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m AS=1.8018n
PS=1.2072m
M7_1 14 8 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m AS=1.8018n
PS=1.2072m
M8 6 7 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m AS=1.8018n
PS=1.2072m
M9_1 14 10 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m AS=1.8018n
PS=1.2072m
M10 14 9 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m AS=1.8018n
PS=1.2072m
M11 Vss 13 11 Vss NMOS L=1.2u W=351.6u AD=1.26576n PD=710.4u
AS=1.26576n PS=710.4u
M12_1 14 16 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m
AS=1.8018n PS=1.2072m
M13 14 15 1 1 PMOS L=1.2u W=600.6u AD=2.16216n PD=1.2084m AS=1.8018n
PS=1.2072m
M14 C-_1 B Vdd Vdd PMOS L=1.2u W=67.2u AD=241.92p PD=141.6u
AS=201.6p PS=140.4u
M15 C+_1 B Vdd Vdd PMOS L=1.2u W=67.2u AD=241.92p PD=141.6u
AS=201.6p PS=140.4u
M16 Gnd B Vdd Vdd PMOS L=1.2u W=67.2u AD=241.92p PD=141.6u AS=201.6p
PS=140.4u
M17 18 20 Vss Vss NMOS L=1.2u W=351.6u AD=1.26576n PD=710.4u
AS=1.26576n PS=710.4u
M18 in_1 B Vdd Vdd PMOS L=1.2u W=67.2u AD=241.92p PD=141.6u AS=201.6p
PS=140.4u
M19 B B Vdd Vdd PMOS L=1.2u W=67.2u AD=241.92p PD=141.6u AS=201.6p
PS=140.4u
M20 Vss X F Vss NMOS L=1.2u W=196.8u AD=708.48p PD=400.8u AS=708.48p
PS=400.8u
M21 C+_1 Gnd F Vss NMOS L=1.2u W=222u AD=799.2p PD=451.2u AS=399.6p
PS=225.6u
M22 F in_1 C-_1 Vss NMOS L=1.2u W=222u AD=399.6p PD=225.6u AS=799.2p
PS=451.2u
M23 Gnd C-_1 E_1 Vss NMOS L=1.2u W=222u AD=799.2p PD=451.2u
AS=399.6p PS=225.6u
M24 E_1 C+_1 in_1 Vss NMOS L=1.2u W=222u AD=399.6p PD=225.6u
AS=799.2p PS=451.2u
M25 Vss X E_1 Vss NMOS L=1.2u W=196.8u AD=708.48p PD=400.8u
AS=708.48p PS=400.8u
M26 27 B B Vss NMOS L=1.2u W=98.4u AD=59.04p PD=99.6u AS=413.28p
PS=205.2u
M27 Vss X 27 Vss NMOS L=1.2u W=98.4u AD=354.24p PD=204u AS=59.04p
PS=99.6u
M28 Vss X X Vss NMOS L=1.2u W=98.4u AD=354.24p PD=204u AS=354.24p
PS=204u
M1_1 C- B_1 Vdd Vdd PMOS L=1.2u W=67.2u AD=241.92p PD=141.6u
AS=201.6p PS=140.4u
M2_1 Vss G F_1 Vss NMOS L=1.2u W=196.8u AD=708.48p PD=400.8u
AS=708.48p PS=400.8u
M3 C+ B_1 Vdd Vdd PMOS L=1.2u W=67.2u AD=241.92p PD=141.6u AS=201.6p
PS=140.4u
M4 C+ Gnd_1 F_1 Vss NMOS L=1.2u W=222u AD=799.2p PD=451.2u AS=399.6p
PS=225.6u
M5_1 F_1 in C- Vss NMOS L=1.2u W=222u AD=399.6p PD=225.6u AS=799.2p
PS=451.2u
M6 Gnd_1 B_1 Vdd Vdd PMOS L=1.2u W=67.2u AD=241.92p PD=141.6u
AS=201.6p PS=140.4u
M7 in B_1 Vdd Vdd PMOS L=1.2u W=67.2u AD=241.92p PD=141.6u AS=201.6p
PS=140.4u
M8_1 Gnd_1 C- E Vss NMOS L=1.2u W=222u AD=799.2p PD=451.2u AS=399.6p
PS=225.6u
M9 E C+ in Vss NMOS L=1.2u W=222u AD=399.6p PD=225.6u AS=799.2p
PS=451.2u
M10_1 Vss G E Vss NMOS L=1.2u W=196.8u AD=708.48p PD=400.8u
AS=708.48p PS=400.8u
M11_1 B_1 B_1 Vdd Vdd PMOS L=1.2u W=67.2u AD=241.92p PD=141.6u
AS=201.6p PS=140.4u
M12 36 B_1 B_1 Vss NMOS L=1.2u W=98.4u AD=59.04p PD=99.6u AS=413.28p
PS=205.2u
M13_1 Vss G 36 Vss NMOS L=1.2u W=98.4u AD=354.24p PD=204u AS=59.04p
PS=99.6u
M14_1 Vss G G Vss NMOS L=1.2u W=98.4u AD=354.24p PD=204u AS=354.24p
PS=204u
* Total Nodes: 37
* Total Elements: 65
* Total Number of Shorted Elements not written to the SPICE file: 24
* Extract Elapsed Time: 4 seconds
.END