i
Time and Frequency Characterization of the High Speed
I/O Data Bus
JIMMY HUANG HUAT SINCE
UNIVERSITI TEKNOLOGI MALAYSIA
iv
God the glory and the highest
My beloved parents
And
My dearest brother and sisters
v
ACKNOWLEDGEMENT
Firstly, I would like to thank God for giving me strength and wisdom in
completing the work, my family in encouraging me to take this course.
I would like to take this oppurnity to express my appreciation to my
supervisor, Prof Madya Dr Ahmad Zuri for his guidance and fully support to
complete the thesis.
Never forget to thank Yew Teong Guan and Ahmad Jalaluddin Bin Yusof
from Intel Corporation, for his guidance, support and information suppied for my
thesis.
Last but not the least, thanks to my friends who help me not matter in
encouragement, support, advice, discussion or commend especially Lai Yit Pin and
Seah Yeow Ngee for student affair coordination.
vi
ABSTRACT
High speed data transfer between the CPU and peripherals on the PC
motherboard is needed to support data traffic in future generation applications such
as multimedia, games and broadband networks. The High Speed I/O data bus is
developed to meet these applications. At high speed with multi Gbits/sec,
impedance mismatch between the CPU and peripherals becomes critical and limits
the possible maximum throughput. This effect can be modeled as a convolution
process where the I/O bus behaves as a linear time invariant system that is defined
by a channel impulse and frequency response. Since there are variations in the
characteristic of the motherboards due to the fabrication and assembly process, it is
desired to estimate the impulse response and frequency response of the High Speed
I/O bus. This information can be used to gage the capability of the motherboard and
use it as feedback to the relevant fabrication and assembly processes. By using
simulation on MATLAB and EDA tools, two candidate methods will be evaluated:
Impulse response and correlation method using simulated channel characteristics.
Robustness of both methods will be evaluated in the presence of noise and cross
talk. Further evaluation will be performed on data collected from actual production
test of the I/O Bus. This is to evaluate the capability of the evaluated methods
under actual manufacturing environment.
vii
ABSTRAK
Data Bas Kelajuan Tinggi antara CPU dan periferal atas Papan Utama
Komputer diperlukan untuk penghantaran data trafik untuk kegunaan seperti
multimedia, kehiburan and kemudahan internet. I/O berkelajuan tinggi diperlukan
untuk memenuhi permintaan tersebut. Dengan kelajuan tinggi sehingga berjuta-juta
perhantaran dalam satu saat, Keselarasan rintangan electrik antara CPU dan
periferal menjadi kritikal dan boleh menghadkan penghantaran data maksimum.
Kesan ini boleh diterangkan sebagai proses pendaraban di mana data bas sebagai
sistem tak ubah dengan masa dan ciri-cirinya boleh dinyatakan tindak balas delta
atau tindak balas frekuensi. Oleh disebabkan wujudnya pengubah semasa process
perkilangan, pempaparan ciri-ciri dalam tindak balas delta dan frekuensi amat
diperlukan. Dengan penggunaan MATLAB dan EDA, dua cara dikajikan, antaranya
adalan tindak balas delta dan tindak balas perkaitkan. Keubahsuaian kedua-dua cara
dalam kebisingan sekeliling dikajikan. Pengkajian seterusnya juga tertumpu kepada
proses perkilangan supaya cara ini boleh digunakan untuk penghasilan buatan
banyak.
viii
CONTENTS
CHAPTER
TITLE
CHAPTER 1
PAGE
TITLE
i
VALIDATION OF E-THESIS PREPARATION
ii
DECLARATION
iii
DEDICATION
iv
ACKNOWLEDGEMENT
v
ABSTRACT
vi
ABSTRAK
vii
CONTENT
viii
INTRODUCTION
1.1
Background
2
1.1.1 High Speed I/O Challenge
2
1.1.2 Communication Blocks of Bus Channel
3
1.2
Objective
5
1.3
Scope
5
1.4
Problem Statement
6
CHAPTER II
LITERATURE REVIEW
2.1
Signal Integrity Enigneering Overview
7
2.2
Time Domain Analysis
8
2.3
Scattering Parameters
10
2.4
Dynamic Modeling Using Transient Response
13
2.5
Dynamic System Modeling using Optimum Filter
13
2.6
Non Linear Modeling Using Neural Network
14
ix
CHAPTER III
THEORY
3.1 Transmision Line Interconnect
16
3.2 Impulse Response Characteristic
17
3.3 Correlation Characterization
18
3.4 Crosstalk, Power Noise and Jitter Noise
23
3.5 Electrical Modeling of Platform Bus Interconnect
25
CHAPTER IV
4.1
METHODOLOGY
Transmission Bus Channel Characterization
29
4.1.1 Device Modeling and Circuit Setup
29
4.1.2 Comparison of Scaterring parameter, Impulse Response
and Correlation Method
31
4.2
Immunity to the Noise
31
4.3
Measurement in the Lab
32
CHAPTER V
RESULT
5.1
Noise Free Environment
5.1.1
Proof of Concept
35
5.1.2
Determination of Correlation Parameters
38
5.1.3
Windowing Technique
40
5.1.4
Simulation Using Simple Transmission Line
45
5.1.5
Simulation Using Full EM Modeling Platform Data
Bus Topology
5.2
CHAPTER VI
35
47
Immunity over Random Noise, Periodic Noise and Jitter
49
CONCLUSION AND RECOMMENDATION
51
REFERENCES
53
x
APPENDIX
55
CHAPTER I
INTRODUCTION
1. Introduction
High speed data transfer between the CPU and peripherals on the PC motherboard
is needed to support data traffic in future generation applications such as multimedia,
games and broadband networks. The high speed I/O differential bus is developed to meet
these applications. At higher speed with multi Gbits/sec, impedance mismatch between
the CPU and peripherals becomes critical and limits the possible maximum throughput.
This effect can be modeled as a convolution process where the I/O high speed behaves as
a linear time invariant system that is defined by a channel impulse and frequency
response. Since there are variations in the characteristic of the motherboards due to the
fabrication and assembly process, it is desired to estimate the impulse response and
frequency response of the bus. This information can be used to gage the capability of the
motherboard and use it as feedback to the relevant fabrication and assembly processes.
By using simulation on MATLAB and EDA tools, two candidate methods will be
evaluated: PDA and correlation method using simulated channel characteristics.
Robustness of both methods will be evaluated in the presence of noise and cross talk.
Further evaluation will be performed on data collected from actual production test of the
1
high speed I/O bus. This is to evaluate the capability of the evaluated methods under
actual manufacturing environment.
1.1. Background
1.1.1. High Speed I/O challenge
Computer system organization has three main components, the CPU, the memory
subsystem and the I/O subsystem. Bus is a terminology used to describe the
interconnecting between the components in the architecture organization. Physically, a
bus is a set of wire to send the information from one component to another; the source
output the components onto the bus. The destination component then inputs this data
from the bus. Due to the increasing complexity of computer architecture, the bus system
is much more efficient in less power consumption; less space and fewer pin than direct
connect from component to component1.
Moore’s Law drives transistor scaling by 2x for every 21 months. Advanced
computer system benefits from the transistor scaling allowing more processing
capabilities can be achieved and higher data bandwidth is needed to support the
increasing processing power (refer to Figure 1) 2 . The performance degrades if the
computer spends most of its time waiting for the data. The needs of data bandwidth is
even critical with the introduction of parallel processing, distribution computing system,
multi core CPU and more efficient pipeline architecture while keep cache size smaller
size or slower growing rate.
1
John D. Carpinelli, “Computer System Organization and Architecture”, Chapter 4, page 141, Addison
Wesley, 2001
2
Maynard Falconer, “Bus Design Boot Camp”, Chapter 1, Intel Corp, 2005
2
Figure 1: Relationship of Moore’s Law and Bus Bandwidth (Courtesy of Intel® Corp)
1.1.2. Communication Block of Transmission Bus Channel
From communication view of point, the transmission bus channel is composed of
transmitter block, bus channel block and receiver channel block as illustrated in Figure2.
The source output is x(t), channel impulse response is h(t) and the receiver output is r(t)
where n(t) is Additive White Gaussian noise. The receiver output is the convolution of h(t)
and x(t) plus summation of n(t)3.
r (t ) = x(t ) ⊗ h(t ) + n(t )
3
Maynard Falconer, “Bus Design Boot Camp”, Chapter 8, Intel Corp, 2005
3
Figure 2: Transmission line can be modeled into communication blocksets
The transmission bus channel is behaves a low pass filter where the channel loss
increase with the frequency. It is due to skin effect loss and dielectric loss. Instead of
amplitude loss, the channel also suffers from phase distortion as Figure 3. Phase
distortion is due to the channel length, dielectric length change, inductance change over
the frequency. As the result, the receiver has closed Eye Diagram4.
Figure 3: Frequency response of transmission line behaves like a low pass filter
Equalizer is implemented to improve the signal quality by introducing the inverse
characteristic of the transmission bus channel so that both equalizer and channel can
cancel each other to retrieve the original transmitting data as Figure 4. The
equalizer, C ( f ) = H −1 ( f ) , can be placed at the transmitter, receiver or both. The
equalizer can be an analog passive high pass filter or discrete FIR filter. Some popular
discrete FIR filter used are pre-emphasis (used in transmitter), Discrete Linear Equalizer
(DLE) and Decision Feedback Equalizer (used at receiver) or advance adaptive equalizer.
No matter which equalizer is used, the H ( f ) must be characterized.
4
Eye Diagram is electrical specification for transmitting or receiving signals. Signal is considered fail to
the specification when it breaks the boundary of the Eye Diagram, where the Eye Diagram looks close.
4
Figure 4: Implementation of equalizer aims to resolve the lossy transmission line
1.2. Objective
The research aims to evaluate the performance and parameters of the proposed
correlation method in transmission bus channel characterization. The evaluation includes
comparison with pulse response method and Scattering parameter measurement on
robustness, algorithm complexity, effectiveness, accuracy and immunity to the
environment noise. An equalizer based on the correlation algorithm is build to evaluate
the performance in the transmission bus channel system.
1.3. Scope
The analysis is done using SPICE and MATLAB focusing on behavior level
simulation excluding any RTL level simulation. The study is based on offline simulation
and the measurement can only be done depending on the hardware readiness. The study
focuses on electrical parameters and assumes the transmission bus channel is a time
invariant system.
5
1.4. Problem Statement
High speed I/O bus design is always hungered due to its significant impact to the
system performance. The challenge consists of large number of process variable,
effecting high volume manufacturing, complex computer organization and cost impact.
Parallel source synchronous bus which it used to be dominant Bus interconnect, cannot
simply increase its bandwidth by scaling the number of bus size and bus speed due to the
ISI (Inter Symbol Interfering) effect, increasing pin count, more variables, larger space
and more tighten timing requirement. Therefore these buses such as PCI migrate to PCIe,
a serial differential bus for the following advantages: noise immunity, fewer pin counts,
less routing space and cost effective. Due to the limited bandwidth of transmission media,
high data rates on printed circuit boards and communication networks impose significant
signal integrity degradation, equalization techniques must be included in the transmitter
and receiver circuitry to compensate for the lossy characteristics of the transmission
channel 5 . Conventional method such as Scattering Parameters measurement cannot
characterize the bus in active operation condition thus an active bus channel
characterization is proposed to resolve the problem
5
M. Cases, D. N. de Araujo, E. Matoglu, “Electrical Design and Specification Challenges for High Speed
Serial Links”, 2005 Electronics Packaging Technology Conference
6
CHAPTER 2
LITERATURE REVIEW
2. Literature Review
2.1. Signal Integrity Engineering Overview
Imagine that the data bus system on motherboard as heavy traffic transportation,
Signal Integrity Engineer (SIE) is the traffic police to set up and control the traffic rules
and regulation. There are three major components, CPU, Memory Controller Hub (MCH)
and I/O Controller Hub (ICH) on the motherboard that dominate 80% of the platform
data traffic activities. SIE main responsibility is providing platform interconnect solution
and ensuring signal quality during signal transfer process. Their activities include buffer
behavior modeling, package parasitic attributes modeling, motherboard interconnect
modeling, simulation deck setup representing the platform data traffic system, simulation
analysis to investigating every possible alternative and High Volume Manufacturing
analysis. SIE has to communicate with circuit designer frequently on output buffer design,
motherboard routing designer, manufacturing representative, motherboard discrete
components provider, customer and client chipset representative to put everything under
one roof to provide design rules guideline that agreed by every counter parts. The
analysis results are divided into time domain and frequency domain analysis. Time
7
domain analysis focuses on measured signal at the receiver end of client. The measured
eye can be analysis via various methods to know whether the signal quality meeting or
failing the specification from the industry compliance. Frequency domain analysis
focuses on interconnect characteristic analysis. It does not indicate the signal failure
directly but is related to the data bus bandwidth.
Figure 5: SIE charter in platform data bus transfer (Courtesy of Intel® Corp)
2.2. Time domain analysis
In time domain analysis, the signal quality is known from the measured overshoot,
undershoot, rising edge, delay time, ring back, ledge and phase shift. Instead of
measuring these attributes individually, an easier measurement technique capturing all
these attributes is introduced and known as Eye Diagram.
8
Eye Diagram is an oscilloscope display in which a digital data signal from a
receiver is repetitively sampled and applied to the vertical input, while the data rate is
used to trigger the horizontal sweep. It is so called because, for several types of coding,
the pattern looks like an eye between a pair of rails. Several system performance
measures can be derived by analyzing the display. If the signals are too long, too short,
poor synchronized with the system clock, too high, too low, too noisy, too slow to change,
or have too much undershoot or overshoot, this can be observed from the eye diagram.
An open eye diagram corresponds to minimal signal distortion which is due to the signal
waveform Inter Symbol Interference (ISI) or noise appears as closure of the eye diagram.
The eye opening (height, peak to peak) measures the additive noise in the signal and peak
distortion while the eye width measures the timing synchronization and jitter effect.
Figure 6: Signal quality from timing analysis (Courtesy of Intel® Corp)
9
Figure 7: Eye Diagram (Courtesy of Intel® Corp)
2.3. Scattering parameters
There’s several way to characterize the transmission bus channel frequency or
impulse response. One way of doing it is using Scattering parameter or known as Sparameter to characterize the frequency behavior of the linear or nonlinear networks
operating with signals sufficiently small to cause the networks to respond in a linear
manner. They can be completely characterized by parameters measured at the network
terminals (ports) without regard to the contents of the networks transmission bus channel.
S-parameter is widely used in the microwave industry for measurement and work in high
frequency because it is conceptually simple and analytical convenient. Once the
parameters of a network have been determined, its behavior in any external environment
can be predicted, again without regard to the contents of the network. S-parameter
measurement is built up using 2 port networks by measuring the incident waves and the
reflection waves. The source and load impedance, Zs and ZL are around 50 ohm where
10
most of the oscillation doesn’t occur at this impedance values6. By shorting, opening and
matching the load impedance, the ZL scattering matrix, S11, S12, S21 and S22 can be
acquire. S11 and S22 represent the reflection from the source and load respectively. S12
and S21 represent the loss from load to source and vice versa respectively. S21 also
represents the transmission bus channel frequency response, H ( f )
Figure 8: Measurement of S-parameters with the presence of Zs and ZL
S-parameter is popular and easy to be used method in the industry for more than
30 years. However, it can only measure the passive network system and cannot be used
when the system is active, for example the computer is running application by
transmitting and receiving the data over the channel. The source impedance is parallel
with the load impedance causing impedance mismatch and thus changing the electrical
behavior. Active characterization is important as the load impedance, temperature, ISI
effect and environment do exist.
6
Hewlett Packard, “S-parameters Technique”, Test and Measurement Application Notes 95-1
11
Figure 9: Fundamental theory of S-parameter measurement
Figure 10: Insertion loss sample
12
2.4. Dynamic System Modeling Using Transient Response
Lennart Lyung and Torkel Glad describe step response or transient analysis show
how and in what time span various affect each other7. From the output variables such as
overshoot, decay time and amplitude help to understand the system characteristic such as
resonance frequency, damping factor and gain. Instead of using step function, impulse
function such a short period of duration can be injected to the desired system. One good
example is servo motor design where a step function, current from idle to load in a very
short transition time is applied then record the overshoot and decay time using encoder.
2.5. Dynamic System Modeling Using Optimum Filter
For image degradation and restoration process, a degradation function is
something called the optical transfer function or point spread function. With the presence
of noise, transient analysis for an image processing may lose its accuracy due to the noise
distortion, another modal is using optimum filter. Wiener filtering is one of the earliest
and best known approached to linear image restoration. This is an optimum filter that is
based on the minimization of mean square error, MSE between the filter output and the
desired signal. The coefficients of the filter are calculated from the MSE to reject the
presenting noise. Wiener filter is not only used to filter out the noise but also can be used
as predicting and smoothing function.
7
Lennar Lyung, Torkel Glad, “Modeling of Dynamic Systems” , chapter 8, page 191-199, Prentice Hall,
1994
13
Interference
due to noise
v(n)
s(n)
Desired
sequence
sd(n)
h(n)
Error
signal
e(n)
y(n)
x(n)
Filter
impulse
response
Ideally y(n) should
be equal to xd(n)
Figure 11: Wiener Block Diagram
Another widely used optimum filter is Least Mean Square algorithm, the h(n)’s
coefficients are solved by using iteration algorithm. The adaptive fileter, h(n) converges
by updating the h(n) coefficients until it reaches to the minimum error, MSE. LMS is
popular due to its simplicity although the convergence speed is needed to be careful tuned
so the MSE can converge. An example of LMS algorithm is Active Noise cancellation
where the environment is modeled into adaptive FIR filter.
Figure 12: An Active Noise Cancellation Block Diagram
2.6. Non Linear System Modeling using Neural Network
14
Both FIR and IIR filters have linear function of the preset and past inputs
and outputs. In active noise and vibration control, system of control actuator and
environment has non-linear characteristic, such as introduced harmonic into
system, and reduce the attenuation performance. Thus it is desired to use the nonlinear filter, the artificial neural network. Its performance compared with FIR
filter, with the same input, same sampling rate, when a tone plus its first harmonic
(non linear), is capable to suppress both the tone and harmonic, while FIR filter
can only suppress the tone. However, the major problem of neural network is its
lack of predictability and consistency, make it not widely used. So more effort is
taken not only for design the desired performance neural network controller, but
also perform it consistently, speedily convergence and reduce signal distortion.
15
CHAPTER 3
THEORY
3. Theory
3.1. Transmission line interconnect
High Speed digital design emphasizes the behavior of active and passive circuit
elements on how they affect signal propagation (ringing and reflection), timing delay
(skew time and jittering), interaction between signal (crosstalk), and interaction with the
natural world (electromagnetic interference). The active elements includes I/O buffers,
op-amp, PLL and data pattern while passive elements include wire, printed circuit board,
IC package, connector and others as Figure 13. At low speed, the passive elements are
just part of the product’s packaging but at higher speed they behave like a transmission
line and directly affect electrical performance8. It is considered as transmission line when
the electrical length is less than 15% of the circuit rising time.
8
Howard Johnson, “High-Speed Digital Design- A Handbook of Black Magic”, Prentice Hall, 1993
16
Figure 13: Interconnect diagram of chip, package and printed circuit board
3.2. Impulse Response Characterization
Active characterization uses impulse response of the system for channel
characterization thus it is known as timing response as well. This method is more
complicated and not easy to be implemented but it can characterize running application
transmission bus channel system9. Same as S-parameter measurement, impulse response
assumes the system must be linear time invariant, h(t).
x (t ) = δ (t )
y (t ) =
∞
h(λ )δ (t − λ )dλ
(1)
(2)
−∞
Y( f ) = H( f )
(3)
H ( f ) = S 21 ( f )
(4)
9
Bryan K. Casper, Matthew Haycock, Randy Mooney, “An Accurate and Efficient Analysis Method for
Multi-Gbls Chip-to-chip Signaling Schemes”, 2002 Symposium On VLSl Circuits Digest of Technical
Papers
17
y (k ) =
N
h(n)δ (k − n)
(5)
n =0
Where y(t) is the h(t). In order to create the impulse response, the transmitter must
send out the pulse which has every fast rising time and short pulse period, which is not
practical in today bus system.
Instead of sending an impulse response, there’s another way by sending in step
pulse and then differentiate the step response of the output.
x (t ) = u (t )
(6)
∞
∂
∂
y (t ) =
h(λ )u (t − λ )dλ
∂k
∂t −∞
(7)
∞
∂
∂
y (t ) = h(λ )
u (t − λ ) dλ
∂k
∂t
−∞
(8)
∞
∂
y (t ) = h(λ )δ (t − λ )dλ
∂k
−∞
∂
y (k ) =
∂k
N
n =0
h(n)u (k − n) −
(9)
N
h(n)u (k − 1 − n)
(10)
n=0
The step response do not require short pulse period and is much more practical to
be used. However, it needs long ‘0’ pulse and ‘1’ pulse to create the system response.
The training code has to be written to generate these long sequences thus introduces large
overheads to the data packet. It is not suitable to be used for real time bus channel
characterization due to its large overheads. The silicon healthy may impact to the rising
time because the slow corner’s rising time is slower and it may create uncertainty.
3.3. Correlation Characterization
Due to the complexity and overheads in generating the impulse or step response to the
transmission bus channel, an easier way and efficient data packet usage method is needed
to improve transmission bus channel characterization robustness. Auto and Cross
correlation method is proposed using the channel characteristic because the data packet
pattern behaves as a pseudo random sequence generator (PRSG).
RXX (τ ) = E[ X (t ) X * (t − τ )] , general auto correlation function
(11)
18
R XX (τ ) = P0 (1 −
|τ |
),
Tb
(12)
where the input is pseudo random sequence, Tb is the pulse period and P0 is the average power of
the random sequence as Figure 14
R XX (τ ) ≈ σ x2δ (τ ) ,
(13)
If the pseudo random has a long and non repetitive sequence with as Figure 15 with σ x2
is the variance of the inputs
S XX ( f ) =
∞
{
T /2
1
RXX (t1 , t1 − τ )dt1 }exp(− j 2πfτ )dτ
T →∞ T
−T / 2
lim
(14)
1
RXX (t1 ,τ )dt1 = RXX (τ )
T →∞ T
−T / 2
(15)
−∞
T /2
lim
S XX ( f ) =
∞
RXX (τ ) exp(− j 2πfτ )dτ
(16)
−∞
For a impulse response of R XX (τ ) = σ x2δ (τ )
S XX ( f ) = σ x2 , as Figure 16
(17)
P0
P0 – average power of
sequence
-Tb
Tb
τ
Figure 14: AutoCorrelation function of Pseudo random sequence
19
2
x
τ
Figure 15: AutoCorrelation function of Pseudo random bits with long sequence
Power Spectrum
σ x2
S xx ( f ) = σ x
2
Figure 16: Power spectrum of pseudo random bits with long sequence
By using additive White Gaussian Pseudo Random Sequence as the inputs,
RYX (τ ) = E[Y (t ) X (t − τ )]
∞
= E[ h(λ ) X (t − λ )dλ X (t − τ )]
(18)
−∞
By putting the expectation operator within the integral, the cross correlation function
obtained is
∞
RYX (τ ) = h(λ ) E[ X (t − λ ) X * (t − τ )dλ ]
(19)
−∞
Since X(t) is stationary random process, the autocorrelation of X(t) derived by making the
substitution t1=τ-λ is
20
E[ X (t1 ) X * (t1 − (τ − λ ))] = RXX (τ − λ )
(20)
∞
RYX (τ ) = h(λ ) RXX (τ − λ )dλ
−∞
= h(τ ) * RXX (τ )
(21)
The cross power spectrum is
SYX ( f ) =
∞
RYX (τ ) exp(− j 2πfτ )dτ
(22)
−∞
S YX ( f ) =
∞ ∞
h(λ ) R XX (τ − λ ) exp(− j 2πfτ )dλdτ
− ∞− ∞
= H ( f ) S XX ( f )
= H ( f )σ x2
(23)
It shows that no special encoding training needed for correlation function
characterization. The natural transmitting behavior of the data packet itself is the inputs to
this method thus the channel characterization can be done when the application is running
thus reducing the overheads. It also allows the channel characterization be more robust
because it does not depend to the rising edge and the pulse period too much.
3.4. Crosstalk, power noise and jitter noise
Correlation function characterization also provides better noise immunity. Besides
channel loss, crosstalk interference can be severe enough to ruin the signal as Figure 17
illustrates two common forms of crosstalk that arise in the system interconnect. The term
“far-end crosstalk” (FEXT) is used to describe interference from an aggressor signal
being transmitted as the victim signal. The term “near-end crosstalk” (NEXT) is used to
describe the interference from an aggressor transmitted at the receiver end of the victim
channel. NEXT impairment is more severe than FEXT because the aggressor interference
21
corrupts the victim signal after it has been attenuated on the backplane channel, when it is
most vulnerable10.
Figure 17: FEXT and NEXT11
Instead of NEXT and FEXT, there’s jitter noise presented in the system as
illustrate in Figure 1812 . There’s two type of jitter noise presented: deterministic jitter
and non-deterministic jitter noise.
10
Cattalen Pelard, Edward Gebara, Andrew J. Kim, Michael G. Vrazel, Franklin Bien, Youngsik Hur,
Moonkyun Maeng, Soumya Chandramouli, Carl Chun, Sanjay Bajekal, Stephen E. Ralph, Bruce
Schmukler, Vincent M. Hietala,, “Realization of Multigigabit Channel Equalization and Crosstalk
Cancellation Integrated Circuits”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 10,
OCTOBER 2004
11
Maynard Falconer, “Bus Design Boot Camp”, Chapter 3, Intel Corp, 2005
12
Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei and Un-Ku Moon, “JITTER IN
HIGH-SPEED SERIAL AND PARALLEL LINKS” , ISCAS 2004
22
Figure 18: The presence of power noise behaves as periodic noise
13
Deterministic jitter is introduced from a variety of systematic effects, which
include duty-cycle distortion (DCD), inter-symbol interference (ISI), sinusoidal or
periodic jitter (PJ), and crosstalk. DCD results from asymmetries in clock like signals, for
example, differences in rise and fall times. IS1 results from dispersions of signals due to
attenuation and reflections. PJ results from coupling from other periodic sources in the
system, for example, power supply modulation. Crosstalk is due to the switching of
signals from neighboring signals. Transmitter, receiver, and passive channel all
contribute to DJ. However, passive channel typically contributes only to DJ due to IS1
and crosstalk. At lower speed, DJ dominates the contribution of the total jitter of the
system. One of the unique features of DJ is that it can be represented by its peak-to-peak
value which is bounded, or finite.
On the other hand, Random Jitter is the result of accumulation of random
processes including thermal noise, shot noise, and flicker noise. The thermal noise results
from resistors and transistors which is proportional to temperature. Shot noise is the
granular nature of the electronic charge which is proportional to DC current of the device.
13
Chris Madden, Kyung Suk Oh, Xingchao Yuan “System Level Deterministic and Random Jitter
Measurement and Extraction for Multi-gigahertz Memory Buses”, EPEP 2004
23
The flicker noise results from resistors and transistors which is proportional to inverse of
frequency.
As result, the passive channel is not a source of RJ, only transmitters and receivers
are. In contrast to DJ, RJ can be represented by a Gaussian distribution which is
characterized by its standard deviation. Note that RJ is unbounded. In the absence of
deterministic jitter, RJ determines the position of an edge. The probability that the edge
crosses the sampling point, causing a bit error, follows a complimentary error function
distribution. At lower data rates, RJ is typically much smaller than DJ, so it is often
ignored. However, this is no longer the case at multi-gigabit data rates.
Figure 19: Jitter measurement shows Gaussian PDF (courtesy from Erfen Matoglu, Nam
Pham, Daniel N. de Araujo, Madhavan Swarninathan, “Statistical Signal Integrity
Analysis and Diagnosis Methodology for High-Speed Systems”, IEEE Transaction on
Advanced Packaging 2004)
24
Figure 20: The presence of jitter noise in the channel
3.5. Electrical Modeling of Platform Bus Interconnect
There are some complex components on the motherboard require detail modeling
such as package, breakout motherboard trace, vias, motherboard trace and connector.
Package itself is broken into a few components because of its short electrical length. Due
to the complexity level in the package, each package interconnect segment is required to
be modeled in 2D or 3D models. Package electrical modeling methodology used in GHz
I/O device modeling in more robust and accurate way to support high volume
manufacturing and signal integrity design is discussed. Each package interconnect is
simulated using appropriate simulation tools. The package wirebond, via & ball are
modeled with physical dimensions using AnsoftLink™, Ansoft Q3D Extractor®. The
package traces and plating bars are modeled using Ansoft Q2D to obtain RLGC model of
the transmission line. AnsoftLink™ is a tool used to extract 3D model with actual
dimension from package layout. The same 3D model is then imported, modeled and
analyzed in Ansoft Q3D to generate parasitic RLC values. Figure 21 & 22 are showing
the package models from Q3D and Q2D simulation tools.
25
Figure 21: Physical dimension of Q3D package model (wirebond, via model).
Figure 22: Q2D trace and plating bar model. Cross sectional view.
26
In order to study the package SI property, Ansoft Q3D and Q2D models are
exported into HSPICE readable file format or any other appropriate SPICE simulation
tools. The Figure 23 shows package interconnects.
Figure 23: Signal paths in a package model
For motherboard modeling itself, they are broken into breakout region, trace and
connector as Figure 24. Breakout and motherboard trace are modeled using Q2D.
connector are modeled as Q3D.
Figure 24: Breakout and trace routing (Courtesy of Intel)
27
Finally, every component from package to the motherboard is hooked up to build
a data bus system. The system can be modeled in black box model using S-parameter
matrix or other behavior form.
Figure 25: Full EM Modeling Platform Data Bus topology system
Figure 26: Black box modeling of Platform Data Bus system
28
CHAPTER 4
METHODOLOGY
4. Methodology
4.1. Phase 1: Transmission Bus Channel Characterization
4.1.1. Device Modeling and Circuit Setup
Active bus channel characterization needs simulation to prove the concept. Due to
potential risk of hardware readiness, the study focuses on software simulation. The
passive elements from the transmission bus channel including package, printed circuit
board routing, connector and cable are modeled in RLC SPICE format using
electromagnetic simulator tool. Ansoft® Maxwell Q2D and Q3D. The simulator captures
electromagnetic behavior and then transforms to RLC matrix elements. Transmission line
such as cables and traces are modeled using Q2D assuming energy flows to one direction
while Q3D is used for 3D structure such as punch-through-via as Figure 27 and Figure 28.
29
Figure 27: Q2D of printed a circuit board trace line models
Figure 28: 3D object electromagnetic analysis of an IC package structure
Every component is modeled in RLC or Scattering parameters matrix. Then they
are hook up to build circuit netlist as Figure 29.
I/O -
I/O
Package
Package
+
-
+
+
-
RX
+
- TX
+
-
+
TX
AC
Connector RX
Cap
Coupling
PCB
Figure 29: Intel® SPICE simulator is chosen because it is easily to be linked up to the
PCB
Connector
RX
Intel® Process Technology Library
30
. Intel Process library provides precise modeling to the transistor attributes used
for transmitting and receiving signals.
4.1.2. Comparison of Scattering parameters, impulse response and
correlation method
For scattering parameters analysis, the active component, transistor is removed
from the circuit netlist and swept over the interested frequency. The result is in S21
frequency domain.
For impulse response, 1 bit is sent from the transmitter to the receiver. The output
measured at receiver end point is the impulse response of the transmission bus channel.
High Speed I/O uses 8bit/10bits encoding scheme for data packet transmitting. A
pseudo random bit generator can be used to mimic this encoding scheme. The bit pattern
is desired to be long enough so that it can capture the worst case scenario but the length is
further optimized due to the long simulation time.
The waveforms at the transmitter start point and receiver end point are capture as
inputs, x(t) and output, y(t). These data are imported into MATLAB for correlation
function. The results are compared against Scattering parameters and impulse response
characterization.
4.2. Phase 2: Immunity to the noise
The comparison between Scattering parameters, impulse response and correlation
method over noisy environment is desired to understand their robustness. There are 3
major noise sources: crosstalk, power noise and jitter noise.
FEXT and NEXT have been discussed at the previous chapter where NEXT has
the dominant contribution. The crosstalk environment can be set by introducing 2
adjacent transmission bus channels operating at normal mode.
31
Power noise is instability of the Vcc power rails due to the passive components. It
is a deterministic noise as it behaves like a periodic noise. It can be set by injecting power
noise to the Vcc of the transistor circuit netlist at both transmitter and receiver.
Jitter noise is non- deterministic noise source as it behaves like a White Gaussian.
It is injected at transmitter.
4.3. Phase 3: Measurement in the lab
The phase 3 method depends on the readiness of the hardware and is a backup
plan. It depends on the probe point availability for transmitter start point and receiver end
point on the test chip.
The S-parameters is taken using Vector Network Analyzer (VNA) from
transmission line start point and end point when the channel does not operate. VNA
cannot be used for active measurement as discussed in the previous chapter.
For impulse response measurement, the bit pattern is sent out with long idle bit
pattern followed with a bit transition then back to idle bit pattern again. The readiness of
the bit pattern really depends on the post silicon validation team to enable it.
Correlation method can be done by operating the channel in normal mode then
measure the transmitter start point and receiver end point.
32
Electromagnetic modeling of transmission bus
channel components and circuit netlist setup
Phase 1
Intel® SPICE
simulates
Frequency domain
response, S21 (f)
Intel® SPICE
simulates impulse
response and
MATLAB post
processing
Result
comparison
Intel® SPICE
simulates
correlation method
and MATLAB post
processing
No
Phase 2
Simulation with
crosstalk noise
Simulation with
power noise
Simulation with
jitter noise
No
Result and
conclusion
Phase 3
Measurement of Sparameter using
VNA
Hardware
Readiness
Measurement of signal
response in normal
mode and MATLAB
post processing
Result
comparison
No
End
Measurement of signal
response using 1 bit
toggle pattern and
MATLAB post processing
No
End
33
Figure 30: Methodology flow chart
Figure 31: Schedule and plan
34
CHAPTER 5
RESULT
5. Result
5.1. Noise Free Environment
5.1.1. Proof of concept
Proof of concept is important to realize the correlation method implementation. A
study of h(t) was done using both impulse response and correlation method. The
comparison between Figure 32, 33 and Figure 34 showed that the outputs from these 2
methods were close.
35
Figure 32: Impulse response and power spectrum
Figure 33: Autocorrelation method response
36
Figure 34: Power spectrum of correlation method
With the presence of noise, the impulse response corrupted. On the other hand,
correlation method still achieved its behavior as Figure 35 and Figure 36.
Figure 35: impulse response with 1/16 white Gaussian noise at transmitter
37
Figure 36: Auto correlation response and Rxy with 1/16 power noise at transmitter
Figure 37: Auto correlation response and power spectrum with 1/16 power noise at
transmitter
5.1.2. Determination of correlation parameters
38
Once the concept is proven, more detail works were carried out to understand the
parameters of the algorithm, including sample size and Fourier Transform technique.
The input data was random pulse train signal. Data sample size started from 100, 1,000
and 10,000 samples to study the sensitivity of the Rxy.
Figure 38: 100 sample size h(t) looks noisy
Correlation method using 100 data sample size didn’t convincing due to the noisy
h(t). The sample size was increased to 1000 samples.
39
Figure 39: 1000 samples h(t) looks much better than 100 points but the power spectrum
still looks noisy
5.1.3. Windowing Technique
By using 1,000 bit samples, the h(t) has less noise 100 points. However, the
frequency domain analysis, Sxy was still noisy. 50 data point at n/2 were removed to
understand the reason behind it. It was found that Rxy contains random noise across the
time.
40
Figure 40: Residue of the Rxx is noisy
In order to tackle the existing noise in the Rxy, level triggered method is used to
extract out the useful information which is above the triggered level. The data points
below the triggered level are filtered. The result as shown in Figure 42 from this method
removes the random noise successfully in Sxy. However, it is difficult to determine
which triggered level to be used. H(t) data will be removed if the it is lower than the
noise.
Figure 41: using 1000 as triggered signal
41
Figure 42: Sxy looks much cleaner
Despite level triggered method, Window technique was proposed to characterize
the Sxy spectrum. 3 Window technique, Periodogram, Welch and Blackman Tukey
windows were used and compared with insertion loss, S21.
Comparing the power spectrum density between Welch and Periodogram, Welch
produced less noise power spectrum density. It wasclearly showing that Welch better
than Periodogram. However, comparing Welch power density method with insertion loss,
S21, they don’t correlate well.
Using Blackman Tukey window, although it had more noise compared to Welch
Window, but the output hasd better correlation with S21. Thus, Blackman Tukey was
chosen as the window.
42
Figure 43: upper left- filtered noise Rxy, upper right- Welch, lower left- FFT only, lower
right- periodogram
43
Figure 44: Comparison between Power Spectrum Density and S21
Figure 45: 10,000 samples ensures good h(t)
44
Figure 46: Blackman turkey method with 10,000 samples reduces the noise in power
spectrum
The result showed 10,000 sample sizes and Blackman Turkey Window giving the
best result in Rxy and Sxy. The further analysis continued using this parameter and
windowing technique.
5.1.4. Simulation using simple transmission line
Cross correlation method was used by using simple transmission line model.
Impulse response analysis was used as the bench mark for comparison.
Figure 47: HSPICE impulse response analysis
45
Using impulse response analysis, the overshoot amplitude is 0.784 and the delay
time is 3.4ns. Comparing with correlation method using 10,000 samples, the overshoot is
0.761, which is close to the impulse response analysis. Both of them have same delay
time, 3.4ns, and very similar waveform shape. Thus it wasconcluded that correlation
method using 10,000 sample data producing convincing h(t) .
Figure 48: result from Rxy by running 10,000 sample random data
The correlation method was also tested under noisy environment. By injecting a
random uniform 10% noise and 10% DC gain. The result still capture h(t) oveshoot,
delay time and waveform shape accurately. The difference is the DC gain observed in the
46
new waveform. Correlation method is proven effective under noisy environment.
Figure 49: uniform 10% random noise
5.1.5. Simulation using complex full EM modeling platform data bus
topology
The correlation method is applied on complicated data bus system as shown in Figure
25. Impulse response analysis is used as the bench mark for comparison. Using impulse
response analysis, the overshoot amplitude is 0.64 and the delay time is 1.1ns. Comparing
with correlation method using 10,000 samples, the overshoot is 0.553, which is close to
the impulse response analysis. Both of them have same delay time, 1.1ns, and very
similar waveform shape as shown in Figure 50. Thus it is concluded that correlation
method using 10,000 sample data produce convincing h(t) .
47
Figure 50: Comparison between impulse response and correlation method on
complicated data bus
By using Blackman Tukey Window, the power spectrum, Sxy wasround 1dB/GHz while S21, the result is -0.875dB/ GHz. They are closed inside 4GHz frequency
band although not as close as h(t). Thus it wasconcluded that correlation method
producing Sxy but the accuracy is needed to be improved by using better Window
technique.
48
Figure 51: comparison between Sxy and S21
5.2. Immunity over random noise, periodic noise and jitter
The correlation method is also tested under noisy environment. By injecting a
distributed random uniform 10% noise, the result still capture h(t) oveshoot, delay time
and waveform shape accurately. The Sxy also doesn’t make difference.
By injecting a 2GHz periodic 10% noise, the result still capture h(t) oveshoot, delay time
and waveform shape accurately. The Sxy also doesn’t make difference.
By injecting 50ps jitter, the result still capture h(t) oveshoot, delay time and
waveform shape accurately although not as accurate as random and periodic noise. The
Sxy also bring minor difference.
Figure 52: Injecting 10% distributed random noise
49
Figure 53: Injecting 10% 2GHz periodic noise
Figure 54: injecting 50% normal distributed random jitter
5.3. Measurement data
The Phase 3 is not completed. There are difficulties in laboratory resource. No
data is available at this moment yet.
50
CHAPTER 6
CONCLUSION AND RECOMMENDATION
From the result from Chapter4, correlation method was concept proven by using a
16 bit h(t) FIR as h(t). The robustness was proven with monor change after tested under
1/16 random noise.
100, 1,000 and 10,000 samples test case was built to study the sensitivity of the
sampling number. 10,000 sample data produced the best result because the Rxy can be
found with least noise. In Sxy, random noise was observed through out the power
spectrum. 3 window technique: Periodogram, Welch and Blackman Tukey were used to
remove the excessive noise. Blackman Tukey appeared to the best Window technique
because the result is closer to the insertion loss, S21.
The algorithm was used on the output of simple transmission line SPICE
simulation. The result correlated with the benchmark impulse response analysis. By
simulating the model under 10% random noise, the result have very minor difference
compared to noise free simulation. The algorithm is once again proven to be robust.
The algorithm was once again applied on HSPICE full EM modeling platform
data bus transmission topology system where it can represent actual motherboard system.
The Rxy result correlated with h(t) from impulse response. The Sxy is close to insertion
loss, S21 but not as close as h(t). It is due to the Windowing technique where Blackman
Tukey still producing noise over power spectrum. It is suggested to explore better
Windowing technique for more accurate result.
51
The algorithm was tested under noisy environment. It was proven to be very
robust with almost no difference using 10% distributed random noise and periodic noise.
It was suggested to increase the noise level and varying frequency range. With the
presence of 50% jitter, the Rxy and Sxy result is still close but not as close as 10% noise.
50% might be too pessimistic and not realistic.
Measurement data on the motherboard is not available at this moment due to
laboratory resource difficulties. In short, cross correlation algorithm is proven to be
effective and robust in concise SPICE simulation.
52
REFERENCE
1. John D. Carpinelli, “Computer System Organization and Architecture”, Chapter 4,
page 141, Addison Wesley, 2001
2. Maynard Falconer, “Bus Design Boot Camp”, Chapter 1, Intel Corp, 2005
3. Maynard Falconer, “Bus Design Boot Camp”, Chapter 8, Intel Corp, 2005
4. Adam Norman, “Chapter 13: Peak Distortion analysis” Bus Design Boot camp,
3/3/05
5. M. Cases, D. N. de Araujo, E. Matoglu, “Electrical Design and Specification
Challenges for High Speed Serial Links”, 2005 Electronics Packaging
Technology Conference
6. Hewlett Packard, “S-parameters Technique”, Test and Measurement Application
Notes 95-1
7. Lennar Lyung, Torkel Glad, “Modeling of Dynamic Systems” , chapter 8, page
191-199, Prentice Hall, 1994
8. Howard Johnson, “High-Speed Signal Propagation”, Prentice Hall, 2003
9. B. Casper, M. Haycock, R. Mooney, “An Accurate and Efficient Analysis Method
for Multi-Gb/sChip-to-Chip Signaling Schemes,”Symposium on VLSI Circuits
Digest of Technical Papers, 2002, pp. 54-57, June 13-15, 2002
10. Cattalen Pelard, Edward Gebara, Andrew J. Kim, Michael G. Vrazel, Franklin
Bien, Youngsik Hur, Moonkyun Maeng, Soumya Chandramouli, Carl Chun,
Sanjay Bajekal, Stephen E. Ralph, Bruce Schmukler, Vincent M. Hietala,,
“Realization of Multigigabit Channel Equalization and Crosstalk Cancellation
Integrated Circuits”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39,
NO. 10, OCTOBER 2004
53
11. Maynard Falconer, “Bus Design Boot Camp”, Chapter 3, Intel Corp, 2005
12. Pavan Kumar Hanumolu, Bryan Casper, Randy Mooney, Gu-Yeon Wei and UnKu Moon, “JITTER IN HIGH-SPEED SERIAL AND PARALLEL LINKS” ,
ISCAS 2004
13. Chris Madden, Kyung Suk Oh, Xingchao Yuan “System Level Deterministic and
Random Jitter Measurement and Extraction for Multi-gigahertz Memory Buses”,
EPEP 2004
14. Ahmad Zuri, “Advance DSP Chapter 6: Optimum Filtering”, UTM
15. Peyton Z. Peebles, Jr, “Probability, Random Variables and Random Signal
Principles”, McGraw-Hill, 2001 International Edition
16. L. Couch, Digital and Analog Communication Systems, MacMillanPublishing
Company, 1987, 2ndedition
17. Edward w. Kamen, Bonnie S. Heck, “Fundamental of Signals and System”,
Prentice Hall, 1997
18. Behzad Razavi, “Design of Analog CMOS integrated circuit”, McGrah-Hill, 2001
international edition
19. Philip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design”, Oxford
2002
20. Rafael C. Gonzalez, Richard E. Woods, Steven L. Eddins, “Digital Image
Processing using Matlab”, chapter 5, Pearson Education, 2004
21. P.A. Nelson, S.J. Elliot, “Active Control of Sound”, Academic Press, 2000
22. Erfen Matoglu, Nam Pham, Daniel N. de Araujo, Madhavan Swarninathan,
“Statistical Signal Integrity Analysis and Diagnosis Methodology for High-Speed
Systems”, IEEE Transaction on Advanced Packaging 2004
23. Yew Teong Guan, “SIE Overview”, Intel Corp Penang Design Center, April 2005
24. Jimmy Huang Huat Since, Lee Chan Kim, Kuan Chin Lee, “Signal Integrity
Analysis and Validation of GHz I/O Interface on Wire Bond Ball Grid Array
Technology Package”, Electronic Manucfacturing Assembly Proceeding, 2006
54
APPENDIX A
1.
Proof of Correlation Concept Using Digital Filter
s=rand_seq1(10000);
x=pulse(8,1,s);
h=[1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1/2 0 0 0];
y=filter(h,1,x);
[ryx, syx]=corr_power_spec_edit(x,y);
N=size(ryx);
N=N(1,2);
%for k=1:N
% if ryx(k)>1500
%
sig(k)=ryx(k);
%
n(k)=0;
%else
% sig(k)=0;
% n(k)=ryx(k);
%end
2.
Correlation Method
function [rxy, sxy]=corr_power_spec_edit(x,y)
num_x=length(x);
rxy=xcorr(y,x);
sxy=abs(fft(rxy));
num_rxy=length(rxy);
subplot(211),plot((1:num_x)-1,x(1:num_x));grid;xlabel('Signal
x');axis([0 num_x -1.5 1.5]);
subplot(212),plot((1:num_x)-1,y(1:num_x));grid;xlabel('Signal
y');axis([0 num_x -2.5 2.5]);
figure;
subplot(211),plot((1:num_rxy)1,rxy(1:num_rxy));grid;xlabel('Correlation Rxy');
subplot(212),plot((1:round(num_rxy/2))1,sxy(1:round(num_rxy/2)));grid;xlabel('Power Spectrum Sxy');
3.
Random Number Generator
function x=rand_seq1(npack)
x0=rand(1,npack);
for k=1:npack
if x0(k)>0.5
x(k)=1;
else
x(k)=0;
end
end
55
4.
Automated Script for for Rxy and Sxy
function [rxy, rxx, sxy, sxx]= s21xcorr1p3(a1,a2,b,c)
%[ryx, rxx, syx, sxx]= s21xcorr1p3('Input.txt','Output.txt',steptime,
window integer)
% Customize for Cougar
x=textread(a1);
y=textread(a2);
fmax=1/b;
rxy=xcorr(y,x);
rxx=xcorr(x,x);
num_x=length(x);
num_y=length(y);
num_rxx=length(rxx);
num_rxy=length(rxy);
mid2=round(num_rxy/2);
mid1=mid2-c/2;
mid3=mid2+c/2;
n=max(rxx);
rxy=rxy/n;
rxx=rxx/n;
rxy1=rxy(mid1:mid3);
sxy=fft(rxy1);
sxx=fft(rxx);
magsxy=(10*log10(abs(sxy)));
magsxy=magsxy-10;
magsxx=(10*log10(abs(sxx)));
phasesxy=angle(sxy);
phasesxx=angle(sxx);
num_rxy1=length(rxy1);
figure;
subplot(311),plot((1:num_rxy)1,rxy(1:num_rxy));grid;xlabel('Correlation Rxy');
subplot(312),plot(((1:round(num_rxy1/2))1)*fmax/num_rxy1,magsxy(1:round(num_rxy1/2)));grid;xlabel('Power
Spectrum Sxy (Hz)');
subplot(313),plot(((1:round(num_rxy1/2))1)*fmax/num_rxy1,phasesxy(1:round(num_rxy1/2)));grid;xlabel('Power
Spectrum Sxy Phase (Hz)');
figure;
subplot(311),plot((1:num_rxx)1,rxx(1:num_rxx));grid;xlabel('Correlation Rxx');
subplot(312),plot(((1:round(num_rxx/2))-1)*fmax/num_rxx,
magsxx(1:round(num_rxx/2)));grid;xlabel('Power Spectrum Sxx (Hz)');
subplot(313),plot(((1:round(num_rxx/2))1)*fmax/num_rxx,phasesxx(1:round(num_rxx/2)));grid;xlabel('Power
Spectrum Sxx Phase (Hz)');
56