vii
TABLE OF CONTENTS
CHAPTER
TITLE
DECLARATION
ii
DEDICATION
iii
ACKNOLEDGEMENT
iv
ABSTRACT
v
ABSTRAK
vi
TABLE OF CONTENTS
vii
LIST OF TABLES
xi
LIST OF FIGURES
xii
LIST OF ABBREVIATIONS
xv
LIST OF APPENDICES
CHAPTER 1
PAGE
xvi
INTRODUCTION
1.1
Overview and Problem Statement
1
1.2
Objectives
3
1.3
Scope of Work
4
1.4
Project Contributions
5
1.5
Thesis Outline
6
viii
CHAPTER 2
BACKGROUND AND THEORY
2.1
An Overview of Serial Communication
7
2.2
UART
8
2.3
BIST – An Overview
10
2.3.1
BIST Process
10
2.3.2
BIST Implementation
11
2.3.3
BIST Pattern Generation
13
2.3.3.1 Standard LFSR
14
2.3.4
BIST Response Compaction
16
2.3.5
Built-In Logic Block Observers
18
CHAPTER 3
METHODOLOGY AND DESIGN TOOLS
3.1
Project Design and Implementation Flow
22
3.2
Verilog HDL
28
3.3
Mentor Graphics Modelsim v6.1
29
3.4
FPGA Synthesis
31
3.5
Altera Quartus II 6.1
32
3.6
Modelsim-Altera v6.1g Web Edition
34
CHAPTER 4
I/O PROCESSOR CORE DESIGN
4.1
IOP – An Overview
36
4.2
IOP Architecture
38
4.3
Message Format
41
4.4
IOP Operation
43
ix
CHAPTER 5
DESIGN OF IOP WITH EMBEDDED
BIST CAPABILITY
5.1
Top Level Architecture
44
5.2
BIST Module
51
5.2.1 BIST DPU Module
5.2.1.1
Command Select Mux
57
5.2.1.2
Functional Block
58
5.2.1.3
BILBO
60
5.2.1.4
Decoder Block
65
5.2.1.5
Command Decoder
67
5.2.1.6
NextCmd Select
68
5.2.2 BIST CU Module
5.3
IOP BIST Operation
CHAPTER 6
54
69
83
SIMULATION, VERIFICATION AND
RESULTS ANALYSIS
6.1
Verilog HDL Code Efficiency Gain
90
6.2
Design Compilation, Synthesis and Timing Analysis
92
6.2.1 Design Synthesis and Analysis
92
6.2.2 Fitter and Assembler
94
6.2.3 Design Timing Analysis
95
6.3
Design Test bench
98
6.4
IOP Simulations and Discussion
100
6.4.1 Functional Mode
100
6.4.2 BIST Mode
108
6.4.2.1
Fault Free Circuit Simulation
109
6.4.2.2
Faulty Circuit Simulation
113
x
CHAPTER 7
CONCLUSION AND FUTURE WORK
7.1
Conclusion
116
7.2
Recommendation for Future Works
117
LIST OF REFERENCES
APENDIX A-B
120
122-192
xi
LIST OF TABLES
TABLE NO
TITLE
PAGE
Table 2.1
Control modes for the BILBO of figure 2.6
19
Table 4.1 (a)
Table of Control Bytes
41
Table 4.1 (b)
Table of Command Bytes
42
Table 5.1
BIST module Input, Output and Internal signal
53
Table 5.2
BIST DPU Input, Output signal
56
Table 5.3
Command Select Mux output table
58
Table 5.4
BILBO block in BIST DPU operation mode
60
Table 5.5
Input and output signals for BIST CU module
70
Table 5.6
BIST CU RTL control sequences table
82
Table 6.1
Verilog HDL migration code efficiency gain
91
Table 6.2
Analysis and Synthesis - IOP Resource
94
Usage Summary
Table 6.3
Summary of IOP timing analysis
96
xii
LIST OF FIGURES
FIGURE NO
TITLE
PAGE
Figure 2.1
UART data frames format
9
Figure 2.2
BIST hierarchy
11
Figure 2.3
BIST architecture
12
Figure 2.4
Standard n-stage LFSR circuit
14
Figure 2.5
Multiple input signature register
18
Figure 2.6
BILBO circuit
19
Figure 2.7
BILBO in serial scan mode
19
Figure 2.8
BILBO in LFSR mode
20
Figure 2.9
BILBO in normal D flip-flop mode
20
Figure 2.10
BILBO in MISR mode
21
Figure 3.1
Project design flow
23
Figure 3.2
Multiple abstractions for digital system design
24
Figure 3.3
Digital design flow
25
Figure 3.4
Project design and implementation flow
27
Figure 3.5
General structure of an FPGA
31
Figure 3.6
Quartus II design flow
33
Figure 4.1
Overall System Architecture of PC-based Design
37
and Test System for digital design in FPGA
Figure 4.2
IOP Architecture
40
Figure 4.3
Data Packet Format
41
Figure 5.1
IOP block diagram with embedded BIST
45
xiii
Figure 5.2
IOP design with embedded BIST
46
capability architecture
Figure 5.3
IOP with embedded BIST Design Hierarchy
47
Figure 5.4
High level BIST operation flow
48
Figure 5.5
BIST module block diagram
52
Figure 5.6
BIST DPU module block diagram
55
Figure 5.7
Command Select Mux block diagram
57
Figure 5.8
Functional Block diagram
59
Figure 5.9
BILBO circuit
61
Figure 5.10
BILBO LFSR block diagram
62
Figure 5.11
BILBO LFSR mode operation waveform
62
Figure 5.12
BILBO scan mode operation waveform
63
Figure 5.13
BILBO D flip-flop mode operation waveform
63
Figure 5.14
BILBO MISR block diagram
64
Figure 5.15
BILBO D MISR mode operation waveform
65
Figure 5.16
Decoder Block diagram
66
Figure 5.17
Command Decoder block diagram
68
Figure 5.18
NextCmd Select block diagram
68
Figure 5.19
BIST CU block diagram
69
Figure 5.20
BIST CU RTL Code
71
Figure 5.21
IOP BIST operation flow chart
84
Figure 6.1
Full compilation of the design by Quartus II
97
Figure 6.2
Design test bench
99
Figure 6.3
Waveform for functional mode simulation 1 result
101
Figure 6.4
Waveform for functional mode simulation 2 result 103
Figure 6.5
Waveform for functional mode simulation 3 result
105
Figure 6.6
Waveform for functional mode simulation 4 result
106
Figure 6.7
Waveform for functional mode simulation 5 result
108
Figure 6.8
Simulation waveform 1 for fault free IOP
110
in BIST mode
Figure 6.9
Simulation waveform 2 for fault free IOP
in BIST mode
112
xiv
Figure 6.10
Simulation waveform 3 for fault free IOP
113
in BIST mode
Figure 6.11
Simulation waveform 1 for faulty IOP
114
in BIST mode
Figure 6.12
Simulation waveform 2 for faulty IOP
in BIST mode
115
xv
LIST OF ABBREVIATIONS
ASIC
-
Applications Specific Integrated Circuit
ATPG
-
Automatic Test-Pattern Generation
BILBO
-
Built-In Logic Block Observers
BIST
-
Built-In-Self-Test
CAD
-
Computer Aided Design
CU
-
Control Unit
CUT
-
Circuit Under Test
DPU
-
Data Path Unit
DUT
-
Design Under Test
FES
-
Front End Subsystem
FPGA
-
Field Programmable Gate Array
HDL
-
Hardware Description Language
IC
-
Integrated Circuit
IP
-
intellectual property
LFSR
-
Linear Feedback Shift Register
LSB
-
Least Significant Bit
MISR
-
Multiple Input Signature Register
I/O
-
Input/Output
PC
-
Personal Computer
ROM
-
Read-Only-Memory
RTL
-
Register Transfer Level
UART
-
Universal Asynchronous Receiver/Transmitter
SDF
-
Standard Delay Format
XOR
-
Excusive OR
xvi
LIST OF APPENDIXS
APPENDIX
TITLE
PAGE
APPENDIX A - Module Block Diagram and Verilog HDL Code
A1
Block diagram and VHDL code for Testbench module
122
A2
Block diagram and Verilog HDL code for IOP module
126
A3
Block diagram and Verilog HDL code for clk_1mhz module
128
A4
Block diagram and Verilog HDL code for bist module
129
A5
Block diagram and Verilog HDL code for bis_cu module
131
A6
Block diagram and Verilog HDL code for bis_dpu module
139
A7
Block diagram and Verilog HDL code for bilbo module
146
A8
Block diagram and Verilog HDL code for DFFlop module
148
A9
Block diagram and Verilog HDL code for IOP_CU module
148
A10
Block diagram and Verilog HDL code for IOP_DPU module
158
A11
Block diagram and Verilog HDL code
159
for IO_Interface module
A12
Verilog HDL code for Interface module
160
A13
Block diagram and Verilog HDL code for Buffers module
161
A14
Verilog HDL code for Register module
163
A15
Verilog HDL code for T_output_reg module
164
A16
Block diagram and Verilog HDL code for Input_card module
164
A17
Verilog HDL code for Trans_comparator module
166
xvii
A18
Verilog HDL code for Counter module
167
A19
Block diagram and Verilog HDL code for Output_card module
167
A20
Verilog HDL code for Poll_comparator module
169
A21
Block diagram and Verilog HDL code for UART module
170
A22
Block diagram and Verilog HDL code for C_transmit module
170
A23
Block diagram and Verilog HDL code for C_receive module
173
A24
Block diagram and Verilog HDL code for Status_reg module
175
A25
Block diagram and Verilog HDL code for UART_Comm module
176
A26
Verilog HDL code for Clock_generator module
177
A27
Block diagram and Verilog HDL code for
178
UART_Receiver module
A28
Verilog HDL code for Receiver_CU module
179
A29
Block diagram and Verilog HDL code
182
for Receiver_DPU module
A30
Verilog HDL code for Bit_counter1 module
183
A31
Verilog HDL code for Rcv_shftreg module
183
A32
Verilog HDL code for Sample_counter module
184
A33
Block diagram and Verilog HDL code
184
for UART_Transmitter module
A34
Block diagram and Verilog HDL code
185
for Transmitter_CU module
A35
Block diagram and Verilog HDL code
187
for Transmitter_DPU module
A36
Verilog HDL code for Datareg module
188
A37
Verilog HDL code for Bit_counter module
189
A38
Verilog HDL code for Shftreg module
190
APPENDIX B
B1
VHDL to Verilog HDL Conversion Table
191