Feedback In
In SRRC
SRRC
Global Orbit Feedback
Jenny Chen,
Chen, K.
K. H.
H. Hu,
Hu, K.
K. T.
T. Hsu
Hsu
C. H. Kuo, Jenny
Synchrotron
Synchrotron Radiation
RadiationResearch
ResearchCenter
Center
No. 11 R&DRoad
R&D Road VI,
Hsinchu Science-Based
No.
VI, Hsinchu
Science-Based Industrial
IndustrialPark,
Park,Hsinchu
Hsinchu 30077,
30077,Taiwan,
Taiwan,R.O.C.
R.O.C.
Abstract. The
The global
Abstract.
global orbit
orbit feedback
feedback system
system plays
plays aa critical
critical role
role inin the
the operation
operation ofofthe
thethird
third
generation light
light source
generation
source in
in SRRC.
SRRC. This
This article
article addresses
addresses various
variousissues
issuesconcerning
concerningthe
theorbit
orbitfeedback
feedback
system to
to optimize
optimize performance.
performance. The
system
The orbit
orbit feedback
feedback system
system has
has been
been recently
recentlyupgraded
upgradedtotomeet
meettoto
user demands.
demands. Following
Following upon
user
upon operational
operational experiences
experiences in
in recent
recent years,
years, SRRC
SRRChas
hasdesigned
designedaanew
new
system to
to be
be more
more easily
system
easily maintained,
maintained, with
with aa better
better diagnostic
diagnostic environment,
environment,robustness
robustnessand
andflexibility
flexibility
controller. The
The new
controller.
new hardware
hardware structure
structure isis based
based on
onaageneral
generalpurpose
purposeCPU
CPUwith
withaareal-time
real-timeoperation
operation
system to
to reduce
reduce the
the upgrade
upgrade time
system
time and
and the
the investment.
investment. Performance
Performanceanalysis
analysistools
toolsare
arealso
alsodeveloped
developed
to monitor
monitor the
the system
to
system and
and analyze
analyze data.
data. Commercial
Commercial Off-The
Off-The Shelf
Shelf (COTS)
(COTS)products,
products, supporting
supporting
effective integration,
integration, are
effective
are applied
applied to
to support
support various
various beam
beamstudies
studiesand
andaccesses.
accesses.
INTRODUCTION
INTRODUCTION
PID parameter
[yref]
Mx1
+
[∆y]Mx1
-
Response Matrix
G
[R]-1NxM
Storage Ring
[y]
BPM
Mx1
Data Acquisition System
FIGURE 1. Basic concept of the orbit feedback system.
FIGURE 1. Basic concept of the orbit feedback system.
The orbit feedback system eliminates orbit irregularities that are caused by
The orbit feedback system eliminates orbit irregularities that are caused by
perturbation sources. Work to improve the stability of the orbit began in 1995, with the
perturbation sources. Work to improve the stability of the orbit began in 1995, with the
installation of the orbit feedback system. This orbit feedback system has been
installation of the orbit feedback system. This orbit feedback system has been
equipped with insertion devices, including undulators (U5 and U9) and, in particular,
equipped with insertion devices, including undulators (U5 and U9) and, in particular,
an elliptically polarized undulator (EPU5.6). Orbit drift and low frequency oscillations
an
elliptically polarized undulator (EPU5.6). Orbit drift and low frequency oscillations
have also been reduced. The orbit feedback system in the storage ring of SRRC is now
have
been reduced.
The orbitincludes
feedbackincreasing
system infeedback
the storage
ring of SRRC
is now
beingalso
upgraded.
This upgrade
bandwidth,
increasing
being upgraded. This upgrade includes increasing feedback bandwidth, increasing
CP648, Beam Instrumentation Workshop 2002: Tenth Workshop, edited by G. A. Smith and T. Russo
© 2002 American Institute of Physics 0-7354-0103-9/02/$19.00
516
sampling rate, compensating for the eddy current effect of the vacuum chamber with a
sampling rate, compensating for the eddy current effect of the vacuum chamber with a
filter, and enhancing the performance and robustness of the control rules. This report
filter, and enhancing the performance and robustness of the control rules. This report
summarizes the status of the orbit feedback development in SRRC.
summarizes the status of the orbit feedback development in SRRC.
EXISTING
EXISTING ORBIT
ORBIT FEEDBACK
FEEDBACK SYSTEM
SYSTEM
AA digital
been developed
developed to
to suppress
suppress orbit
orbit
digital orbit
orbit feedback
feedback system
system [1,2]
[1,2] had
had been
disturbances
such
as
long-term
drift,
low
frequency
oscillation
and
perturbation
due
disturbances such as long-term drift, low frequency oscillation and perturbation due toto
the
of the
the system
system isis the
the response
response
theoperation
operation of
of insertion
insertion devices.
devices. The
The main
main component
component of
matrix.
The
linear
response
matrix
is
measured
by
taking
an
electron
beam
position
matrix. The linear response matrix is measured by taking an electron beam position
monitor
(BPM)
reading
when
each
corrector
is
individually
perturbed.
This
response
monitor (BPM) reading when each corrector is individually perturbed. This response
matrix
method for
for compensation
compensation
matrix isis inverted
inverted by
by aa single
single value
value decomposition
decomposition method
calculation
of
system.
The
feedback
controller
is
based
on
the
PID
algorithm.
Digital
calculation of system. The feedback controller is based on the PID algorithm. Digital
filtering
techniques
were
used
to
remove
noise
in
the
electron
beam
position
reading,
filtering techniques were used to remove noise in the electron beam position reading,
totocompensate
vacuum chamber,
chamber, and
and to
to increase
increase the
the
compensate for
for the
the eddy
eddy current
current effect
effect of
of the
the vacuum
bandwidth
of
the
orbit
feedback
loop.
The
infrastructure
of
the
digital
orbit
feedback
bandwidth of the orbit feedback loop. The infrastructure of the digital orbit feedback
system
fiber links,
links, digital
digital signal
signal
system consists
consists of
of an
an orbit
orbit acquisition
acquisition system,
system, gigabit
gigabit fiber
processing
software,
and
high
precision
digital-to-analog
converters.
The
orbit
processing software, and high precision digital-to-analog converters. The orbit
feedback
constitutes
a
typical
multiple
input,
multiple
output
problem.
Figure
feedback constitutes a typical multiple input, multiple output problem. Figure 11
depicts
Implementing an
an analog
analogmatrix
matrix
depictsthe
the basic
basic concept
concept of
of the
the orbit
orbit feedback
feedback system.
system. Implementing
operation
with
many
BPMs
and
correctors
is
technically
difficult.
However,
a
digital
operation with many BPMs and correctors is technically difficult. However, a digital
based
feedback
system
is
a
better
way
to
implement
the
multiple
input/output
system.
based feedback system is a better way to implement the multiple input/output system.
com puter
server
Sun SPAR C
W orkstation
M ouse
Keyboard
Keyboard
Keyboard
M ouse
M ouse
Keyboard
Sw itch H ub
Sw itch H ub
......
16
AC
1 6bitbitDD
AC
16
AC
1 6bitbitDD
AC
16
AC
1 6bitbitDD
AC
0
0
RReflective
eflective
M
em ory
Memory
c
DDSP
SP BBoard
oard CC40
40
*
......
PPC
PPC 604e/200
604e/200
M
Hz
MHz
P
*
DVX26
X
D V X 2601#7
1
H
0
DVX26
1
D V X 2503
1
VME
V
M E crate (corrector node)
0,
D V X 2601#1
MHs
1
0
Tim er Interrupt
PPC 604e/200
PPCM604
Hz
3
R eflective M em ory
V M E crate (BPM node)
0
C .H .Kuo'98/06/08
FIGURE 2.
2. Hardware
Hardware structure
structure of
of system.
system.
FIGURE
517
Workstation
Workstation
Workstation
PC
Ethernet
VME
DDB Upload
Program
Setting
Service
Program
BPM
Reflective
M em ory
BPM node
Dynamic Database
Global
Feedback
GeneralReading
Program
PowerSupply
Reflective
M em ory
AO card
FiberO ptic
AI card
FIGURE 3.
3. Software
Software diagram
diagram of
of system.
system.
FIGURE
HARDWARE STRUCTURE
STRUCTURE
HARDWARE
Figure 2 illustrates the hardware configuration
configuration of the corrector
corrector control
control system
system in
in
SRRC. The low layer is a VME crate
crate system
system and
and includes
includes aa PowerPC
PowerPC 604e
604e CPU
CPU
board and I/O interface cards. The CPU board consists
consists of
of a PowerPC
PowerPC microprocessor,
microprocessor,
32 megabytes on-board memory, RS-232, PMC sites and Ethernet ports.
ports. The front-end
front-end
devices are connected to this system via VME interfaces
interfaces for
for analog
analog I/O
I/O and
and digital
digital I/O.
I/O.
A PowerPC-based server system is used as the TFTP file
file server
server for
for OS
OS downloading
downloading
and the network file server (NFS) for disk mounting.
mounting. All
All application
application programs
programs are
are
stored on the server disk. These programs are developed and debugged
debugged on
on the
the client
client
node to relieve the server loading. The real-time
real-time multi-tasking
multi-tasking kernel
kernel is
is embedded
embedded in
in
the single board computer of the VME bus. It provides
provides satisfactory
satisfactory performance,
performance,
reliability, and a rich set of system services. A new device is easily created
created by
by aa
modification in the device table file,
just
like
editing
a
word
file
on
line.
The
system
file, just
file
line. The system
can automatically boot and execute various applications in each VME
VME node
node with
with the
the
same operation system environment after
after rebooting or restarting
restarting the
the system.
system. The
The
upload task will be reduced to a low priority when the global feedback
feedback is on, avoiding
interference with the latency time of the feedback
feedback system.
system. This
This task
task handles
handles the
the analog
analog
input, digital input and database service when it receives the broadcast
broadcast upload
upload message
message
from the Ethernet. The cycle time of the system was improved
improved to
to 1 ms
ms by
by the
the VME
VME
interrupt. The present hardware system consists of two VME
VME crates,
crates, an orbit
orbit server
server
VME crate, and a corrector and computation VME crate. The bus
bus adapter
adapter is
is inserted
inserted in
in
slot one of the VME crate as a system controller. All programs
programs were
were developed
developed and
and
debugged on the PC and downloaded to a DSP board. The DSP
DSP board,
board, carrying
carrying the
the
TMS320C40 module, handles all signal processing. This includes a digital
digital low
low pass
pass
filter (LPF) and a PID controller. Completing the feedback
feedback processes
processes takes
takes 1 ms,
ms,
including the operation of the PID, digital low pass
pass filtering,
filtering, matrix
matrix operation,
operation, BPMs
BPMs
data reading from reflective memory, and the corrector compensation. The corrector
corrector
setting was upgraded to a 16 bit DAC to achieve sub-µrad
sub-jurad steering resolution. All
parameters can be remotely adjusted
adjusted from
from graphical
graphical interfaces
interfaces of
of the
the control
control system.
system.
518
SOFTWARE STRUCTURE
STRUCTURE OF
OF SYSTEM
SYSTEM
SOFTWARE
The corrector
corrector node
node isis attached
attached to
to the
the corrector
corrector controller
controller via
via aa PowerPC,
PowerPC, multiple
multiple
The
16 bit
bit D/A
D/A and
and A/D
A/D cards
cards and
and aa DSP
DSP card.
card. Figure
Figure 44 shows
shows the
the structure
structure of
of the
the
16
application software.
software. Some
Some process
process tasks
tasks are
are performed
performed in
in the
the PowerPC.
PowerPC. The
The setting
setting
application
process involves
involves aa corrector
corrector setting
setting when
when aa setting
setting command
command arrives
arrives from
from the
the database.
database.
process
It spawns
spawns child
child tasks
tasks to
to process
process command
command requests
requests to
to save
save the
the PowerPC
PowerPC loading.
loading. The
The
reading
is
triggered
by
the
external
10
Hz
clock
signal
from
the
network
when
the
reading is triggered by the external 10 Hz clock signal from the network when the
broadcasted upload
upload message
message isis received
received from
from the
the network.
network. An
An event
event isis sent
sent from
from the
the
timing server
server to wake
wake up
up the
the data
data acquisition
acquisition process.
process. The
The data
data acquisition
acquisition process
process of
of
the PowerPC directly
directly controls
controls the
the I/O
I/O interface
interface cards
cards of
of crate.
crate. The
The DDB
DDE process
process
handles communicating
communicating with
with the
the shared
shared memory
memory between
between the
the reading
reading and
and setting
setting
process. ItIt also
also provides
provides data
data access
access for
for the
the external
external request
request to
to survey
survey the
the feedback
feedback
process.
performance.
OPERATIONAL PERFORMANCE
PERFORMANCE
OPERATIONAL
Operational performance of
of the
the orbit
orbit feedback
feedback system
system was
was obtained
obtained by
by varing
varing the
the
gap of the insertion devices
devices and
and the
the externally
externally applied
applied perturbation
perturbation source
source in
in the
the
corrector. Figures
Figures 4,
4, 55 and
and 66 show
show the
the results.
results. The
The cutoff
cutoff frequency
frequency of
of LPF
LPF isis 60
60 Hz,
Hz,
corrector.
combination of
of PID
PID parameters
parameters was
was selected
selected to
to fulfill
fulfill control
control goals
goals toto
and the combination
minimize the orbit
orbit variation
variation due
due to
to any
any perturbation
perturbation source
source in
in the
the devices.
devices. The
The PID
PID
minimize
parameters were
were modified
modified while
while increasing
increasing the
the bandwidth
bandwidth of
of the
the feedback.
feedback. The
The
parameters
description is
is based
based on
on parameters,
parameters, K
Kpp == 0.8,
0.8, KKIi ==0.03
0.03and
andKKa=
0.
following description
d = 0.
Perturbation with
with U5
US Gap
Gap Variation
Variation
Perturbation
R C V C P S 1 1 (A )
S a t J u n 1 3 1 6 :4 2 :2 4 1 9 9 8
- 0 .3 2 5
Orbit differencewith U5 gapchangeand feedback on/off
0.2
"gap:40mmfeedback on"
"gap:40mmfeedback off"
"gap:100mmfeedback off"
Orbit difference (unit :mm)
0.15
' e 9 8 0 6 1 2 g .d a t '
- 0 .3 3
- 0 .3 3 5
- 0 .3 4
- 0 .3 4 5
- 0 .3 5
0.1
R 2 B P M 5 Y (m m )
1«
0.05
- 0 .3 5 50
100
200
300
S a t J u n 1 3 1 6 :4 0 :3 4 1 9 9 8
- 1 .4 4 2
- 1 .4 4 4
- 1 .4 4 6
- 1 .4 4 8
- 1 .4 5
- 1 .4 5 2
- 1 .4 5 4
- 1 .4 5 6
- 1 .4 5 8
- 1 .4 6 0
100
200
300
0
-0.05
-0.1
O n (1 )/O ff (0 )
S a t J u n 1 3 1 6 :3 5 :4 4 1 9 9 8
-0.15
-0.2
400
500
600
T im e I n te r v a l:0 .1 s
700
800
900
' e 9 8 0 6 1 2 g .d a t '
400
500
600
T im e I n te r v a l:0 .1 s
1
700
800
900
' e 9 8 0 6 1 2 g .d a t '
0
-0.25
0
10
20
30
40
BPMlocation in the storagering
50
60
0
100
200
300
400
500
600
T im e I n te r v a l:0 .1 s
700
(a)
(b)
(a)
(b)
FIGURE
FIGURE 4.
4. (a)
(a) Orbit
Orbit displacement
displacement with
with various
various gaps
gaps of
of U5
U5 and
and feedback
feedback on/off.
on/off.
displacement
displacement with
with corrector
corrector perturbation
perturbation and
and feedback
feedback on/off.
on/off.
519
800
900
(b)
(b) Orbit
Orbit
A new insertion device has been installed in the storage ring. It is a 4-meter long
prototype undulator with a 5 cm period (U5). The orbit is changed due to the beta
beating and field error of the insertion device. Figure 3 presents the orbit variation
with and without DGFB, while adjusting the U5 gap. The difference orbit is defined
from the gap variation of ID. The gap of ID is to 100mm and 40mm from the 219mm.
The displacement of the orbit was much smaller when the digital global feedback was
turned on than when it was off.
Perturbation Source due to Corrector
The displacement of the orbit due to a perturbation source at the corrector is much
smaller when the orbit feedback is turned on than when it is off. Figure 4(b ii) shows
the results of the performance testing. The beam position monitor, R2BPM5Y, is
included in the feedback loop. An external perturbation source is applied in the
corrector. The source is a 0.9 Hz sine wave with an amplitude of 0.02 A peak-to-peak.
Figure 4(b i) shows the perturbation source, RCVCPS11. Figure 4 (b iii) shows the
orbit feedback control status.
UPGRADE ISSUES
The new hardware system is based on a new model DSP board and is compatible
with the new development environment. This Windows-based environment, with an
Ethernet network, supports maintenance and trouble-shooting. The host of the
corrector node handles interrupt requests and generates two signals to the DSP. One is
for vertical orbit feedback; the other is for horizontal orbit feedback. The DSP, Texas
Instruments TMS320C40, was also upgraded to 50 MHz from 40MHz.
This upgrade will be insufficient in the future, when many insertion devices are
installed. The number of BPM signals is continually increasing and the corrector must
be included in the feedback loops, especially since the insertion devices are operated
at the same time. The orbit feedback system is currently being upgraded. The new
system is planned to become operational in 2002. Several reasons for the upgrade exist.
First, to improve system maintainability and stability. The DSP board of the original
feedback system is embedded in the corrector control of VME crate, which is
inconvenient for the development of the feedback system. The hindrance of feedback
loop R&D due to machine operations is troublesome. Secondly, the system was
implemented in 1995 with a slow DSP board; the functionality of the feedback loop is
limited. Computing power is insufficient to handle the demand for more BPMs and
correctors. The selection of a control algorithm is also limited. In the new
implementation, the feedback calculation will be located in a separate VME crate. An
Ethernet-based processor was selected to provide remote access. The corrector node is
loosely coupled to. The upgraded system includes three VME crates, the BPM node,
corrector node, and feedback node as shown in Figure 5. These three nodes are
connected by reflective memory. Several fiber link reflective memory cards are held
tightly together by one dedicated reflective hub that simplifies the wiring of the fiber
link. The corrector node handles power-supply control. The feedback node is upgraded
520
from the DSP to the PowerPC 7410 (G4) that handles feedback control, the control
algorithm calculation and corrector compensation data conversion from orbit
information. The correction results are sent to the host processor of the corrector node
to do compensation processing.
DSP and PowerPC
The calculation power of the processor can handle more and more multi-input and
multi-output controller loops in each millisecond. The new generation DSPs, such as
TMS320C6201 and TMS320C6701 from Texas Instruments, suffice. However, DSP
maintenance and stocking represent problems that are expensive to solve. The general
purpose CPU, a PowerPC with a real time OS, is preferred over DSP for this. The
manufacturer supports driver and Business Service Provider (BSPP in the operation
system to reduce the development time for this upgrade.
The PowerPC is based on Motorola's AltiVec technology, and, specifically, the
fourth generation MPC74xx. The digital signal processing applications are beginning
to migrate from a traditional DSP environment to a RISC environment. At the same
time, Motorola has been increasing the processing power of the PowerPC, increasing
the speed and flexibility of an already impressive portfolio of DSPs, and Texas
Instruments has been introducing new parts for the C6000 family. Table 1 specifies
some of the processors available from Texas Instruments and Motorola, these will
satisfy requirements in the future.
TABLE 1. Processor lists for orbit feedback.
Manufacturer
Texas Instruments
Texas Instruments
Texas Instruments
Motorola
Part Number
TMS320C6415
TMS320C6203
TMS320C6701
MPC7410
Processor
C6415
C6203
C6701
7410
TABLE 2. Speed and benchmarks for DSP and PowerPC. The 7410 can perform up to 16 parallel
integer calculations on 8-bit data every cycle, so the MIPS number would be 16 multiplied by 500 MHz
or 8000 MIPS. 2) Some 7410 instructions can be performed at eight calculations per cycle.
Clock(MHz)
Instruction Cycle (ns)
Instruction Per Cycle
Peak MIPS
Floating-Point Operations Per
Cycle
Peak MFLOPS
600
1.67
1-8
4800
-
300
3.33
1-8
2400
-
C6701
167
6
1-8
1336
1-6
7410
500
2
1-3
9171
42
1000
2000
Compare the clock speeds and peak processing power in the Table2. The
performance of PowerPC is close to the DSP.
521
CONCLUSIONS
CONCLUSIONS
The feedback node is now a separate VME crate
crate from
from the
the original
original corrector
corrector node.
node.
The sub-component of the feedback node is now being tested. These components
components
include the VME interrupt request, VME
VME bus
bus access,
access, signal
signal processing
processing and
and the
the
controller loop.
loop. The
The task
task of
of corrector
controller
corrector node
node will
will be
be simplified,
simplified, has
has been
been modified,
modified, and
and
will be
be tested
tested during
during aa shutdown
will
shutdown of
of the
the storage
storage ring.
ring. Some
Some slots
slots will
will be
be vacated
vacated in
in this
this
crate due
due to
to removal
removal of
of the
the DSP.
DSP. It
It will
will reserve
reserve slot
crate
slot of
of VME
VME to
to increase
increase numbers
numbers of
of
corrector control
control in
in the
the future.
corrector
future. Figure
Figure 55 presents
presents the
the new
new system
system structure.
structure.
PC
Control
Consoles
Control
Network
Orbit Acquisition
VME Crate
16 16
Bit Bit
A A
D D
C C
16
Bit
A
D
C
VME Host
PowerPC 7410
(G4)
H
O
S
T
RM/
DMA
Timer Generator
V
M
E
Reflective Memory
Hub
RM/
DMA
Corrector Control
VME Crate
V
M
E
Feedback
VME
Crate
H
O
S
T
RM/
DMA
16 16
Bit Bit
D D
A A
C C
16
Bit
D
A
C
Private Ethernet Switch
Correction Magnet Power Supply
Electron BPM
PBPM Front-end
PBPM Front-end
PBPM Front-end
Photon BPM
Orbit Feedback System Upgrade, June 8, 2001
;k System Upgrade, Jim
FIGURE 5.
FIGURE
5. The
The block
block diagram
diagram of
of new
new system.
system.
REFERENCES
REFERENCES
1. C.
C. H.
H. Kuo,
Kuo, et
et al.,
al., Local
Local Feedback
Feedback Experiment
Experiment in
1.
in the
the Taiwan
Taiwan Light
Light Source,
Source, Proceedings
Proceedings of
of 1997
1997
IEEE Particle
Particle Accelerator
Accelerator Conference,
Conference, Vancouver,
IEEE
Vancouver, 1997.
1997.
2. C.
C. H.
H. Kuo,
Kuo, et
et al.,
al., Digital
Digital Global
Global Orbit
2.
Orbit Feedback
Feedback System
System Developing
Developing in
in SRRC,
SRRC, Proceedings
Proceedings of
of 1997
1997
IEEE Particle
Particle Accelerator
Accelerator Conference,
Conference, Vancouver,
IEEE
Vancouver, 1997.
1997.
522