A Digital Signal Receiver VXI Module For BPM
And Phase Detection Processing
Brian E. Chase, Keith G. Meisner
Fermi National Accelerator Laboratory, Box 500, Batavia IL 60510
Abstract A VXI module containing eight digital receivers is described for use in the Fermilab
Main Injector, Tevatron and Recycler Low Level RF systems. It is used as a phase detector and
radial position processor for multi-harmonic RF operation. This module is also slated for use in
the Recycler Electron Cooling system as a multiple beam BPM processor. The module and its
many operational modes are discussed.
INTRODUCTION
The Fermilab Main Injector RF System supports many RF accelerating frequencies.
The 53 MHz RF is currently the main accelerating system, while other harmonics are
designed for coalescing multi-bunch protons and antiprotons (pbars) before transfer
into the Tevatron for Collider operation. The proposed scheme to decelerate hot
Tevatron pbars in the Main Injector for storage in the Fermilab Recycler Ring will
require using 2.5 MHz RF in a closed loop feedback mode, with new detectors,
preamps, and signal processing for phase and radial position detection at 2.5 MHz. A
Digital Signal Receiver (DSR) module has been prototyped that is compatible with the
existing LLRF platform and provides the required processing. This module far
exceeds the accuracy and dynamic range of the present analog processing equipment.
The DSR also fits the dual beam measurement requirements for the BPM system in
the Electron Cooling straight section of the Recycler Ring.
DIGITAL SIGNAL RECEIVER
Hardware Description
The DSR VXI module has eight digital radio channels that are controlled and read
out by a single Digital Signal Processor (DSP). The channels may be synchronized in
pairs, or in groups of pairs to make coherent measurements between multiple inputs.
Synchronized DSR channels form the core of any Quadrature Amplitude Modulation
(QAM) or vector processing function, while the DSP uses the channel vectors to
compute complex functions in real time. This real time data is then presented to off
module processes in a variety of high speed data ways.
CP648, Beam Instrumentation Workshop 2002: Tenth Workshop, edited by G. A. Smith and T. Russo
2002 American Institute of Physics 0-7354-0103-9
368
Each DSR channel receives signal through a daughter card that allows custom
analog preprocessing and anti-alias filtering. The daughter card output drives an
Analog Devices AD6644 14 bit, 65 MSPS ADC and an AD6620 Digital Receiver
Processor. The digital receiver contains a frequency translator and three cascaded
filters. It outputs I and Q data that is read out by the ADSP-21062 DSP. The DSP
provides additional narrow band filtering of the I/Q data, and calculations of position
or phase at data rates of up to 1 MHz. The DSP also programs the AD6620s, drives an
eight channel DAC, and provides digital control of the analog processing daughter
cards. All ADCs are clocked from a common front panel input. Each AD6620
channel pair is separately programmable to allow processing at different center
frequencies, bandwidths, decimation rates and gains.
Noise sources on the DSR module include VXI bus transfers, on-board clocks,
DSP internal processes, and data transfers from the AD6620s. This noise must be
controlled to take full advantage of the ADC's dynamic range. When all eight
channels are synchronized to latch AD6620 output data at the same time, coherent
noise from digital power bus currents transfer to the analog power bus and the ADCs.
For a data rate of 21.66kHz, this noise signal level measures at about -90 dBc.
Careful choices of decimation and clock rates allow for minimum interference to the
measurement.
Processor Calculations
Once the I and Q data is acquired by the DSP, it is converted to floating point
format to vastly increase the dynamic range of further processing. The DSR module's
synchronization between channels allows for measurements of relative phase as well
as amplitude, making it effectively a multi-channel Vector Signal Analyzer. The
phase measurement is very accurate over a large dynamic range due to the small errors
inherent in digital down conversion. The determination of position from split plate
detector signals "a" and "b" is solved to first order by the equation (a-b)/(a+b).
Maintaining the phase information and solving the equation with the complete vector
increases accuracy in the presence of random noise. The phase error between plate
signals is measured and zeroed by setting the phase register in the AD6620's NCO.
With a zero phase difference between plates some terms may be eliminated from the
position calculation as well as removing the computationally intensive square roots.
Position =
The relative phase between two channels is found by dividing the two vectors and
taking the arctangent of the resultant vector. l
b
(J
a
Q ^ . ___Qb___ (J _Q ^
a
2
2 a
a
L
^xt
7 +O
Phase = arctan(-a-)
369
'
Optimizing For Accuracy And Signal To Noise
Any signals other than the signal intended for processing are capable of increasing
the variance and or mean of the processed result. These signals may be random noise,
out-of-band signals picked up on cables, or distortions of in-band signals caused by
non-linearity in the process chain. The sources of random noise are preamplifiers, the
quantization noise of the ADC and the digital receiver's filters. This noise is reduced
by separately filtering the I and Q outputs to as narrow a bandwidth as practical, and
by optimizing the gain at each stage in the signal chain. High over sampling ratios
improve SNR by spreading the quantization noise of the ADC over a larger spectrum.
This noise may then be largely removed by digital filtering. This "Process Gain" is
calculated from the equation:
/ Sample _ Rate_ Of _
= 10xlogi ——*—=———~ " ~——j
V
Filter Bandwidth )
For the case of an output bandwidth of 1 Hz and a sample rate of 65 MHz, the process
gain is an impressive 78 dB!
Correlated noise from cable pickup or noise on the DSR module itself presents a
more serious problem than random noise. In band correlated signals cause a shift in
the mean position output and therefore cannot be filtered out. If these noise sources
are identified, then frequency domain filtering can suppress any strong lines that are
present. While noise is a major issue for wide band systems, non-linearity and gain
stability dominates position accuracy in extremely narrow band systems. Sources of
non-linearity are ADC differential non-linearity and round off errors in the AD6620
filters. Adding out-of-band signal or dithering reduces the distortion of the ADC.
Operating the AD6620 at the lowest decimation rate possible and setting the filter
stage gains as high as possible reduces round off errors. Slight de-tuning of the
AD6620 center frequency randomizes the round off errors in the digital receiver's I
and Q outputs so that they may be averaged out by the wide dynamic range floating
point filters in the DSP.
MAIN INJECTOR LOW LEVEL RF SYSTEM OVERVIEW
The Main Injector Low Level RF (MILLRF) system generates low power
signals at several harmonics of the MI beam revolution frequency. Its RF outputs
drive High Level systems that develop cavity RF buckets to support RF synchronous
transfer, beam energy control, bunch shape manipulations, and preservation of
longitudinal emittance. TTL outputs at the revolution frequency trigger local systems
and drive the Main Injector Beam Synchronous Clock to support beam transfers
between machines, beam diagnostics, and high bandwidth beam control systems.
Beam energy control requires Direct Coupled RF phase and frequency
feedback whenever the MI energy (bend buss current) is changing. This feedback is
classic RF phase control based on detected beam radial position (RPOS) and the LLRF
oscillator to beam Phase Lock Loop (PLL). MILLRF is largely a VXI system that
370
includes seven VXI modules manufactured by Fermilab. A VXI DSR module
processes BPM detected signals at 2.5Mhz and 53Mhz, to provide the RPOS signal
required for DC beam energy feedback. The DSR also provides 2.5Mhz and 53Mhz
I/Q demodulators for the phase detection required by the PLL and frequency feedback
loop.
Radial Position (RPOS) Processing in the Main Injector
While beam radial position processing is basically the same as other BPM
measurements, there are additional requirements. In the Main Injector, the RPOS
system must work well over beam intensities from 1E10 to at least 2E13, from a single
bunch to an almost full ring, and with beam bunched at several RF frequencies. 2'3
DSR ADC+DRP
Main Injector
Q530 BPM
(detector)
DSR SHARC DSP
channel 0 53Mhz Fcenter, 30Khz BW
channel 1 53Mhz I
0» Q 0 » 1 1 » Q 1 outputs
Data Valid DSP interrupt @ 21Khz
channel 2 2.5 Mhz Fcenter, 30Khz BW
channel 3 2.5Mhz I
2 > Q 2 > I 3 > Q 3 outputs
——^
I/Q data acquisition
IIR Filters
RPOS calculation
RPOS of 2.5 or 53 Mhz MI beam
SetRposLowClampO
Set RposHighClampO
Set RposIIRFpoleQ
Acceleration and
Deceleration
Transition Crossing
Sign control
RPERR
QRPFB
Loop Output
to phase shifter
ROFF
(p,t) curve
RGAIN
(p) curve
JT
SetPgainQ
SetRposFb(HOLD)
NAMES are DSR DSP sourced data and Acnet Devices updated at 720hz
FunctionNameQ describes DSR DSP interface (software) for Rpos feedback processes
Figure 1. MILLRF DSR RPOS Processing Block Diagram
The process must also have short group delay to optimize the radial position
feedback loop. For 200 Hz closed loop bandwidth and 30-degree loss in phase
margin, the group delay must be less than 400 microseconds. To achieve this delay,
the AD6620 RAM Coefficient Filter is programmed with a simulated 2nd order IIR
low pass combined with a notch filter centered at the revolution harmonic. This RPOS
data is passed to the radial position feedback loop at a 100 kHz rate, as shown in
figure 1.
371
ELECTRON COOLING BPM SYSTEM
The Electron Cooling System for the Recycler Ring will send a low emittance
electron beam along the same axis as the 8 GeV Recycler Ring anti-proton beam in a
specially designed straight section. The velocities of the beams are closely matched to
exchange heat by coulomb scattering and cool the antiproton beam. For cooling to
work properly, the relative position of the two beams must be measured and controlled
to the 50-micrometer level. Because the detector plates see both beams at
Ecool BPM Signal Flow Diagram
Low Noise
Current
Preamp
Analog Preprocessing Analog to Digital
r
Daughter Card
Converte^
V152 Slot 0 Controller
Acnet/MOOC Interface
Ethernet
DSR Function List
DsrReset()
DsrLdr()
DsrLdFilter()
DsrSetNCOFreqO
DsrSetNCOPhase()
DsrSetCIC2Gain()
DsrSetCIC5Gain()
;quency set
Mapping Coefficients
DSR Channel Pair 1of4
DsrLdDetMap()
DsrLdCalCoefF()
DsrSetPreampGain()
DsrMapDac()
DsrSetDacGain()
DsrSetDacOffset()
DSR VXI Module 1 of 11
Ecool BPM VXI Crate
Generatorl
gf 5
M Calibration SyStem
CallSpiitudeO
CalSetWaveshape()
Ethernet
Generator 2
Figure 2.
the same time, their position signals must be resolved in the frequency domain. The
anti-proton beam position is processed at the first revolution harmonic signal of 90
kHz and the electron beam is processed at 32 kHz. The 32 kHz signal is produced by
a few milliamps modulation on the 1 amp DC beam. By frequency hopping DSR
receiver channels between these frequencies, the two beam positions can be measured
almost simultaneously. The filter sections of the AD6620s are programmed with an
800 Hz bandwidth (BW) and an output data rate of 21.66 kHz. The DSP filters the I
and Q data down to a 100 Hz BW and calculates position and beam intensity at a 800
Hz rate. This data is available to the control system for fast time plots. The position
data is further filtered down to a 1 Hz BW and is served to a beam position application
program through the ACNET control system.
372
The
allows programmable
programmable gains
gains in
in each
each of
of the
the filter
filter stages.
stages. The
The first
first
The AD6620
AD6620 allows
Combined
Comb
Integrator
filter
(CIC2),
has
a
range
of
36
dB,
the
CIC5
filter
120
Combined Comb Integrator filter (CIC2), has a range of 36 dB, the CIC5 filter 120
45
dB,
and
the
RAM
Coefficient
Filter
(RCF),
42
dB.
From
the
AD6620
data
sheet
dB, and the RAM Coefficient Filter (RCF), 42 dB. From the AD6620 data sheet4,5' ,,
the
safe gains
gains for
for our
our filter
filter design
design are
are determined
determined to
to be:
be:
the maximum
maximum safe
CIC2
(-36 dB)
15
CIC2 =
= 66 (-36
dB) for
for MCIC2
MCIC2 =
= 15
CIC5
(-102 dB)
dB) for
= 20
20
CIC5 =17
=17 (-102
for MCIC5
MCIC5 =
Sout
Sout =
= 7(-18dB)
7 (-18 dB)
Where
and MCIC5
MCIC5 are
are the
the stage’s
stage's decimation
decimation rates.
rates.
Where MCIC2
MCIC2 and
For
SNR and
and linearity,
linearity, the
the gains
gains in
in each
each stage
stage may
may be
be increased
increased based
based on
on
For the
the best
best SNR
the
total
signal
level
in
the
pass
band
of
that
stage.
The
goal
is
that
each
stage
works
the total signal level in the pass band of that stage. The goal is that each stage works
as
load level
level while
while maintaining
maintaining aa reasonable
reasonable safety
safety margin.
margin. An
An AGC
AGC
as close
close to
to its
its over
over load
is
conceived
to
work
in
the
following
manner.
Starting
at
a
safe
low
gain,
CIC2
gain
is conceived to work in the following manner. Starting at a safe low gain, CIC2 gain
is
increased
while
monitoring
position.
A
small
calibration
signal
that
is
out
of
band
is increased while monitoring position. A small calibration signal that is out of band
of
filter but
but in
CIC2 filter
filter is
is injected
injected into
into the
the preamp.
preamp. If
If the
the gain
gain
of the
the CIC5
CIC5 filter
in band
band of
of the
the CIC2
change
or
the
calibration
signal
affects
position
the
CIC2
gain
is
reduced.
This
change or the calibration signal affects position the CIC2 gain is reduced. This
procedure
to adjust
adjust the
the CIC5
CIC5 filter
filter gain.
gain. The
The RCF
RCF gain
gain is
is then
then set
set so
so that
that
procedure is
is repeated
repeated to
the output intensity signal is within –15
-15 to
to –3
-3 dB
dB of
of full
full scale.
scale. Gain
Gain ranging
ranging isis of
of
course unnecessary in the DSP filters due
due to
to floating
floating point
point processing.
processing. A
A power
power sweep
sweep
of the input power is shown in figure
figure 3.
3. Only
Only two
two gain
gain changes
changes were
were made
made in
in the
the
AD6620 filter sections during this 100
100 dB
dB sweep
sweep and
and as
as aa result
result aasystematic
systematicerror
errorinin
position is seen around –40
-40 dBm.
dBm. These
These errors
errors are
are expected
expected to
to be
be greatly
greatly reduced
reduced by
by
implementing the AGC algorithm.
DSR BPM
BPM Power
Power Sweep
Sweep 2.5
2.5 MHz
MHz
DSR
HzBW
11 Hz
BW
6
(a)
4
(b)
2
"0 dB"
"1 dB"
-120
(c)
(c)
"-1 dB"
0
-100
-80
-60
-40
-20
0
20
"2 dB"
"-2 dB"
-2
(d)
-4
(e)
(e)
-6
Input
B) (dBm)
Input Power max( A
A , B)(dBm)
Figure 3.
3. 100
Figure
100 dB
dB power
power sweep
sweep of
of the
the DSR
DSR Module.
Module. The
The five
five graphs
graphs are
are produced
produced by
by changing
changing the
the
power ratio
ratio between
between channels
channels in
in 11 dB
power
dB steps:
steps: a=2
a=2 dB,
dB, b=1
b=l dB,
dB, c=0
c=0 dB,
dB, d=-1
d=-l dB,
dB, ee == -2
-2 dB
dB
Calibration And Mapping Of Detector
Each BPM detector in the Electron Cooling section has been carefully mapped over
its full range. A 3rd order fit to this data will be applied to the raw data at 800 Hz
when the position is calculated. Gain terms determined from calibration are applied
here as well. The calibration system will generate arbitrary waveform generator
signals that mimic the frequency and wave shape of the beam of interest. This signal
is injected through precision resistors to the tunnel preamp. The resistors are of
slightly different values to calibrate for a position offset of about 1mm. This offset
gives the system the additional information that there are no shorts between channels
and the cables are wired correctly. Beam signals may be mimicked as closely as
possible in shape and intensity. Calibration may be checked with beam in the machine
by moving the calibration signal frequency away from the beam frequency. The
calibration system may also be used to generate dither signals to reduce the differential
nonlinearity in the ADC.
CONCLUSIONS
Digital Radio technology has advanced to the point where it is a clear winner
or at least a strong contender for a wide variety of IF and direct RF processing
applications. Using this technology, the DSR module is finding many applications
beyond its original designed of radial position and phase processing. The function
blocks of programmable analog daughter cards, digital receivers and floating point
DSP create a very powerful and flexible processing environment. The bi-directional
high-speed digital IO allows the DSR to be used in many real time feedback
applications. The ability to program perfectly matched digital filters with over 130 dB
dynamic range makes it ideal for processing high precision narrow-band applications
such as the Ecool BPM system. At a production cost of less than $2000 per unit, the
DSR module is attractive for even high channel count instrumentation projects.
ACKNOWLEDGMENTS
The development of any complex system requires teamwork and the shared
experience from an open engineering environment. Special thanks to the LLRF
Group members; Barry Barnes, Jerry Cai, Paul Joireman, Dan Klepec and to Duane
Voy for continuing improvement of our software development environment.
374
REFERENCES
1
Wooton, Beckman, Dolciani, Modern Trigonometry, Boston: Houghton Mifflin Company, 1966, pp.
259-280.
2
Chase, B., Barnes, B., and Meisner, K., "Digital Low Level RF Systems for Fermilab Main Ring and
Tevatron" in Proceedings of the 1997 Particle Accelerator Conference, edited by M.Comyn et al.,
Institute of Electrical and Electronic Engineers, Inc, New Jersey: 1998, pp. 2326-2328.
3
Chase, B.,Mason, A., Meisner, K., "Current DSP Applications in Accelerator Instrumentation and RF" in
Proceedings of the 1997 International Conference on Accelerator and Large Experimental Physics Control
Systems, Editors Jijiu Zhao, Axex Daneels, IHEP Chinese Academy of Sciences, Beijing, China, P230
4
"65 MSPS Digital Receiver Signal Processor" Analog Devices, Norwood, MA
5
"Designing Filters with the AD6620" Analog Devices, Greensboro, NC
375