Radiation Protection Utilizing Electronic Berms John Anderson Jr. and Glenn Federwitz Fermi National Accelerator Laboratory Abstract. Excessive radiation losses from particle beams produce personnel, environmental, and component activation hazards. With the new high intensity fast repetition rate beam lines being constructed at Fermilab, small pulse to pulse losses are a significant concern. This paper presents the proposed design of a total loss monitoring system for the MiniBooNE Project. INTRODUCTION INPUT DEVICES The 8 GeV Fixed Target Facility, being built at Fermilab, is used to transport beam from the Booster accelerator to a new area dedicated to external beam physics. MiniBooNE, the first experiment to use the new facility, has requested 5E20 protons per year. This equates to more beam per year than has been accelerated in the history of Fermilab. To minimize radioactivation of beamline components, groundwater, and areas outside the overburden; the project has specified a total beam loss monitoring system termed an Electronic Berm or E-Berm. This system is intended to monitor the amount of beam lost between two toroids and disable the beamline if losses exceed a predefined level. Toroid Integrator The Toroid Integrator receives an event trigger to open a lOus integrate window. Upon completion of the integration window, the integrator sends the Eberm comparator module a 16 bit 2's compliment binary data word and a valid data pulse. There are 4 possible gain settings on the integrator electronics card; they are +1.875E14, +5.625E13, +1.875E13, and +5.625E12 protons at full scale. Using the lowest gain setting and taking into consideration that the signal is bipolar, the output resolution achieved is 1.717E8 protons per count. The system described here will use two toroids and the associated integrating electronics. One toroid will be located at the upstream end of the 8 GeV beam line and the other will be located slightly in front of the target focusing horn. The comparator module will measure the absolute value of the difference of the two toroids on a pulse-to-pulse basis. Using the pulse-topulse difference along with summing the error of the last 10 pulses, both an instantaneous and integrated loss can be measured. The integrating electronics card buffers the output data word and the valid data pulse before being sent to the E-berm comparator module. Beam Presence Detector The beam presence detector utilizes a resistive wall monitor (beam sensing device) connected to a 53Mhztuned detector to provide a TTL level output pulse for each beam pulse. This signal is used as a coincidence check within the E-berm comparator module to verify the toroid integrator electronics is looking for beam at the correct time. The beam presence detector will detect beam signals of approximately 5E10 or higher. SYSTEM IMPLEMENTATION Figure 1 shows a block diagram of the E-berm system. There are four major components to the system; the toroid and integrator electronics, the calibration module, the beam presence detector (resistive wall monitor), and the comparator module. The focus of this document is on the comparator module with a brief description of the other three components. Toroid Integrator Calibration Module The Toroid Integrator Calibration Module is a part of the E-Berm total beam loss monitoring system. The module provides the ability to monitor the performance of the toroid and the integrator electronics, thus greatly improving the reliability of the beam to the experiment. The module is not part of the Fermilab Safety Systems, but rather a tool to improve the systematic performance of the E-Berm system. CP642, High Intensity and High Brightness Hadron Beams: 20th ICFA Advanced Beam Dynamics Workshop on High Intensity and High Brightness Hadron Beams, edited by W. Chou, Y. Mori, D. Neuffer, and J.-F. Ostiguy © 2002 American Institute of Physics 0-7354-0097-0/02/$ 19.00 125 The intent of the calibration module is to perform a toroid calibration sequence in approximately 100ms. To do this, the module generates a family of calibration pulses sent through the toroid calibration winding, performs a least squares fit to the data measured by the toroid integrator module, and outputs the gain and offset values to the Fermilab control system in the form of five 8 bit digital data words. total. Thus generating a sum of the last 10 beam samples to be used for subsequent comparisons. Pulse to Pulse Comparison The absolute value of the difference between integrator "A" and integrator "B" is compared to a set of switches located on the comparator board. The value of the switches for MiniBooNE is set at approximately (~3E11). This equates to 6% of the total pulse-to-pulse beam of (~5E12) per pulse. If the difference value is higher than the switch setting a trip occurs. In the normal operating mode, (not performing a calibration sequence), the module sits idle. To initiate the calibrate mode, the module receives a 1 microsecond calibrate trigger from the Fermilab control system. A calibrate in progress bit is sent to the E-berm comparator module to trip the output permits to inhibit beam during a calibrate sequence. Integrated Loss Comparison The value of the sum of the last 10 beam pulse differences is compared to a set of switches again located on the comparator board. The value of the switches for MiniBooNE is set at approximately (-IE 12). This equates to approximately a 20% loss of beam for the last 10 beam pulses. Looking at this from a pulse-to-pulse basis yields an average loss of less than 2%. Again, if the value is higher than the switch setting, a trip occurs. COMPARATOR MODULE The figure 2 shows the interconnecting logic functions performed by the comparator module. The logic functions are implemented in Altera™ large scale EPLD logic to eliminate the need for microprocessors. The diagram above shows both the "A" and "B" side comparison circuits. A description of each internal logic function is described below. Self Test Compare Between beam pulses, the integrator is triggered to take a sample with no beam present. The absolute value is then compared to a small positive value to check if the integrator has drifted away from zero. If the value gets too high, the module is tripped. This value is defined inside the EPLD's. At present, the value is set to (2.7E9) and will be defined during the commissioning process after the noise floor for the toroid integrators has been established. Intensity Compare The 16-bit signal from the "A" integrator is compared to switch settings in the "A" side EPLD's of the module and if the signal from the integrator is higher, a trip occurs. The same function occurs for the "B" side with the "B" integrator. This allows setting of a maximum intensity limit for the beamline. This is not expected to be used in the MiniBooNE beamline but is included for future applications. After completion of the zero test, a current pulse is sent through the calibrate winding of both toroids. This is to insure the integrity of all cables and the associated electronics. The absolute value is then compared against to a near full scale positive window. This checks for integrator gain drift and verifies cable integrity. If the value falls outside the window, the module is tripped. This value is defined inside the EPLD's Difference Engine This block takes the 16-bit 2's complement data values from Toroid Integrator "A" and Toroid Integrator "B", subtracts them and returns the absolute value of the result. The "A" side EPLD's perform an |"A-B"| function and the "B" side EPLD's perform an |"B-A"| function. The inversion of the two functions between the "A" and "B" sides is done to assist in preventing common mode errors. Beam Presence Detector Compare The Beam Presence Detector compare logic is used as a beam coincidence check with the toroid integrator electronics. If either toroid integrator reads more than 1E11 beam, then a pulse indicating beam has passed is required from the beam presence detector. The absence of this pulse, when more than IE 11 beam is Last 10 Sum This block adds the current value of the difference engine to a running total and stores the value in a 10 deep by 16-bit shift register. The value that gets shifted out of the memory is then subtracted from the 126 on the main board. Third, there is a reset in signal from the safety interlock system. To prevent undesired clearing of the shift registers; the reset-in signal from the safety interlock system is masked unless the system is in a tripped state. detected by either of the integrator electronics, will initiate a system trip. Timing The timing block takes the ACNET event strobe signals and passes the appropriate signal on to each integrator starting a beam event timing sequence. The event timing sequence requires that the beam pulse from the Beam Presence Detector occur between 2.5us and 8us after the event strobe occurs. Knowing that the Booster extraction pulse is 1.6us guarantees that both integrators were looking for the beam pulse at the correct time. This timing window is defined inside the EPLD's. Additionally a signal from the Beam Presence Detector at anytime outside the beam event will initiate a system trip. Clock monitor The comparator module uses two lOMhz clocks for internal timing. There are two independent clock watchdog circuits. A failure of either clock will remove the output permit signals. Proposed Use Event strobe signals may not occur at intervals of less than 40ms. This insures the previous event has been fully processes and the internal self test has completed before beginning the next event timing sequence. The E-berm system is intended to be used in place of chipmunk radiation monitor arrays. The system is not intended to be used beyond allowing the same reduction in shielding as would be allowed by the use of chipmunks. The system does not and cannot prevent the initial beam loss. The major advantages of the E-berm over the standard chipmunk radiation monitors are that losses are detected from any direction. This will help to minimize ground water activation, component activation, and allow for a reduction in the required overburden. Outputs Design Methodology The five digital output words connected to an IRM consist of the buffered 16-bit 2's complement integrator values, the 16-bit absolute value of the difference between toroid A and B, the 16-bit sum of the last 10-beam pulse losses, the zero self test value, and the test pulse value. The design methodology used in the proposed design is consistent with the guidance provided in the Fermilab Radiological Control Manual (FRCM) Chapter 10. Two independent monitoring channels are provided inside the comparator module both capable of interrupting the output permit loops. Individual trip indicators are provided to the front panel for the self test zero and test pulse compare trips, intensity compare trip, single beam pulse loss trip, sum of last 10 beam pulse losses trip, strobe A or B errors, beam presence detector error, event timing errors, and clock errors. Failure Modes Each Integrator Electronics module must provide a strobe signal indicating valid data is ready within 15us of an event strobe signal. During the design process, failure mode reduction principles utilizing redundant circuits were employed. Additionally, all signals to and from the comparator board are buffered. Monitoring two independent toroid integrators and comparing to a beam presence detector signal verifies event timing. The "A" side channel performs an Integrator |A-B| function while the "B" side channel performs an Integrator |B-A| function. The output permit signals are active high signals. Self test functions verify cable integrity. All data is echoed to the ACNET control system via an IRM for further analysis. Two 24vdc active high "A" and "B" output permits are provided for connection to the safety interlock system. Two RS-485 connections for the Safety System Data Acquisition System are also provided. Reset There are three separate reset inputs for the comparator module. Each reset signal clears the data shift registers and resets the "A" & "B" output trip circuits. First, there is an internal power up reset for the board initialization. Second, there is a manual reset button located internal to the comparator module Testing The calibration module built by Columbia University will be used to monitor the calibration drift of each toroid integrator between physical calibrations. A physical calibration of each toroid integrator will be 127 performedatataaminimum minimumofofevery everysix sixmonths monthsutilizing utilizing performed pulse generator generator and and oscilloscope. oscilloscope. The The gain gain and and aa pulse offset values values for for each each integrator integrator electronics electronics module module offset willbe beadjusted adjustedatatthat thattime timetotonull nullout outany anyerrors errorssince since will thelast lastcalibration. calibration. the Modification" form, form, (Radiation (Radiation Physics Physics Form Form #42), #42), Modification” will be be submitted submitted toto the the ES&H ES&H Section Section for for aa will preliminary design design approval. approval. Final Final approval approval will will be be preliminary requestedfrom from the theES&H ES&HSection Section upon upon submission submission ofof requested completedtest testresults. results. completed The comparator comparator module module trip trip functions functions will will be be The testedby byinputting inputtingknown knowndata datasignals signalsvia viaan anin-house in-house tested built test test unit. unit. The Thetest testunit unitwill willverify verify the thepulse-topulse-tobuilt pulse difference difference trip trip settings, settings, the the sum sum ofof the the last last 1010pulse event difference difference setting, setting, the the event event timing timing functions, functions, event andthe theinternal internalself-test self-testfunctions. functions. and ReviewStandards Standards Review The review review process process established established for for the the proposed proposed The design isis consistent consistent with with the the Fermilab Fermilab Work Work Smart Smart design Standardsset setand andthe theFRCM. FRCM. Standards ACKNOWLEDGMENTS ACKNOWLEDGMENTS ReviewProcess Process Review would like like toto thank thank Glen Glen Federwitz, Federwitz, Paul Paul II would Czarapata, Craig Craig Moore, Moore, Ralph Ralph Pasquinelli, Pasquinelli, James James Czarapata, Crisp,James JamesZagel, Zagel,Rick RickFord, Ford,Peter Peter Kasper, Kasper, Kamran Kamran Crisp, Vaziri, Michael Michael Gerardi, Gerardi, and and Daniel Daniel Johnson Johnson for for Vaziri, servingasasmembers membersofofthe theproject projectdesign designteam. team. serving The review review process process established established by by the the Beams Beams The Division Head Head isis toto produce produce aa design design with with the the joint joint Division inputs ofof the the Fermilab Fermilab ES&H ES&H Section, Section, the the RF&I RF&I inputs Instrumentation Engineering Engineering Group, Group, the the MiniBooNE MiniBooNE Instrumentation beamlinePhysicists, Physicists,and andthe theBD BDES&H ES&H Interlock Interlock and and beamline RadiationProtection ProtectionGroups. Groups. Upon Upon completion completion ofofan an Radiation approved design, design, the the standard standard “Request "Request for for Interlock Interlock approved E-Btmi Block DIngram FIGURE1.1. E-berm E-bermsystem systemblock blockdiagram diagram. FIGURE . 128 Pearson 3100 Torroid Integrator A Buffer 16 bit Data Word 1(H) 8 Bit Buffer 2(L) 8 Bit Buffer 3(H) 8 Bit Buffer 4(L) 8 Bit Buffer STB TRG Buffer IRM Both Add. & Data on 1, 37 pin D connector. Address on 1-8 Data on 9-16 8 Bit Data Word Intensity Compare Cal Pulse Wall Mon. Intensity Compare Self Test Compare Difference Engine Comp 6% 5(H) Buffer 6(L) Last 10 Sum Cal Unit Status 8 Bit Address 7 Manual Calibrate Manual Cal Trig “A” Event A Enable Enable Trig Trig Req Cal in progress Reset Enable STB “A” Resistive Wall Mon. Pearson 3100 Torroid Integrator B STB “B” Wall Mon itor “A” Comp 20% E rror Permit A Output Latch “A” Reset A 8(H) Buffer 16 bit Data Word 9(L) STB Buffer Intensity Compare Both Add. & Data on 1, 37 pin D connector. Address on 1-8 Data on 9-16 8 Bit Data Word 8 Bit Address Cal Pulse Wall Mon. Intensity Compare Self Test Compare Difference Engine Comp 6% Last 10 Sum Buffer Cal Unit 8 Bit Buffer 8 Bit Buffer 12(H) 8 Bit Buffer 13(L) 8 Bit Buffer Status Trig Trig Req Cal in pro gress Enable STB “A” STB “B” Manual Calibrat e “B” Manual Cal Trig B Event B Enable Enable Enable Reset Timing Enable Comp 20% Output Latch “B” 8 Bit Buffer 9 B it Bu ffer f or AART 9 Bit Buf fer f or Frnt P nl Enable Event “B” Resistive Wall Mon. 8 Bit Buffer 11(L) 14 Man ual Calibrat e 8 Bit Buffer 10(H) TRG IRM 9 Bit Buffer 9 Bit Buf fer for Frnt P nl Enable Event “A” 8 Bit Buffer 9 B it Bu ffer f or AART Enable Timing Event “B” 8 Bit Buffer Event “A” IRM Both Add. & Data on 1, 37 pin D connector. Address on 1-8 Data on 9-16 8 Bit Data Word 8 Bit Address Error Wall Monitor “B” Permit B Reset B FIGURE 2. 2. Interconnecting Interconnecting logic logic functions functions performed by the comparator module. FIGURE 129
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