vii
TABLE OF CONTENTS
CHAPTER
TITLE
PAGE
DECLARATION................................................................................. ii
DEDICATION.................................................................................... iii
ACKNOWLEDGEMENT ................................................................. iv
ABSTRACT ..........................................................................................v
ABSTRAK .......................................................................................... vi
TABLE OF CONTENTS ................................................................. vii
LIST OF TABLES ............................................................................ xii
LIST OF FIGURES ......................................................................... xiii
LIST OF ABBREVIATIONS ......................................................... xvi
LIST OF APPENDICES ................................................................ xvii
1 INTRODUCTION ...................................................................................................1
1.1 Research Background ......................................................................1
1.2 Project Background ..........................................................................2
1.3 Problem Statement ...........................................................................3
1.4 Objective ..........................................................................................4
1.5 Scope of Work .................................................................................4
1.6 Project Schedule...............................................................................4
1.7 Report Outline ..................................................................................4
1.8 Summary of Chapter 1 .....................................................................5
viii
2 LITERATURE REVIEW .......................................................................................6
2.1 Procedure Identification ...................................................................6
2.2 Instruction Set Architecture (ISA) ...................................................7
2.2.1 Complex Instruction Set Computer (CISC) ......................7
2.2.2 Reduced Instruction Set Computer (RISC).......................8
2.2.3 Instruction Usage ..............................................................9
2.3 Load/Store Architecture .................................................................10
2.4 Pipelining .......................................................................................11
2.5 Pipeline Hazard ..............................................................................13
2.5.1 Structural Hazard ............................................................13
2.5.2 Data Hazard ....................................................................13
2.5.3 Control Hazard ................................................................14
2.6 Processor Resources.......................................................................14
2.6.1 Incrementer .....................................................................15
2.6.2 Program Counter .............................................................15
2.6.3 Link Register ...................................................................15
2.6.4 Instruction Memory ........................................................15
2.6.5 Instruction Register .........................................................16
2.6.6 Register File ....................................................................16
2.6.7 Barrel Shifter ...................................................................16
2.6.8 Arithmetic and Logic Unit ..............................................16
2.6.9 Status Register ................................................................17
2.6.10 Data Memory ................................................................17
2.6.11 Control Unit ..................................................................17
2.6.12 Data Bus ........................................................................17
2.6.13 Address Bus ..................................................................18
2.6.14 Control Bus ...................................................................18
2.6.15 Pipeline Register ...........................................................18
2.7 Previous Work ...............................................................................18
2.8 Jurij Silc, Advanced Processor Architecture .................................18
2.8.1 V. Heuring and H. Jordan Computer Systems Design
and Architecture ......................................................................20
ix
2.8.2 VHDL Design of A 32-bit RISC Processor Core for
FPGA Implementation .............................................................21
2.8.3 The RTL Design of 32-bit 5-stage Pipeline RISC
Processor Using Verilog HDL .................................................23
2.9 Introduction to ARM Architecture.................................................27
2.10 Summary of Chapter 2 .................................................................28
3 METHODOLOGY AND PRECEDURES ..........................................................29
3.1 Methodology ..................................................................................29
3.2 Research Flow and Methodology ..................................................30
3.3 Design Flow and Methodology......................................................32
3.4 Summary of Chapter 3 ...................................................................36
4 RESULT AND DISCUSSION ..............................................................................37
4.1 Processor Top Level Design ..........................................................37
4.2 Processor Design Specification......................................................40
4.3 Processor Resources.......................................................................42
4.3.1 Clock ...............................................................................42
4.3.2 Incrementer .....................................................................43
4.3.3 Program Counter .............................................................45
4.3.4 Link Register ...................................................................46
4.3.5 Instruction Memory ........................................................48
4.3.6 Instruction Register .........................................................50
4.3.7 Register File ....................................................................51
4.3.8 Barrel Shifter ...................................................................54
4.3.8.1 Logical Shift Left .....................................................................56
4.3.8.2 Logical Shift Right ...................................................................57
4.3.8.3 Arithmetic Shift Right..............................................................59
4.3.8.4 Rotate Right .............................................................................60
4.3.8.5 Rotate Right Extended .............................................................62
4.3.9 Arithmetic Logic Unit .....................................................63
4.3.10 Current Program Status Register ..................................65
4.3.11 Data Memory ................................................................66
x
4.4 Instruction Set Architecture and Format ........................................68
4.4.1 Data Processing ...............................................................68
4.4.2 Single Data Transfer .......................................................71
4.4.3 Branch .............................................................................74
4.5 ASM Flowchart ..............................................................................74
4.6 Datapath Unit Design .....................................................................77
4.7 Control Unit Design .......................................................................79
4.8 myARM RISC Processor Core Architecture .................................81
4.9 Processor Validation ......................................................................83
4.10 Design Optimization and Performance Analysis .........................85
4.10.1 Maximum Operating Frequency ...................................85
4.10.2 Critical Path Delay ........................................................85
4.10.3 Throughput ....................................................................86
4.10.4 Latency..........................................................................86
4.10.5 Resource Utilization......................................................86
4.11 Summary of Chapter 4 .................................................................87
5 CONCLUSION ......................................................................................................88
5.1 Limitation of the Processor Core ...................................................88
5.2 Project Conclusion .........................................................................88
5.3 Future Works .................................................................................89
5.3.1 Pipeline Hazard Handling ...............................................89
5.3.2 Interrupt Capability .........................................................89
5.3.3 Multiplier and Divisor Design ........................................90
5.3.4 Assembler Compatibility ................................................90
5.3.5 Implementation on FPGA ...............................................90
5.3.6 Memory Extension ..........................................................90
5.3.7 Extending the Instruction ................................................91
5.3.8 Cache Memory Architecture ...........................................91
5.3.9 Interfacing with Co-Processor ........................................92
5.3.10 I/O System ....................................................................92
5.4 Summary of Chapter 5 ...................................................................92
xi
REFERENCES ...........................................................................................................93
Appendix A ..............................................................................................................96
xii
LIST OF TABLES
TABLE NO.
TITLE
PAGE
4.1
Register file operation ..........................................................................54
4.2
Barrel shifter operation ........................................................................55
4.3
Logical shift left operation barrel shifter .............................................57
4.4
Logical shift right operation barrel shifter ...........................................59
4.5
Arithmetic shift right operation barrel shifter ......................................60
4.6
Rotate right operation of barrel shifter.................................................61
4.7
Rotate right extended operation of barrel shifter .................................63
4.8
Arithmetic and logic unit operation .....................................................64
4.9
Condition flags .....................................................................................65
4.10
Instruction set and format ....................................................................68
4.11
Data processing instruction ..................................................................70
4.12
RTL notation for single data transfer operation ...................................73
4.13
Pipeline stages ......................................................................................77
4.14
Hardware for pipeline stages ...............................................................78
4.15
Pipeline validation ...............................................................................85
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LIST OF FIGURES
FIGURE NO.
TITLE
PAGE
2.1
Basic 5-stage pipeline structure ...........................................................12
2.2
5-stage pipeline structure by Jurij Silc .................................................19
2.3
5-stage pipeline structure by V. Heuring .............................................20
2.4
VHDL Design of A 32-bit RISC Processor Core ................................22
2.5
Top level architecture ..........................................................................24
2.6
Datapath unit design and the interconnection ......................................25
2.7
ARM7TDMI core architecture ............................................................28
3.1
Project Methodology............................................................................29
3.2
Research Methodology ........................................................................30
3.3
Experiment on memory’s timing performance ....................................31
3.4
RTL Design Flow ................................................................................32
3.5
Hierarchical Modularity of RTL Design Methodology .......................34
3.6
RTL Design Methodology ...................................................................35
4.1
Selected blocks from ARM7TDMI core architecture ..........................38
4.2
Hierarchical modularity of processor design .......................................39
4.3
Hierarchical modularity of processor design .......................................40
4.4
Clocking design ...................................................................................43
4.5
Incrementer design ...............................................................................44
4.6
Incrementer simulation result ..............................................................44
4.7
Program counter design .......................................................................45
4.8
Output waveform program counter simulation ....................................46
4.9
Link register design..............................................................................47
4.10
Register instantiation module ..............................................................48
xiv
4.11
Instruction memory design ..................................................................49
4.12
Memory initialization file ....................................................................49
4.13
Output waveform of instruction memory simulation...........................50
4.14
Output waveform of instruction memory simulation...........................50
4.15
Register file design ..............................................................................51
4.16
Register file organization .....................................................................52
4.17
Register file organization .....................................................................53
4.18
Barrel shifter design .............................................................................55
4.19
Output waveform of logical shift left operation ..................................56
4.20
Output waveform of logical shift right operation ................................58
4.21
Output waveform of arithmetic shift right operation ...........................59
4.22
Output waveform of rotate right operation ..........................................61
4.23
Output waveform of rotate right extended operation ...........................62
4.24
Arithmetic and logic unit design ..........................................................64
4.25
Current Program Status Register design ..............................................65
4.26
Comparing the condition field with CPSR ..........................................66
4.27
Data Memory design ............................................................................67
4.28
Store and load instructions ...................................................................67
4.29
Data processing instruction binary encoding .......................................69
4.30
Shift operation binary encoding ...........................................................70
4.31
Single data transfer binary encoding....................................................71
4.32
Branch instruction binary encoding .....................................................74
4.33
Algorithmic State Machine ..................................................................75
4.34
Processor’s state transition ...................................................................76
4.35
Datapath unit design ............................................................................78
4.36
Top level design of datapath unit .........................................................79
4.37
Control unit design ...............................................................................80
4.38
Conceptual design of myAR ................................................................81
4.39
myARM core architecture....................................................................82
4.40
Test program ........................................................................................83
4.41
Output waveform of pipeline verification............................................84
4.42
Critical path delay ................................................................................85
4.43
Resource Usage ....................................................................................86
xv
5.1
ARM7 instruction set and format ........................................................91
xvi
LIST OF ABBREVIATIONS
RISC
-
Reduced Instruction Set Computer
CISC
-
Complex Instruction Set Computer
SoC
-
System-on-Chip
ISA
-
Instruction Set Architecture
PC
-
Program Counter
OPCODE
-
Operation Code
xvii
LIST OF APPENDICES
APPENDIX
A
TITLE
PAGE
VERILOG CODE ................................................................................96