vii
TABLE OF CONTENTS
CHAPTER
1
2
TITLE
PAGE
DECLARATION
ii
DEDICATION
iii
ACKNOWLEDGEMENT
iv
ABSTRACT
v
ABSTRAK
vi
TABLE OF CONTENTS
vii
LIST OF TABLES
xii
LIST OF FIGURES
xiii
LIST OF ABBREVIATIONS
xvii
LIST OF APPENDICES
xviii
INTRODUCTION
1
1.1
Introduction to Digital Filter
1
1.2
Introduction to FPGA
4
1.3
Project Motivations and Objectives
5
1.4
Scope of Work
6
LITERATURE RESEARCH
8
2.1.
Principle of Filter Operations
2.2.
Quantization and Finite Wordlength Effects
11
2.3.
FPGA Implementations
16
2.3.1
19
Baugh-Wooley Multiplier
8
2.4.
Biquad Block of a Digital Filter
20
2.5.
Biquad Architecture Implementations
22
viii
2.6.
3
Fully Combinational
23
2.5.2
Combinational-Sequential Implementation
24
2.5.3
Word-serial Implementation
25
2.5.4
Bit-serial Implementation
26
Optimization using Bit Serial Arithmetic
29
METHODOLOGY AND IMPLEMENTATION PLAN
31
3.1.
IIR Digital Filter Design Considerations
31
3.2.
Bit-true Model Realization
33
3.2.1
Filter Response Simulation
34
3.2.2
Coefficient Quantization
35
3.2.3
Intermediate Wordlength
36
3.2.4
Bit true Filter Modelling
38
3.3.
4
2.5.1
FPGA Implementations
41
3.3.1
Biquad Architecture Implementation in FPGA 42
3.3.2
Lookup Table Implementation in FPGA
42
3.4.
Design Optimization
44
3.5.
IIR Bandstop Filter Specification
45
DESIGN AND MODELING
4.1
High Level Design of Biquad IIR Filter
48
48
4.1.1 Synchronous Dataflow Graph (SDFG) of IIR
Filter
4.2.
Fully-Combinational Biquad Model
49
50
4.2.1 Scheduling and RTL Code of Fully
Combinational Model
50
4.2.2 Algorithm and ASM-Chart of Fully
Combinational Model
51
4.2.3 Datapath Unit (DU) Design using General
Multiplier
4.2.4 Baugh-Wooley Multiplier
52
53
4.2.5 Datapath Unit (DU) Design using BaughWooley Multiplier
56
4.2.6 Verilog Coding of Fully Combinational Model 56
ix
4.3
Combinational-Sequential Biquad Model
57
4.3.1 Scheduling and RTL code of CombinationalSequential Model
57
4.3.2 ASM-Chart of Combinational-Sequential
Model
58
4.3.3 Datapath Unit (DU) Design
59
4.3.4 Control Unit (CU) Design
61
4.3.5 Top level Design of Combinational-Sequential
Model
63
4.3.6 Verilog Coding of Combinational-Sequential
Model
4.4
4.5
63
Bit-Serial Biquad Model
64
4.4.1
ASM Chart of Bit-Serial Model
64
4.4.2
Bit-Serial Building Blocks
66
4.4.2.1
66
Bit-Serial Adder
4.4.2.2 Bit-Serial Two’s Complementor
67
4.4.2.3 Serial by Parallel Multiplier (SPM)
67
4.4.2.4 Bit-Serial Subtractor
69
4.4.3 Datapth Unit Design
69
4.4.4 Control Unit Design
71
4.4.5 Top level Design
72
4.4.6 Verilog Coding of Bit-Serial Model
73
Bit-Serial Arithmetic Model using Lookup Tables
73
4.5.1 Algorithm of Lookup Tables
74
4.5.2 ASM-Chart of Bit-Serial Arithmetic using
Lookup Tables
75
4.5.3 Datapath Unit Design
76
4.5.4 Verilog Coding of Bit-Serial Arithmetic using
Lookup Table
5
RESULTS AND DISCUSSION
5.1
Quantization Effect of Digital Filter
76
77
77
5.1.1 Simulation Results of Quantization Comparison 78
x
5.1.2 Discussion on Quantization Effect of Digital
Filter
80
5.2
Filter Verification Using MATLAB simulation
80
5.3
Verification Using TestBench
82
5.3.1 Verilog Coding of TestBench for Biquad IIR
Bandstop Filter
5.4.
83
Simulation Results of Fully-Combinational Biquad
Model
84
5.4.1 Simulation Result of Fully-Combinational
Model using General Multiplier
84
5.4.2 Simulation Result of Baugh Wooley Multiplier 85
5.4.3 Simulation Result of Fully Combinational
Model using Baugh Wooley Multiplier
5.4.4 Discussion on Fully-Combinational Model
5.5.
87
88
Simulation Results of Combinational-Sequential
Biquad Model
89
5.5.1 Simulation Result of Datapath Unit in
combinational-sequential Biquad Model
89
5.5.2 Simulation Result of Control Unit in
Combinational-Sequential Model
90
5.5.3 Simulation Results of Top-Level of
Combinational-Sequential Model
90
5.5.4 Discussion on Combinational-Sequential
Model
5.6.
91
Simulation Results of Bit-Serial Biquad Model
92
5.6.1 Simulation Result of Bit-serial Adder
92
5.6.2 Simulation Result of Bit-Serial Two’s
Complementor
93
5.6.3 Simulation Result of Serial Parallel Multiplier
(SPM)
94
5.6.4 Datapath Unit Simulation Results
95
5.6.5 Simulation Result of Control Unit
95
5.6.6 Top Level Simulation Results
96
5.6.7 Discussion on Bit-Serial Model
96
xi
5.7.
Simulation Result of Bit-Serial Arithmetic using
Lookup Tables
97
5.7.1 Simulation Results
97
5.7.2 Discussion on Bit-Serial Arithmetic using
LUT
98
5.8.
Summary of Comparison
104
5.9.
Design Challenges
105
5.9.1 Rounding Issue
105
5.9.2 Bit-order in Bit-Serial Implementation
106
5.9.3 Delay Element in Bit-Serial Arithmetic using
LUT
6
106
CONCLUSION AND FUTURE RECOMMENDATIONS 107
6.1.
Conclusion
107
6.2.
Future Recommendations
108
REFERENCES
Appendices A - F
109
112 - 146
xii
LIST OF TABLES
TABLE NO.
3.1
TITLE
PAGE
Bandstop Filter Quantized Coefficient Values Floatingpoint to Fixed point conversion
46
4.1
Two’s complement and one’s complement representations
53
4.2
Datapath Unit Assigned Register Arithmetic Operations
60
4.3
RTL-CS for the Combinational Sequantial Control Unit
62
4.4
RTL-CS for the Bit Serial Control Unit
71
5.1
Performance Analysis of Fully-Combinational using
General Multipliers
85
Performance Analysis of Fully-Combinational using BW
Multipliers
87
Comparison of performance of fully combinational model
using general purpose multiplier and Baugh Wooley
multiplier
88
5.4
Performance Analysis of Combinational-Sequential Model
91
5.5
Bit-wise operation of bit-serial adder
92
5.6
Performance Analysis of Combinational-Sequential Model
96
5.7
LUT Values Used During Bit Serial Filter Operation
99
5.8
Summary of Comparison of Different Models of Design
104
5.2
5.3
xiii
LIST OF FIGURES
FIGURE NO.
TITLE
PAGE
1.1
Block Diagram of a Digital Filter
2
1.2
Internal structure of a generic FPGA (courtesy Xilinx, Inc.)
5
2.1
Time and frequency Domain Response of a Bandpass Filter
9
2.2
Template of a Band-stop Filter
10
2.3
An ADC-based digital conversion system
12
2.4
A saturating arithmetic operational behavior
13
2.5
Truncation vs. rounding in fixed-point representation
13
2.6
Arithmetic Error in a fixed-point MAC unit
14
2.7
Frequency of a FIR with coefficients determined using SA
15
2.8
(a) SFG & (b) DFG of a DSP recursion y(n) = ay(n − 1) + x(n)
17
2.9
Example of (a) before (b) after pipelining
17
2.10
IIR filter with look-ahead arithmetic
18
2.11
The parametric biquad (second-order) building block
22
2.12
Fully combinational implementation of a biquad system
23
2.13
Scheduling of combinational implementation
24
2.14
Combinational-sequential implementation of a biquad system
24
2.15
Scheduling diagram of combinational-sequential implementation 25
2.16
Word-serial Implementation
26
2.17
Bit-serial Implementation of a biquad section
26
2.18
Scheduling of bit-serial implementation with 16 bit coefficient
length and 20-bit internal data path
27
2.19
Bit Serial Adder
27
2.20
Bit-serial multiplier for three-bit numbers
28
2.21
IIR Digital Filter using Bit-Serial Arithmetic Architecture
30
3.1
A fixed-point filter design procedure
32
xiv
3.2
GUI of FDA tool
34
3.3
Quantization of Filter Coefficient in FDA Tool
36
3.4
Nodes at the biquad to find maximum swing shown by arrow
37
3.5
Coefficient scaling in FDA tool
37
3.6
Filter intermediate word length specification in FDA tool
38
3.7
Direct-Form II, Second Order Sections filter structure
39
3.8
Bit-True model of the filter in Simulink
40
3.9
Look up (LUT) implementation of a digital filter
43
3.10
Filter Designed in FDA Tool
45
3.11
FDA Tool Generated Coefficients
45
3.12
FDA Tool Generated Quantized Coefficients
46
3.13
Fixed Point Coefficients stored in RF.mif
47
4.1
SDFG of biquad bandstop IIR filter
49
4.2
Scheduling and RTL code of fully combinational model
50
4.3
ASM Chart for Fully Combinational Model
51
4.4
Functional Block Diagram of Fully Combinational Model
52
4.5
Tabular form of bit-level Baugh Wooley Multiplication
54
4.6
Functional block diagram of 16-bits Baugh Wooley Multiplier
55
4.7
Functional Block Diagram of Fully Combinational Model
using Baugh-Wooley Multipliers
56
4.8
Scheduling and RTL code of Combinational-Sequential
57
4.9
ASM Chart for Combinational-Sequential Model
58
4.10
Datapath functional block diagram for Combinational-Sequential
Model
59
4.11
Top Level Unit of Combinational-Sequential Biquad Model
63
4.12
ASM chart of Bit-Serial Model
65
4.13
Functional block diagram of bit-serial adder
66
4.14
Bit-Serial Two’s Complementor
67
4.15
Functional block diagram of Serial Parallel Multiplier (SPM)
68
4.16
Bit Serial Subtractor
69
4.17
Functional Block diagram of DU
70
4.18
Top Level Unit of Bit-Serial Biquad Model
72
4.19
ASM Chart for Bit Serial Biquad using LUT
75
xv
4.20
Functional block diagram for Bit-Serial Biquad Using Lookup
Table
76
5.1
Magnitude response of a bandstop IIR Filter (reference filter)
78
5.2
Magnitude and phase responses of reference IIR filter and
quantized filter with 4 bits word length for filter coefficients
5.3
Magnitude and phase responses of reference IIR filter and
quantized filter with 7 bits word length for filter coefficients
5.4
79
Magnitude and phase responses of reference IIR filter and
quantized filter with 8 bits word length for filter coefficients
5.5
78
79
Magnitude and phase responses of reference IIR filter and
quantized filter with 16 bits word length for filter coefficients
79
5.6
Magnitude Response of Biquad IIR Bandstop Filter
81
5.7
Input Signal of 10kHz and 12kHz Sinusoids
81
5.8
Filtered Bandstop Signal
82
5.9
TestBench Simulation in ModelSim
83
5.10
TestBench Expected Input and Output Values (hex)
83
5.11
Simulation results of fully-combinational biquad model using
general purpose multipliers
84
5.12
Simulation result of 16-bits BW multiplier
86
5.13
Simulation result of 8-bits BW multiplier
86
5.14
Simulation results of fully-combinational biquad model using
Baugh-Wooley Multipliers
5.15
Simulation Results of Datapath Unit of CombinationalSequential Biquad Model
5.16
89
Simulation Results of Control Unit of Combinational-Sequential
Biquad Model
5.17
87
90
Top Level Simulation Results of Combinational-Sequential
Biquad Model
90
5.18
Simulation result of bit-serial adder
92
5.19
Simulation result of bit-serial two’s complementor
93
5.20
Simulation result of serial-parallel multiplier
94
5.21
Simulation Result of Datapath Unit of Bit-Serial
95
5.22
Simulation Result of CU of Bit-Serial model
95
5.23
Simulation result of top-level of bit-serial model
96
xvi
5.24
Simulation Results of Bit-Serial Arithmetic using Lookup Table 97
5.25
Simulation result of first stage in bit-serial arithmetic using
lookup table
5.26
Simulation result of second stage of bit-serial arithmetic using
lookup table
5.27
5.29
101
Simulation result of third stage of bit-serial arithmetic using
lookup table
5.28
100
102
Simulation result of negative numbers of bit-serial arithmetic
using lookup table
103
Difference of one between expected and simulated value
105
xvii
LIST OF ABBREVIATIONS
ADC
-
Analog-to-Digital Converter
ASIC
-
Application-specific Integrated Circuit
BW
-
Baugh-Wooley
CU
-
Control Unit
DU
-
Datapath Unit
DAC
-
Digital-to-Analog Converter
DSP
-
Digital Signal Processing
FIR
-
Finite Impulse Response
FPGA
-
Field-programmable Gate Array
FT
-
Fourier Transform
GUI
-
Graphical User Interface
HDL
-
Hardware Descriptive Language
IIR
-
Infinite Impulse Response
LTI
-
Linear Time Invariant
LSB
-
Least Significant Bit
LUT
-
Look-up
MAC
-
Multiplication-Accumulation Unit
MSB
-
Most Significant Bit
RAM
-
Random Access Memory
RTL
-
Register-transfer Level
SA
-
Simulated Annealing
SNR
-
Signal-to-noise Ratio
VLSI
-
Very-Large-Scale Integration
xviii
LIST OF APPENDICES
APPENDIX
A-1
TITLE
PAGE
Verilog program of Fully Combinational
(General multiplier)
112
Verilog program of Fully Combinational (BW
multiplier)
114
A-3
Verilog program of 16-bits BW Multiplier
116
B-1
Verilog program of Datapath Unit (DU) for
Combinational- Sequential Model
121
Verilog program of Control Unit (CU) for
Combinational- Sequential Model
123
Verilog program of Top-Level for CombinationalSequential Model
124
Verilog program of Datapath Unit (DU) for BitSerial Model
125
Verilog program of Control Unit (CU) for Bit-Serial
Model
127
C-3
Verilog program of Top-Level for Bit-Serial Model
128
C-4
Verilog program of Bit-Serial Adder
129
C-5
Verilog program of Bit-Serial Two’s Complementor
130
C-6
Verilog program of Serial-Parallel Multiplier
131
C-7
Verilog program of Bit-Serial Subtractor
132
A-2
B-2
B-3
C-1
C-2
xix
C-8
Verilog program of Bit-Serial Delay
133
C-9
Verilog program of Shift-Registers
134
D-1
Verilog program of Bit-Serial Arithmetic using LUT
135
D-2
Perl-Script of LUT Generator
138
E-1
Matlab Code for Biquad IIR Bandstop Filter
140
F-1
Testbench for Biquad IIR Bandstop Filter
141