vii
TABLE OF CONTENTS
CHAPTER
1
2
TITLE
PAGE
DECLARATION
ii
DEDICATION
iii
ACKNOWLEDGEMENT
iv
ABSTRACT
v
ABSTRAK
vi
TABLE OF CONTENTS
vii
LIST OF TABLES
x
LIST OF FIGURES
xi
LIST OF ABBREVIATIONS
xii
INTRODUCTION
1
1.1
Background
1
1.2
Motivation and Problem Statement
3
1.3
Objectives
7
1.4
Scope of Work
8
1.5
Report Outline
9
LITERATURE REVIEW AND THEORY
11
2.1
Semiconductor diagnosis
11
2.1.1
Semiconductor diagnosis algorithms
12
2.1.1.1 Cause-effect Analysis
13
2.1.1.2 Effect-cause Analysis
14
2.1.1.3 Structural Pruning
14
viii
2.1.1.4 Backtracing
14
2.1.1.5 Inject-and-Evaluate
15
2.1.2
Ranking Metrics
16
2.1.3
Efforts to Improve Diagnostic Resolution
16
2.1.3.1 Diagnostic Fault Models
16
2.1.3.2 Multiple Fault Types
17
2.1.3.3 Same/different Fault Dictionary
18
2.1.3.4 Layout Data to Filter Bridge Defects
18
2.1.3.5 Diagnostic Test Pattern Generation
19
2.1.3.6 Test Point Insertion
19
2.1.3.7 Diagnosis Resolution Improvements
19
Summary
2.2
3
Photoemission Infrared Microscopy
20
2.2.1
21
IREM Logic State Imaging
2.3
Binary Search
22
2.4
Graph Theory and Partitioning
23
2.4.1
Weighted Graphs
23
2.4.2
Hypergraphs
24
2.4.3
Partitioning Algorithms
24
METHODOLOGY
27
3.1
Determining Probe Location
29
3.1.1
Parse Diagnosis Report File
29
3.1.2
Fanin and Graph Generation
30
3.1.3
Graph Pruning
30
3.1.4
Gate Dropping
31
3.1.5
Gate Location Extraction
31
3.1.6
Assigning Weights to Vertices
32
3.1.7
Graph Bisection
33
3.1.8
Probe Frame Determination
34
ix
4
IMPLEMENTATION
35
4.1
Parse Diagnosis Report File
35
4.2
Fanin and Graph Generation
35
4.3
Graph Pruning
36
4.4
Gate Dropping
36
4.5
Assigning Weights to Vertices
37
4.6
Graph Bisection
37
4.7
Probe Frame Determination
38
4.8
Compute Resources
38
4.9
Experimental Setup
39
5
RESULTS
40
6
DISCUSSION
46
7
CONCLUSION AND FUTURE DIRECTION
48
7.1
Conclusion
48
7.2
Future Direction
49
REFERENCES
51
x
LIST OF TABLES
TABLE NO.
5.1
TITLE
Weighted bisection, highly constrained partitioning
PAGE
41
(UBfactor = 1)
5.2
Weighted bisection, unconstrained partitioning
41
(UBfactor = 40)
5.3
Unweighted bisection, highly constrained partitioning
42
(UBfactor = 1)
5.4
Unweighted bisection, unconstrained partitioning
43
(UBfactor = 40)
5.5
Baseline data, greedy probe algorithm to determine
44
probe frames
5.6
Comparison of iterative methods
45
xi
LIST OF FIGURES
FIGURE NO.
TITLE
PAGE
1.1
Manufacturing-yield analysis-FI/FA feedback loop
2
1.2
Resolution vs. effort in defect isolation techniques
4
1.3
Typical fault isolation flow
6
1.4
Iterative diagnosis workflow
8
2.1
Moore’s law
12
2.2
Diagnosis fault models used by Poirot [8]
17
2.3
Net fault combining stuck-at equivalences [8]
17
2.4
Filtering faults A-E, B-E, D-F with layout data
18
2.5
Inverter chain
20
2.6
IREM emission image showing interpreted logic values [22]
22
2.7
A graph bisection (k=2)
23
2.8
Steps in coarsening using the MHEC algorithm
25
2.9
Multilevel paradigm towards graph partitioning [27]
25
3.1
Iterative diagnosis workflow
28
3.2
Probe point determination
29
3.3
Candidate cover
29
3.4
Graph after dropping all gates except inverters
31
3.5
Greedy algorithm choosing 3 probe frames from 5 probe
34
points
xii
LIST OF ABBREVIATIONS
ATE
-
Automated Test Equipment
CAD
-
Computer Aided Design
CUT
-
Circuit Under Test
DTPG
-
Diagnostic Test Pattern Generation
DUT
-
Device Under Test
FA
-
Failure Analysis
FI
-
Fault Isolation
FM
-
Fidduccia-Mattheyses algorithm
IREM
-
Infrared Emission Microscopy
LADA
-
Laser Assisted Device Alteration
LSI
-
Logic State Imaging
LVI
-
Laser Voltage Imaging
LVP
-
Laser Voltage Probing
LVS
-
Layout vs. Schematic verification
MHEC
-
Modified Hyperedge Coarsening algorithm
MLFM
-
Multilevel Fiduccia-Mattheyses algorithm
MOSFET
-
Metal-Oxide-Semiconductor Field Effect Transistor
NMOS
-
N-type Metal-Oxide-Semiconductor Transistor
NP
-
Nondeterministic Polynomial Time
PEM
-
Photon Emission Microscopy
PFA
-
Physical Failure Analysis
PICA
-
Picosecond Imaging Circuit Analysis
PMOS
-
P-type Metal-Oxide-Semiconductor Transistor
xiii
LIST OF ABBREVIATIONS
RAM
-
Random Access Memory
ROI
-
Region Of Interest
SA
-
Stuck At
SEM
-
Scanning Electron Microscopy
SRAM
-
Static Random Access Memory
TCL
-
Tool Control Language
TEM
-
Transmission Electron Microscopy
TRE
-
Time Resolved Emission
XML
-
Extended Markup Language
XPath
-
XML Path Language