Intel® Stratix 10 Device Datasheet
S10-DATASHEET
2017.05.08
Contents
Contents
Stratix® 10 Device Datasheet..................................................................................................................................................... 3
Electrical Characteristics...................................................................................................................................................... 3
Operating Conditions.................................................................................................................................................. 4
Switching Characteristics....................................................................................................................................................19
L-Tile Transceiver Performance Specifications............................................................................................................... 20
H-Tile Transceiver Performance Specifications.............................................................................................................. 27
E-Tile Transceiver Performance Specifications...............................................................................................................34
Core Performance Specifications.................................................................................................................................37
Periphery Performance Specifications.......................................................................................................................... 43
HPS Performance Specifications - Preliminary ..............................................................................................................51
Configuration Specifications................................................................................................................................................ 79
POR Specifications....................................................................................................................................................79
External Configuration Clock Source Requirements....................................................................................................... 79
JTAG Configuration Timing.........................................................................................................................................80
AS Configuration Timing............................................................................................................................................81
Avalon-ST Configuration Timing................................................................................................................................. 82
NAND Configuration Timing....................................................................................................................................... 84
SD/MMC Configuration Timing....................................................................................................................................90
Initialization............................................................................................................................................................ 91
Configuration Bit Stream Sizes...................................................................................................................................91
Minimum Configuration Time Estimation......................................................................................................................92
I/O Timing....................................................................................................................................................................... 94
Glossary.......................................................................................................................................................................... 94
Document Revision History................................................................................................................................................. 98
Intel® Stratix 10 Device Datasheet
2
Stratix® 10 Device Datasheet
Stratix® 10 Device Datasheet
This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing for
Stratix® 10 devices.
Table 1.
Stratix 10 Device Grades and Speed Grades Supported
Device Grade
Speed Grade Supported
Extended
•
•
•
•
•
–E1V (fastest)
–E2V
–E2L
–E3V
–E3X
Industrial
•
•
•
•
•
–I1V
–I2V
–I2L
–I3V
–I3X
The suffix after the speed grade denotes the power options offered in Stratix 10 devices.
•
V—SmartVID with standard static power
•
L—0.85 V fixed voltage with low static power
•
X—0.80 V fixed voltage with lowest static power
Electrical Characteristics
The following sections describe the operating conditions and power consumption of Stratix 10 devices.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no
responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by
Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
Stratix® 10 Device Datasheet
Operating Conditions
Stratix 10 devices are rated according to a set of defined parameters. To maintain the highest possible performance and
reliability of the Stratix 10 devices, you must consider the operating requirements described in this section.
The Maximum Allowed Overshoot During Transitions specifications will be available in a future release of the Stratix 10 Device
Datasheet.
Absolute Maximum Ratings
This section defines the maximum operating conditions for Stratix 10 devices. The values are based on experiments
conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the
device is not implied for these conditions.
Caution:
Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device.
Table 2.
Absolute Maximum Ratings for Stratix 10 Devices—Preliminary
Symbol
Description
Condition
Minimum
Maximum
Unit
VCC
Core voltage power supply
—
–0.50
1.26
V
VCCP
Periphery circuitry and transceiver fabric interface power supply
—
–0.50
1.26
V
VCCERAM
Embedded memory and digital transceiver power supply
—
–0.50
1.24
V
VCCPT
Power supply for programmable power technology and I/O pre-driver
—
–0.50
2.46
V
VCCBAT
Battery back-up power supply for design security volatile key register
—
–0.50
2.46
V
VCCIO_SDM
Configuration pins power supply
—
–0.50
2.46
V
VCCIO
I/O buffers power supply
–0.50
4.10
V
–0.50
2.46
V
V
3 V I/O
LVDS I/O
1
VCCA_PLL
Phase-locked loop (PLL) analog power supply
—
–0.50
2.46
VCCT_GXB
Transmitter analog power supply
—
–0.50
1.47
V
continued...
1 The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
Intel® Stratix 10 Device Datasheet
4
Stratix® 10 Device Datasheet
Symbol
Description
Condition
Minimum
Maximum
Unit
VCCR_GXB
Receiver analog power supply
—
–0.50
1.47
V
VCCH_GXB
Transmitter output buffer power supply
—
–0.50
2.46
V
VCCL_HPS
HPS core voltage and periphery circuitry power supply
—
–0.50
1.30
V
LVDS I/O
1
VCCIO_HPS
HPS I/O buffers power supply
–0.50
2.46
V
VCCPLL_HPS
HPS PLL power supply
—
–0.50
2.46
V
IOUT
DC output current per pin
—
–25
40
mA
TJ
Operating junction temperature
—
–55
125
°C
TSTG
Storage temperature (no bias)
—
–65
150
°C
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal
is equivalent to 100% duty cycle.
For example, a signal that overshoots to 2.70 V for LVDS I/O can only be at 2.70 V for ~4% over the lifetime of the device.
Table 3.
Maximum Allowed Overshoot During Transitions for Stratix 10 Devices—Preliminary
This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. The LVDS I/O values
are applicable to the VREFP_ADC and VREFN_ADC I/O pins.
Symbol
Description
Condition (V)
LVDS I/O
Vi (AC)
AC input voltage
2
Overshoot Duration as % at TJ = 100°C
Unit
3 V I/O
2.50
3.80
100
%
2.55
3.85
42
%
2.60
3.90
18
%
continued...
2 The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
Intel® Stratix 10 Device Datasheet
5
Stratix® 10 Device Datasheet
Symbol
Description
Condition (V)
LVDS I/O
2
Overshoot Duration as % at TJ = 100°C
Unit
3 V I/O
2.65
3.95
9
%
2.70
4.00
4
%
> 2.70
> 4.00
No overshoot allowed
%
Recommended Operating Conditions
This section lists the functional operation limits for the AC and DC parameters for Stratix 10 devices.
Recommended Operating Conditions
Table 4.
Recommended Operating Conditions for Stratix 10 Devices—Preliminary
This table lists the steady-state voltage values expected for Stratix 10 devices. Power supply ramps must all be strictly monotonic, without plateaus.
Symbol
VCC
VCCP
Description
Core voltage power supply
Periphery circuitry and transceiver fabric
interface power supply
Condition
Minimum
3
Typical
Maximum
3
Unit
–E1V, –I1V, –E2V, –I2V, –E3V,
–I3V 4
0.77 – 0.91
0.8 – 0.94
0.83 – 0.97
V
–E2L, –I2L
0.82
0.85
0.88
V
–E3X, –I3X
0.77
0.8
0.83
V
–E1V, –I1V, –E2V, –I2V, –E3V,
–I3V 4
0.77 – 0.91
0.8 – 0.94
0.83 – 0.97
V
–E2L, –I2L
0.82
0.85
0.88
V
–E3X, –I3X
0.77
0.8
0.83
V
continued...
2 The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
3 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the power distribution network (PDN) tool for the additional budget for the dynamic tolerance requirements.
4 SmartVID graded devices require the use of a configurable voltage regulator or system controller to receive the device’s settings
through PMBUS or PWM for proper performance.
Intel® Stratix 10 Device Datasheet
6
Stratix® 10 Device Datasheet
Symbol
Description
VCCIO_SDM
Configuration pins power supply
VCCPLLDIG_SDM
Condition
Minimum
3
Typical
Maximum
3
Unit
1.8 V
1.71
1.8
1.89
V
Secure Device Manager (SDM) block PLL digital
power supply
—
0.87
0.9
0.93
V
VCCPLL_SDM
SDM block PLL analog power supply
—
1.71
1.8
1.89
V
VCCFUSEWR_SDM
Fuse block writing power supply
—
2.35
2.4
2.45
V
VCCADC
ADC voltage sensor power supply
—
1.71
1.8
1.89
V
VCCERAM
Embedded memory and digital transceiver
power supply
0.9 V
0.87
0.9
0.93
V
Battery back-up power supply (For design
security volatile key register)
—
1.14
—
1.89
V
1.8 V
1.71
1.8
1.89
V
3.0 V (for 3 V I/O only)
2.85
3
3.15
V
2.5 V (for 3 V I/O only)
2.375
2.5
2.625
V
1.8 V
1.7
1.8
1.9
V
1.5 V
1.4
1.5
1.6
V
1.2 V
1.14
1.2
1.26
V
1.2 V
0.9
1.2
1.5
V
VCCBAT
5
VCCPT
Power supply for programmable power
technology and I/O pre-driver
VCCIO
I/O buffers power supply
VCCIO_UIB
Power supply for the Universal Interface Bus
between the core and embedded HBM2
memory
VCCM
Power supply for the embedded HBM2 memory
—
2.375
2.5
2.625
V
VCCA_PLL
PLL analog voltage regulator power supply
—
1.71
1.8
1.89
V
VREFP_ADC
Precision voltage reference for voltage sensor
—
1.2475
1.25
1.2525
V
continued...
3 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the power distribution network (PDN) tool for the additional budget for the dynamic tolerance requirements.
5 If you do not use the design security feature in Stratix 10 devices, connect VCCBAT to a 1.8 V power supply. Stratix 10 power-on reset
(POR) circuitry monitors VCCBAT.
Intel® Stratix 10 Device Datasheet
7
Stratix® 10 Device Datasheet
Symbol
VI
6
Description
DC input voltage
VO
Output voltage
TJ
Operating junction temperature
tRAMP
78910
Power supply ramp time
Condition
Minimum
3
Typical
Maximum
3
Unit
3 V I/O
–0.3
—
3.6
V
LVDS I/O
–0.3
—
2.46
V
—
0
—
VCCIO
V
Extended
0
—
100
°C
Industrial
–40
—
100
°C
Standard POR
200 μs
—
100 ms
—
3 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the power distribution network (PDN) tool for the additional budget for the dynamic tolerance requirements.
6 The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
7 This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL =
0 and tRAMP specifications for fast POR when HPS_PORSEL = 1.
8 tRAMP is the ramp time of each individual power supply, not the ramp time of all combined power supplies.
9 To support AS fast mode, all power supplies to the Stratix 10 device must be fully ramped-up within 10 ms to the recommended
operating conditions.
10 To support AS normal mode, VCCIO_SDM of the Stratix 10 device must be fully ramped-up within 10 ms to the recommended operating
condition.
Intel® Stratix 10 Device Datasheet
8
Stratix® 10 Device Datasheet
Transceiver Power Supply Operating Conditions
Table 5.
Transceiver Power Supply Operating Conditions for Stratix 10 GX/SX L- and H-Tile Devices—Preliminary
Symbol
VCCT_GXB[L,R]
Description
Transmitter power supply
Condition
Chip-to-Chip
13
11
Minimum
≤ 17.4 Gbps
12
Typical
Maximum
Unit
1.0
1.03
1.06
V
1.0
1.03
1.06
V
1.710
1.8
1.890
V
Or
Backplane 14 ≤ 12.5 Gbps
VCCR_GXB[L,R]
Receiver power supply
VCCH_GXB[L,R]
Transceiver high voltage power
Table 6.
13 ≤ 17.4 Gbps
Or
Backplane 14 ≤ 12.5 Gbps
Chip-to-Chip
—
Transceiver Power Supply Operating Conditions for Stratix 10 GX/SX/TX/MX E-Tile Devices—Preliminary
Symbol
Description
Minimum
15
Typical
Maximum
15
Unit
VCCERT
Transceiver power supply
0.87
0.9
0.93
V
VCCERT_PLL
Transceiver PLL power
supply
0.87
0.9
0.93
V
VCCEHT
Analog power supply
1.067
1.1
1.133
V
15
continued...
11 These data rate ranges vary depending on the transceiver speed grade. Refer to Transceiver Performance for Stratix 10 GX/SX
Devices for exact data rate ranges.
12 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
13 Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same
side of the device as the channels that required 1.12 V ± 20 mV, VCCR_GXB and VCCT_GXB = 1.12 V ± 20 mV.
14 Backplane applications assume advanced equalization circuitry, such as decision feedback equalization (DFE), is enabled to
compensate for signal impairments. Chip-to-chip links are assumed to be applications with short reach channels that do not require
DFE.
15 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
Intel® Stratix 10 Device Datasheet
9
Stratix® 10 Device Datasheet
Symbol
Description
Minimum
15
Typical
Maximum
15
Unit
VCCL
Periphery circuitry power
supply
0.725
0.75
0.775
V
VCCN2P5V_IO
LVPECL REFCLK power
supply
2.375
2.5
2.625
V
VCCR
Transceiver high voltage
power supply
1.71
1.8
1.89
V
Note:
Most VCCR_GXB and VCCT_GXB pins associated with unused transceiver channels can be grounded on a per-tile basis to
minimize power consumption. Refer to the Stratix 10 GX, GT, and SX Device Family Pin Connection Guidelines and the
Quartus® Prime pin report for information about pinning out the package to minimize power consumption for your specific
design.
Related Links
Stratix 10 GX, GT, and SX Device Family Pin Connection Guidelines
HPS Power Supply Operating Conditions
Table 7.
HPS Power Supply Operating Conditions for Stratix 10 Devices—Preliminary
This table lists the steady-state voltage and current values expected for Stratix 10 system-on-a-chip (SoC) devices with ARM®-based hard processor system
(HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to Recommended Operating Conditions for Stratix 10 Devices table for the
steady-state voltage values expected from the FPGA portion of the Stratix 10 SoC devices.
Symbol
VCCL_HPS
VCCPLLDIG_HPS
Description
Condition
Minimum
Typical
Maximum
Unit
HPS core voltage and periphery circuitry power
supply
–E2L, –I2L, –E3X, –I3X
0.91
0.94
0.97
V
–E1V, –I1V, –E2V, –I2V, –E3V,
–I3V 16
0.77 – 0.91
0.8 – 0.94
0.83 – 0.97
V
–E2L, –I2L, –E3X, –I3X
0.91
0.94
0.97
HPS PLL digital power supply
V
continued...
15 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements.
Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
16 SmartVID graded devices require the use of a configurable voltage regulator or system controller to receive the device’s settings
through PMBUS or PWM for proper performance.
Intel® Stratix 10 Device Datasheet
10
Stratix® 10 Device Datasheet
Symbol
Description
Condition
Minimum
Typical
Maximum
Unit
–E1V, –I1V, –E2V, –I2V, –E3V,
–I3V 16
0.77 – 0.91
0.8 – 0.94
0.83 – 0.97
V
VCCPLL_HPS
HPS PLL analog power supply
1.8 V
1.71
1.8
1.89
V
VCCIO_HPS
HPS I/O buffers power supply
1.8 V
1.71
1.8
1.89
V
Related Links
•
Recommended Operating Conditions on page 6
Provides the steady-state voltage values for the FPGA portion of the device.
•
HPS Clock Performance - Preliminary on page 51
DC Characteristics
The pin capacitance specifications will be available in a future release of the Stratix 10 Device Datasheet.
Supply Current and Power Consumption
Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Quartus Prime
Power Analyzer feature.
Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a
magnitude estimate of the device power because these currents vary greatly with the usage of the resources.
The Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete
place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal
activities that, when combined with detailed circuit models, yield very accurate power estimates.
I/O Pin Leakage Current
Table 8.
I/O Pin Leakage Current for Stratix 10 Devices—Preliminary
Symbol
Description
Condition
Min
Max
Unit
II
Input pin
VI = 0 V to VCCIOMAX
–80
80
µA
IOZ
Tri-stated I/O pin
VO = 0 V to VCCIOMAX
–80
80
µA
Intel® Stratix 10 Device Datasheet
11
Stratix® 10 Device Datasheet
Bus Hold Specifications
The bus-hold trip points are based on calculated input voltages from the JEDEC standard.
Table 9.
Bus Hold Parameters for Stratix 10 Devices—Preliminary
Parameter
Symbol
Condition
VCCIO (V)
1.2
Unit
1.5
1.8
3.0
Min
Max
Min
Max
Min
Max
Min
Max
Bus-hold, low,
sustaining current
ISUSL
VIN > VIL
(max)
8
—
12
—
30
—
70
—
µA
Bus-hold, high,
sustaining current
ISUSH
VIN < VIH
(min)
–8
—
–12
—
–30
—
–70
—
µA
Bus-hold, low,
overdrive current
IODL
0 V < VIN <
VCCIO
—
125
—
175
—
200
—
500
µA
Bus-hold, high,
overdrive current
IODH
0 V < VIN <
VCCIO
—
–125
—
–175
—
–200
—
–500
µA
Bus-hold trip point
VTRIP
—
0.3
0.9
0.38
1.13
0.68
1.07
0.8
2
V
OCT Calibration Accuracy Specifications
If you enable on-chip termination (OCT) calibration, calibration is automatically performed at power up for I/Os connected to
the calibration block.
Table 10.
OCT Calibration Accuracy Specifications for Stratix 10 Devices—Preliminary
Calibration accuracy for the calibrated on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) are applicable at the moment of calibration.
When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change.
Symbol
Description
Condition (V)
Calibration Accuracy
Unit
–E1, –I1
–E2, –I2
–E3, –I3
48-Ω, 60-Ω, 80-Ω, and
240-Ω RS
Internal series termination with calibration
(48-Ω, 60-Ω, 80-Ω, and 240-Ω setting)
VCCIO = 1.2
±15
±15
±15
%
34-Ω and 40-Ω RS
Internal series termination with calibration
(34-Ω and 40-Ω setting)
VCCIO = 1.5, 1.35, 1.25, 1.2
±15
±15
±15
%
continued...
Intel® Stratix 10 Device Datasheet
12
Stratix® 10 Device Datasheet
Symbol
Description
Condition (V)
Calibration Accuracy
Unit
–E1, –I1
–E2, –I2
–E3, –I3
25-Ω and 50-Ω RS
Internal series termination with calibration
(25-Ω and 50-Ω setting)
VCCIO = 3.0, 1.8, 1.5, 1.2
±15
±15
±15
%
34-Ω, 40-Ω, 48-Ω, 60-Ω,
80-Ω, 120-Ω, and 240-Ω RT
Internal parallel termination with
calibration (34-Ω, 40-Ω, 48-Ω, 60-Ω, 80Ω, 120-Ω, and 240-Ω setting)
POD12 I/O standard,
VCCIO = 1.2
±15
±15
±15
%
34-Ω, 48-Ω, 80-Ω, and
240-Ω RT
Internal parallel termination with
calibration (34-Ω, 48-Ω, 80-Ω, and 240-Ω
setting)
VCCIO = 1.2
–10 to +40
–10 to +40
–10 to +40
%
40-Ω, 60-Ω, and 120-Ω RT
Internal parallel termination with
calibration (40-Ω, 60-Ω, and 120-Ω
setting)
VCCIO = 1.5, 1.35, 1.25, 1.2
–10 to +40
–10 to +40
–10 to +40
%
25-Ω RT
Internal parallel termination with
calibration (25-Ω setting)
VCCIO = 1.5
–10 to +40
–10 to +40
–10 to +40
%
50-Ω RT
Internal parallel termination with
calibration (50-Ω setting)
VCCIO = 1.8, 1.5, 1.2
–10 to +40
–10 to +40
–10 to +40
%
OCT Without Calibration Resistance Tolerance Specifications
Table 11.
OCT Without Calibration Resistance Tolerance Specifications for Stratix 10 Devices—Preliminary
This table lists the Stratix 10 OCT without calibration resistance tolerance to PVT changes.
Symbol
25-Ω RS
50-Ω RS
100-Ω RD
Description
Condition (V)
Resistance Tolerance
Unit
–E1, –I1
–E2, –I2
–E3, –I3
Internal series termination without
calibration
(25-Ω setting)
VCCIO = 1.8, 1.5
TBD
TBD
TBD
%
VCCIO = 1.2
TBD
TBD
TBD
%
Internal series termination without
calibration
(50-Ω setting)
VCCIO = 1.8, 1.5
TBD
TBD
TBD
%
VCCIO = 1.2
TBD
TBD
TBD
%
Internal differential termination (100-Ω
setting)
VCCIO = 1.8
±25
±35
±40
%
Intel® Stratix 10 Device Datasheet
13
Stratix® 10 Device Datasheet
Figure 1.
Equation for OCT Variation Without Recalibration—Preliminary
The definitions for the equation are as follows:
•
The ROCT value calculated shows the range of OCT resistance with the variation of temperature and VCCIO.
•
RSCAL is the OCT resistance value at power-up.
•
ΔT is the variation of temperature with respect to the temperature at power up.
•
ΔV is the variation of voltage with respect to the VCCIO at power up.
•
dR/dT is the percentage change of RSCAL with temperature.
•
dR/dV is the percentage change of RSCAL with voltage.
Internal Weak Pull-Up Resistor
All I/O pins, except configuration, test, and JTAG pins, have an option to enable weak pull-up. For SDM and HPS, the
configuration I/O and peripheral I/O are supported with weak pull-up and weak pull-down options.
Table 12.
Internal Weak Pull-Up Resistor Values for Stratix 10 Devices—Preliminary
Symbol
RPU
Description
Value of the I/O pin pull-up resistor before and during configuration, as
well as user mode if you have enabled the programmable pull-up
resistor option.
Condition (V)
Nominal Value
Unit
VCCIO = 3.0 ±5%
25
kΩ
VCCIO = 1.8 ±5%
25
kΩ
VCCIO = 1.5 ±5%
25
kΩ
VCCIO = 1.35 ±5%
25
kΩ
VCCIO = 1.25 ±5%
25
kΩ
VCCIO = 1.2 ±5%
25
kΩ
Related Links
Intel Stratix 10 GX, MX, and SX Device Family Pin Connection Guidelines
Provides more information about the pins that support internal weak pull-up and internal weak pull-down features.
Intel® Stratix 10 Device Datasheet
14
Stratix® 10 Device Datasheet
I/O Standard Specifications
Tables in this section list the input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH
and IOL) for various I/O standards supported by Stratix 10 devices.
For minimum voltage values, use the minimum VCCIO values. For maximum voltage values, use the maximum VCCIO values.
You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards.
Related Links
Recommended Operating Conditions on page 6
Single-Ended I/O Standards Specifications
Table 13.
Single-Ended I/O Standards Specifications for Stratix 10 Devices—Preliminary
I/O Standard
VCCIO (V)
VIL(V)
VIH(V)
VOL (V)
VOH (V)
IOL 17
(mA)
IOH 17
(mA)
Min
Typ
Max
Min
Max
Min
Max
Max
Min
3.0-V LVTTL
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.4
2.4
2
–2
3.0-V LVCMOS
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.2
VCCIO – 0.2
0.1
–0.1
1.8 V
1.71
1.8
1.89
-0.3
0.35 × VCCIO
0.65 × VCCIO
VCCIO + 0.3
0.45
VCCIO – 0.45
2
–2
1.5 V
1.425
1.5
1.575
–0.3
0.35 × VCCIO
0.65 × VCCIO
VCCIO + 0.3
0.25 × VCCIO
0.75 × VCCIO
2
–2
1.2 V
1.14
1.2
1.26
–0.3
0.35 × VCCIO
0.65 × VCCIO
VCCIO + 0.3
0.25 × VCCIO
0.75 × VCCIO
2
–2
17 To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the 1.8- V
LVCMOS specification (4 mA), you should set the current strength settings to 4 mA. Setting at lower current strength may not meet
the IOL and IOH specifications in the datasheet.
Intel® Stratix 10 Device Datasheet
15
Stratix® 10 Device Datasheet
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Table 14.
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Stratix 10 Devices—Preliminary
I/O Standard
VCCIO (V)
VREF (V)
VTT (V)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SSTL-18
Class I, II
1.71
1.8
1.89
0.833
0.9
0.969
VREF - 0.04
VREF
VREF + 0.04
SSTL-15
Class I, II
1.425
1.5
1.575
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
SSTL-135
Class I, II
1.283
1.35
1.45
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
SSTL-125
Class I, II
1.19
1.25
1.31
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
HSTL-18
Class I, II
1.71
1.8
1.89
0.85
0.9
0.95
—
VCCIO/2
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.68
0.75
0.9
—
VCCIO/2
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.47 × VCCIO
0.5 × VCCIO
0.53 × VCCIO
—
VCCIO/2
—
HSUL-12
1.14
1.2
1.3
0.49 × VCCIO
0.5 × VCCIO
0.51 × VCCIO
—
—
—
POD12
1.16
1.2
1.24
—
Internally
calibrated
—
—
VCCIO
—
Intel® Stratix 10 Device Datasheet
16
Stratix® 10 Device Datasheet
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Table 15.
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Stratix 10 Devices—Preliminary
I/O Standard
VIL(DC) (V)
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
IOL 18
(mA)
IOH 18
(mA)
Min
Max
Min
Max
Max
Min
Max
Min
SSTL-18 Class I
–0.3
VREF –0.125
VREF + 0.125
VCCIO + 0.3
VREF – 0.25
VREF + 0.25
VTT – 0.603
VTT + 0.603
6.7
–6.7
SSTL-18 Class
II
–0.3
VREF –0.125
VREF + 0.125
VCCIO + 0.3
VREF – 0.25
VREF + 0.25
0.28
VCCIO –0.28
13.4
–13.4
SSTL-15 Class I
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.175
VREF + 0.175
0.2 × VCCIO
0.8 × VCCIO
8
–8
SSTL-15 Class
II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.175
VREF + 0.175
0.2 × VCCIO
0.8 × VCCIO
16
–16
SSTL-135
—
VREF – 0.09
VREF + 0.09
—
VREF – 0.16
VREF + 0.16
0.2 × VCCIO
0.8 × VCCIO
—
—
SSTL-125
—
VREF – 0.09
VREF + 0.09
—
VREF – 0.15
VREF + 0.15
0.2 × VCCIO
0.8 × VCCIO
—
—
HSTL-18 Class I
—
VREF –0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
8
–8
HSTL-18 Class
II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
16
–16
HSTL-15 Class I
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO – 0.4
8
–8
HSTL-15 Class
II
—
VREF – 0.1
VREF + 0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO –0.4
16
–16
HSTL-12 Class I
–0.15
VREF – 0.08
VREF + 0.08
VCCIO + 0.15
VREF – 0.15
VREF + 0.15
0.25 × VCCIO
0.75 × VCCIO
8
–8
HSTL-12 Class
II
–0.15
VREF – 0.08
VREF + 0.08
VCCIO + 0.15
VREF – 0.15
VREF + 0.15
0.25 × VCCIO
0.75 × VCCIO
16
–16
—
VREF – 0.13
VREF + 0.13
—
VREF – 0.22
VREF + 0.22
0.1 × VCCIO
0.9 × VCCIO
—
—
–0.15
VREF – 0.08
VREF + 0.08
VCCIO + 0.15
VREF – 0.15
VREF + 0.15
(0.7 – 0.15) ×
VCCIO
(0.7 + 0.15) ×
VCCIO
—
—
HSUL-12
POD12
18 To meet the IOL and IOH specifications, you must set the current strength settings accordingly. For example, to meet the SSTL15CI
specification (8 mA), you should set the current strength settings to 8 mA. Setting at lower current strength may not meet the IOL and
IOH specifications in the datasheet.
Intel® Stratix 10 Device Datasheet
17
Stratix® 10 Device Datasheet
Differential SSTL I/O Standards Specifications
Table 16.
Differential SSTL I/O Standards Specifications for Stratix 10 Devices—Preliminary
I/O Standard
VCCIO (V)
VSWING(DC) (V)
VSWING(AC) (V)
VX(AC) (V)
Min
Typ
Max
Min
Max
Min
Max
Min
Max
SSTL-18 Class I,
II
1.71
1.8
1.89
0.25
VCCIO + 0.6
0.5
VCCIO + 0.6
VCCIO/2 – 0.175
VCCIO/2 + 0.175
SSTL-15 Class I,
II
1.425
1.5
1.575
0.2
19
2(VIH(AC) – VREF)
2(VREF – VIL(AC))
VCCIO/2 – 0.15
VCCIO/2 + 0.15
SSTL-135
1.283
1.35
1.45
0.18
19
2(VIH(AC) – VREF)
2(VIL(AC) – VREF)
VCCIO/2 – 0.15
VCCIO/2 + 0.15
0.18
19
2(VIH(AC) – VREF)
2(VIL(AC) – VREF)
VCCIO/2 – 0.15
VCCIO/2 + 0.15
SSTL-125
1.19
1.25
1.31
Differential HSTL and HSUL I/O Standards Specifications
Table 17.
Differential HSTL and HSUL I/O Standards Specifications for Stratix 10 Devices—Preliminary
I/O Standard
VCCIO (V)
VDIF(DC) (V)
VDIF(AC) (V)
VX(AC) (V)
VCM(DC) (V)
Min
Typ
Max
Min
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
HSTL-18 Class
I, II
1.71
1.8
1.89
0.2
—
0.4
—
0.78
—
1.12
0.78
—
1.12
HSTL-15 Class
I, II
1.425
1.5
1.575
0.2
—
0.4
—
0.68
—
0.9
0.68
—
0.9
HSTL-12 Class
I, II
1.14
1.2
1.26
0.16
VCCIO
+ 0.3
0.3
VCCIO
+ 0.48
—
0.5 ×
VCCIO
—
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
HSUL-12
1.14
1.2
1.3
2(VIH(DC) –
VREF)
2(VREF –
VIH(DC))
2(VIH(AC) –
VREF)
2(VREF –
VIH(AC))
0.5 ×
VCCIO –
0.12
0.5 ×
VCCIO
0.5 ×
VCCIO
+0.12
0.4 ×
VCCIO
0.5 ×
VCCIO
0.6 ×
VCCIO
19 The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended
limits (VIH(DC) and VIL(DC)).
Intel® Stratix 10 Device Datasheet
18
Stratix® 10 Device Datasheet
Differential I/O Standards Specifications
Table 18.
Differential I/O Standards Specifications for Stratix 10 Devices—Preliminary
I/O Standard
LVDS
RSDS
23
24
Mini-LVDS
LVPECL
26
25
VCCIO (V)
VID (mV)
20
VICM(DC) (V)
VOD (V)
21 22
VOCM (V)
21
Min
Typ
Max
Min
Max
Min
Condition
Max
Min
Typ
Max
Min
Typ
Max
1.71
1.8
1.89
100
—
0.05
Data rate
≤700 Mbps
1.65
0.247
—
0.6
1.125
1.25
1.375
1
Data rate
>700 Mbps
1.6
1.71
1.8
1.89
100
—
0.3
—
1.4
0.1
0.2
0.6
0.5
1.2
1.4
1.71
1.8
1.89
200
600
0.4
—
1.325
0.25
—
0.6
1
1.2
1.4
1.71
1.8
1.89
300
—
0.6
Data rate
≤700 Mbps
1.7
—
—
—
—
—
—
1
Data rate
>700 Mbps
1.6
Switching Characteristics
This section provides the performance characteristics of Stratix 10 core and periphery blocks.
20 The minimum VID value is applicable over the entire common mode range, VCM.
21 RL range: 90 ≤ RL ≤ 110 Ω.
22 The specification is only applicable to default VOD setting.
23 For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 700
Mbps and 0.05 V to 1.65 V for data rates below 700 Mbps.
24 For optimized RSDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.4 V.
25 For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.4 V to 1.325 V.
26 For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above
700 Mbps and 0.45 V to 1.95 V for data rates below 700 Mbps.
Intel® Stratix 10 Device Datasheet
19
Stratix® 10 Device Datasheet
L-Tile Transceiver Performance Specifications
Transceiver Performance for Stratix 10 GX/SX L-Tile Devices
Table 19.
L-Tile Transmitter and Receiver Data Rate Performance, VCCR_GXB and VCCT_GXB Specifications—Preliminary
Symbol/Description
Chip-to-Chip
Backplane
Table 20.
27 28
27 30
Minimum
Typical
Maximum
Unit
1 Gbps to 17.4 Gbps
29
1.0
1.03
1.06
V
1 Gbps to 12.5 Gbps
29
1.0
1.03
1.06
V
L-Tile ATX PLL Performance—Preliminary
Symbol/Description
Supported Output Frequency
Table 21.
Condition
Condition
Transceiver Speed Grade 3
Unit
Maximum Frequency
8.7
GHz
Minimum Frequency
500
MHz
Transceiver Speed Grade 3
Unit
Maximum Frequency
6.25
GHz
Minimum Frequency
500
MHz
L-Tile Fractional PLL Performance—Preliminary
Symbol/Description
Supported Output Frequency
Condition
27 Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same
side of the device as the channels that required 1.12 V ± 20 mV, VCCR_GXB and VCCT_GXB = 1.12 V ± 20 mV.
28 Chip-to-chip refers to transceiver links that are short reach and dont require advanced equalization such as decision feedback
equalization (DFE).
29 Stratix 10 transceivers can support data rates below 1 Gbps through over sampling.
30 Backplane applications refer to ones which require advanced equalization, such as DFE enabled, to compensate for channel loss.
Intel® Stratix 10 Device Datasheet
20
Stratix® 10 Device Datasheet
Table 22.
L-Tile CMU PLL Performance—Preliminary
Symbol/Description
Supported Output Frequency
Condition
Transceiver Speed Grade 3
Unit
Maximum Frequency
5.15625
GHz
Minimum Frequency
2.450
GHz
Transceiver Specifications for Stratix 10 GX/SX L-Tile Devices
Table 23.
L-Tile Reference Clock Specifications—Preliminary
Symbol/Description
Condition
Transceiver Speed Grade 3
Min
Supported I/O Standards
Dedicated reference clock pin
Typ
Unit
Max
CML, Differential LVPECL, LVDS, and HCSL
RX reference clock pin
CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency
(CMU PLL)
61
—
800
MHz
Input Reference Clock Frequency
(ATX PLL)
100
—
800
MHz
—
800
MHz
Input Reference Clock Frequency
(fPLL PLL)
50
31
Rise time
20% to 80%
—
—
400
ps
Fall time
80% to 20%
—
—
400
ps
Duty cycle
—
45
—
55
%
Spread-spectrum modulating clock frequency
PCIe
30
—
33
kHz
Spread-spectrum downspread
PCIe
—
0 to –0.5
—
%
On-chip termination resistors
—
—
100
—
Ω
Absolute VMAX
Dedicated reference clock pin
—
—
1.6
V
RX reference clock pin
—
—
1.2
V
continued...
31 The fMIN is 29 MHz when the fPLL is used as a core PLL.
Intel® Stratix 10 Device Datasheet
21
Stratix® 10 Device Datasheet
Symbol/Description
Condition
Transceiver Speed Grade 3
Unit
Min
Typ
Max
Absolute VMIN
—
–0.4
—
—
V
Peak-to-peak differential input voltage
—
200
—
1600
mV
VICM (AC coupled)
VCCR_GXB =1.03 V
VICM (DC coupled)
HCSL I/O standard for PCIe
reference clock
—
1.03
—
V
250
—
550
mV
100 Hz
—
—
–70
dBc/Hz
1 kHz
—
—
–90
dBc/Hz
10 kHz
—
—
–100
dBc/Hz
100 kHz
—
—
–110
dBc/Hz
≥ 1 MHz
—
—
–120
dBc/Hz
Transmitter REFCLK Phase Jitter (100 MHz)
1.5 MHz to 100 MHz (PCIe)
—
—
4.2
ps (rms)
RREF
—
—
2.0 k ±1%
—
Ω
TSSC-MAX-PERIOD-SLEW
Max spread spectrum clocking
(SSC) df/dt
Transmitter REFCLK Phase Noise (622 MHz)
Table 24.
32
0.75
L-Tile Transceiver Clock Network Maximum Data Rate Specifications—Preliminary
Clock Network
Maximum Performance
33
Channel Span
Unit
ATX
fPLL
CMU
x1
17.4
12.5
10.3125
6 channels
Gbps
x6
17.4
12.5
N/A
6 channels
Gbps
16
12.5
N/A
2 banks up and 2 banks
down
Gbps
x24
32 To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise
at f (MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622).
33 The maximum data rate depends on speed grade.
Intel® Stratix 10 Device Datasheet
22
Stratix® 10 Device Datasheet
Table 25.
L-Tile Receiver Specifications—Preliminary
Symbol/Description
Transceiver Speed Grade 3
Condition
Min
Typ
Unit
Max
Supported I/O Standards
—
Absolute VMAX for a
receiver pin 34
—
—
—
1.2
V
Absolute VMIN for a
receiver pin 34
—
-0.4
—
—
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before device
configuration 35
—
—
—
1.6
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) after device
configuration 35
VCCR_GXB = 1.03 V
—
—
2.0
V
Minimum differential eye
opening at receiver serial
input pins 37
—
50
—
—
mV
85-Ω setting
—
85 ± 20%
—
Ω
100-Ω setting
—
100 ± 20%
—
Ω
VCCR_GXB = 1.03 V
—
700
—
mV
VCCR_GXB = 1.12 V
—
750
—
mV
Differential on-chip
termination resistors
VICM (AC and DC coupled)
non-PCIe channels
High Speed Differential I/O, CML, Differential LVPECL, and LVDS
36
continued...
34 The device cannot tolerate prolonged operation at this absolute maximum.
35 DC coupling specifications are pending silicon characterization.
36 Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same
side of the device as the channels that required 1.12 V ± 20 mV, VCCR_GXB and VCCT_GXB = 1.12 V ± 20 mV.
37 The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable
Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
Intel® Stratix 10 Device Datasheet
23
Stratix® 10 Device Datasheet
Symbol/Description
VICM (AC and DC coupled)
PCIe channels
Condition
Transceiver Speed Grade 3
Unit
Min
Typ
Max
VCCR_GXB = 1.03 V
—
650
—
mV
—
mV
VCCR_GXB = 1.12 V
—
650
tLTR
38
—
—
—
1
ms
tLTD39
—
4
—
—
µs
tLTD_manual40
—
4
—
—
µs
tLTR_LTD_manual41
—
15
—
—
µs
Run Length
—
—
—
200
UI
-300
—
300
ppm
-1000
—
1000
ppm
CDR ppm tolerance
Table 26.
PCIe-only
All other protocols
L-Tile Transmitter Specifications—Preliminary
Symbol/Description
Supported I/O Standards
Differential on-chip
termination resistors
Condition
Transceiver Speed Grade 3
Min
—
Typ
High Speed Differential I/O
Max
42
Unit
—
85-Ω setting
—
85 ± 20%
—
Ω
100-Ω setting
—
100 ± 20%
—
Ω
continued...
38 tLTR is the time required for the receiver CDR to lock to the input reference clock frequency after coming out of reset.
39 tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
40 tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high
when the CDR is functioning in the manual mode.
41 tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes
high when the CDR is functioning in the manual mode.
42 High Speed Differential I/O is the dedicated I/O standard for the transmitter in Stratix 10 transceivers.
Intel® Stratix 10 Device Datasheet
24
Stratix® 10 Device Datasheet
Symbol/Description
Condition
Transceiver Speed Grade 3
Min
Typ
Max
Unit
VOCM (AC coupled)
VCCT_GXB = 1.03 V
—
515
—
mV
VOCM (DC coupled)
VCCT_GXB = 1.03 V
—
515
—
mV
20% to 80%
20
—
130
ps
80% to 20%
20
—
130
ps
TX VCM = 0.5 V and slew
rate of 15 ps
—
—
15
ps
Rise time
Fall time
43
43
Intra-differential pair skew
44
Table 27.
L-Tile Typical Transmitter VOD Settings—Preliminary
Symbol
VOD differential value = VOD/VCCT_GXB ratio x VCCT_GXB
VOD Setting
VOD/VCCT_GXB Ratio
31
1.00
30
0.97
29
0.93
28
0.90
27
0.87
26
0.83
25
0.80
24
0.77
23
0.73
22
0.70
21
0.67
20
0.63
continued...
43 The Quartus Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
44 In QPI mode, if VCM < 0.17 V, the input Vid must be greater than 100 mV. If VCM > 0.17 V, the input Vid must be greater than 70 mV.
Intel® Stratix 10 Device Datasheet
25
Stratix® 10 Device Datasheet
Symbol
Table 28.
VOD/VCCT_GXB Ratio
19
0.60
18
0.57
17
0.53
16
0.50
15
0.47
14
0.43
13
0.40
12
0.37
L-Tile Transmitter Channel-to-channel Skew Specifications—Preliminary
Mode
Channel Span
x6 Clock
Table 29.
VOD Setting
Up to 6 channels in one bank
Maximum Skew
Unit
61
ps
Transceiver Clocks Specifications for Stratix 10 GX/SX L-Tile Devices—Preliminary
Clock
Value
Unit
reconfig_clk
≤ 125
MHz
fixed_clk for the RX detect circuit
250 ± 20%
MHz
For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.
Related Links
•
External Configuration Clock Source Requirements on page 79
•
PLLs and Clock Networks
Intel® Stratix 10 Device Datasheet
26
Stratix® 10 Device Datasheet
H-Tile Transceiver Performance Specifications
Transceiver Performance for Stratix 10 GX/SX H-Tile Devices
Table 30.
H-Tile Transmitter and Receiver Data Rate Performance, VCCR_GXB and VCCT_GXB Specifications—Preliminary
Channel
Symbol/Description
Transceiver Speed Grades
-1
GX
45 46
GXT
Table 31.
Typical
Maximum
-3
Unit
1 Gbps to 17.4
Gbps
1 Gbps to 17.4
Gbps 47
1 Gbps to 17.4
Gbps 47
1.0
1.03
1.06
Backplane
1 Gbps to 17.4
Gbps 47
1 Gbps to 17.4
Gbps 47
1 Gbps to 17.4
Gbps 47
1.0
1.03
1.06
Chip-to-Chip
1 Gbps to 28.3
Gbps 47
1 Gbps to 26
Gbps 47
1 Gbps to 17.4
Gbps 47
1.10
1.12
1.14
Backplane
1 Gbps to 28.3
Gbps 47
1 Gbps to 26
Gbps 47
1 Gbps to 17.4
Gbps 47
1.10
1.12
1.14
Chip-to-Chip
48
-2
Minimum
47
V
V
V
V
H-Tile ATX PLL Performance—Preliminary
Symbol/Description
Supported Output
Frequency
Condition
Transceiver Speed
Grade 1
Maximum Frequency
14.15
Minimum Frequency
500
Transceiver Speed
Grade 2
13
Transceiver Speed
Grade 3
Unit
8.7
GHz
MHz
45 GX channels are the transceiver channels that run at datarates ≤ 17.4 Gbps.
46 Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same
side of the device as the channels that require 1.12 V ± 20 mV, VCCR_GXB and VCCT_GXB = 1.12 V ± 20 mV.
47 Stratix 10 transceivers can support data rates below 1 Gbps through over sampling.
48 GXT channels are the transceiver channels that run at datarates ≤ 28.3 Gbps.
Intel® Stratix 10 Device Datasheet
27
Stratix® 10 Device Datasheet
Table 32.
H-Tile Fractional PLL Performance—Preliminary
Symbol/Description
Supported Output Frequency
Table 33.
Condition
All Transceiver Speed Grades
Unit
Maximum Frequency
6.25
GHz
Minimum Frequency
500
MHz
All Transceiver Speed Grades
Unit
Maximum Frequency
5.15625
GHz
Minimum Frequency
2.450
GHz
H-Tile CMU PLL Performance—Preliminary
Symbol/Description
Supported Output Frequency
Condition
Transceiver Specifications for GX/SX H-Tile Devices
Table 34.
H-Tile Reference Clock Specifications—Preliminary
Symbol/Description
Supported I/O Standards
Condition
Min
Dedicated reference clock pin
Typ
Max
Unit
CML, Differential LVPECL, LVDS, and HCSL
RX reference clock pin
CML, Differential LVPECL, and LVDS
Input Reference Clock Frequency (CMU PLL)
61
—
800
MHz
Input Reference Clock Frequency (ATX PLL)
100
—
800
MHz
—
800
MHz
Input Reference Clock Frequency (fPLL PLL)
50
49
Rise time
20% to 80%
—
—
400
ps
Fall time
80% to 20%
—
—
400
ps
Duty cycle
—
45
—
55
%
Spread-spectrum modulating clock frequency
PCIe
30
—
33
kHz
Spread-spectrum downspread
PCIe
—
0 to –0.5
—
%
On-chip termination resistors
—
—
100
—
Ω
continued...
49 The fMIN is 29 MHz when the fPLL is used as a core PLL.
Intel® Stratix 10 Device Datasheet
28
Stratix® 10 Device Datasheet
Symbol/Description
Condition
Min
Typ
Max
Unit
Dedicated reference clock pin
—
—
1.6
V
RX reference clock pin
—
—
1.2
V
—
–0.4
—
—
V
Peak-to-peak differential input voltage
—
200
—
1600
mV
VICM (AC coupled)
VCCR_GXB =1.03 V
—
1.03
—
V
VCCR_GXB = 1.12 V
—
1.12
—
V
250
—
550
mV
Absolute VMAX
Absolute VMIN
VICM (DC coupled)
HCSL I/O standard for PCIe
reference clock
50
100 Hz
—
—
–70
dBc/Hz
1 kHz
—
—
–90
dBc/Hz
10 kHz
—
—
–100
dBc/Hz
100 kHz
—
—
–110
dBc/Hz
≥ 1 MHz
—
—
–120
dBc/Hz
Transmitter REFCLK Phase Jitter (100 MHz)
1.5 MHz to 100 MHz (PCIe)
—
—
4.2
ps (rms)
RREF
—
—
2.0 k ±1%
—
Ω
TSSC-MAX-PERIOD-SLEW
Max SSC df/dt
Transmitter REFCLK Phase Noise (622 MHz)
0.75
50 To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise
at f (MHz) = REFCLK phase noise at 622 MHz + 20*log(f/622).
Intel® Stratix 10 Device Datasheet
29
Stratix® 10 Device Datasheet
Table 35.
H-Tile Transceiver Clock Network Maximum Data Rate Specifications—Preliminary
Clock Network
Maximum Performance
51
Channel Span
Unit
ATX
fPLL
CMU
x1
17.4
12.5
10.3125
6 channels
Gbps
x6
17.4
12.5
N/A
6 channels
Gbps
16
12.5
N/A
2 banks up and 2 banks
down
Gbps
28.3
N/A
N/A
4 GXT channels within the
same transceiver bank and
2 from the bank above or
2 from the bank below. 52
Gbps
x24
GXT clock lines
Table 36.
H-Tile Receiver Specifications—Preliminary
Symbol/Description
Condition
Transceiver Speed Grade 3
Min
Typ
Max
Unit
Supported I/O Standards
—
High Speed Differential I/O, CML, Differential LVPECL, and LVDS
Absolute VMAX for a
receiver pin 53
—
—
—
1.2
V
Absolute VMIN for a
receiver pin 53
—
-0.4
—
—
V
Maximum peak-to-peak
differential input voltage
VID (diff p-p) before device
configuration 54
—
—
—
1.6
V
continued...
51 The maximum data rate depends on speed grade.
52 If the upper ATX PLL in a bank is used, then the channel span includes two GXT channels from the bank above. If the lower ATX PLL in
a bank is used, then the channel span includes two channels from the bank below.
53 The device cannot tolerate prolonged operation at this absolute maximum.
54 DC coupling specifications are pending silicon characterization.
Intel® Stratix 10 Device Datasheet
30
Stratix® 10 Device Datasheet
Symbol/Description
Transceiver Speed Grade 3
Condition
Min
Typ
Max
Unit
Maximum peak-to-peak
differential input voltage
VID (diff p-p) after device
configuration 54
VCCR_GXB = 1.03 V, 1.12 V
55, 58
—
—
2.0
V
Minimum differential eye
opening at receiver serial
input pins 56
—
50
—
—
mV
85-Ω setting
—
85 ± 20%
—
Ω
Differential on-chip
termination resistors
VICM (AC and DC coupled)
tLTR
59
tLTD
60
tLTD_manual
61
100-Ω setting
57
—
100 ± 20%
—
Ω
VCCR_GXB = 1.03 V
58
—
700
—
mV
VCCR_GXB = 1.12 V
58
—
750
—
mV
—
—
—
1
ms
—
4
—
—
µs
—
4
—
—
µs
continued...
55 Bonded channels operating at data rates above 16 Gbps require 1.12 V ± 20 mV at the pin. For channels that are placed in the same
side of the device as the channels that required 1.12 V ± 20 mV, VCCR_GXB = 1.12 V ± 20 mV.
56 The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable
Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
57 Stratix 10 devices support DC coupling to other Stratix 10 devices and other devices operating under the Hybrid Memory Cube (HMC)
specifications.
58 For GXT channels, VCCR_GXB must be 1.12 V. For GX channels, VCCR_GXB must be 1.03 V. VCCR_GXB must be 1.12 V for the transceiver
on the side of the device when using GX and GXT channels together.
59 tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
60 tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
Intel® Stratix 10 Device Datasheet
31
Stratix® 10 Device Datasheet
Symbol/Description
tLTR_LTD_manual
62
Run Length
CDR ppm tolerance
Table 37.
Condition
Transceiver Speed Grade 3
Unit
Min
Typ
Max
—
15
—
—
µs
—
—
—
200
UI
-300
—
300
ppm
-1000
—
1000
ppm
PCIe-only
All other protocols
H-Tile Transmitter Specifications—Preliminary
Symbol/Description
Supported I/O Standards
Differential on-chip
termination resistors
Condition
Transceiver Speed Grade 3
Min
—
Typ
High Speed Differential I/O
85-Ω setting
63
Unit
—
—
85 ± 20%
—
Ω
—
100 ± 20%
—
Ω
VCCT_GXB = 1.03 V
64
—
515
—
mV
VOCM (AC coupled)
VCCT_GXB = 1.12 V
64
—
560
VOCM (DC coupled)
VCCT_GXB = 1.03 V
64
—
515
—
mV
VOCM (DC coupled)
VCCT_GXB = 1.12 V
64
—
560
—
mV
VOCM (AC coupled)
100-Ω setting
Max
mV
continued...
61 tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high
when the CDR is functioning in the manual mode.
62 tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes
high when the CDR is functioning in the manual mode.
63 High Speed Differential I/O is the dedicated I/O standard for the transmitter in Stratix 10 transceivers.
64 For GXT channels, VCCT_GXB must be 1.12 V. For GX channels, VCCT_GXB must be 1.03 V. VCCT_GXB must be 1.12 V for the transceiver
bank when using GX and GXT channels together within the same bank.
Intel® Stratix 10 Device Datasheet
32
Stratix® 10 Device Datasheet
Symbol/Description
Rise time
Fall time
65
65
Intra-differential pair skew
Table 38.
Condition
Transceiver Speed Grade 3
Unit
Min
Typ
Max
20% to 80%
20
—
130
ps
80% to 20%
20
—
130
ps
TX VCM = 0.5 V and slew
rate of 15 ps
—
—
15
ps
H-Tile Typical Transmitter VOD Settings—Preliminary
Symbol
VOD differential value = VOD/VCCT_GXB ratio x VCCT_GXB
VOD Setting
VOD/VCCT_GXB Ratio
31
1.00
30
0.97
29
0.93
28
0.90
27
0.87
26
0.83
25
0.80
24
0.77
23
0.73
22
0.70
21
0.67
20
0.63
19
0.60
18
0.57
17
0.53
16
0.50
continued...
65 The Quartus Prime software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
Intel® Stratix 10 Device Datasheet
33
Stratix® 10 Device Datasheet
Symbol
Table 39.
VOD/VCCT_GXB Ratio
15
0.47
14
0.43
13
0.40
12
0.37
H-Tile Transmitter Channel-to-channel Skew Specifications—Preliminary
Mode
Channel Span
x6 Clock
Table 40.
VOD Setting
Up to 6 channels in one bank
Maximum Skew
Unit
61
ps
Transceiver Clocks Specifications for Stratix 10 GX/SX H-Tile Devices—Preliminary
Clock
Value
Unit
reconfig_clk
≤ 125
MHz
fixed_clk for the RX detect circuit
250 ± 20%
MHz
For OSC_CLK_1 specifications, refer to the External Configuration Clock Source Requirements section.
Related Links
External Configuration Clock Source Requirements on page 79
E-Tile Transceiver Performance Specifications
Intel® Stratix 10 Device Datasheet
34
Stratix® 10 Device Datasheet
Transceiver Performance for Stratix 10 E-Tile Devices
Table 41.
E-Tile Transmitter and Receiver Data Rate Performance Specifications—Preliminary
Symbol/Description
Supported
datarate66
Condition
Minimum
NRZ
PAM-4
Typical
Maximum
Unit
1
30
Gbps
2
5667
Gbps
Maximum
Unit
Transceiver Reference Clock Specifications
Table 42.
E-Tile Reference Clock Specifications—Preliminary
Symbol/Description
Condition
Minimum
I/O standard
Termination voltage (Vtt)
Typical
LVPECL
2.5 V compliant
0.4
0.5
0.6
V
1.04
1.3
1.56
V
Termination resistor (Rtt)
40
50
60
ohm
Differential voltage (Vdiff)
0.4
0.8
1.2
V
VCCN2P5V_IO-Vdiff/2
V
VCCN2P5V_IO-1
V
VCCN2P5V_IO-Vdiff/2
V
2.6
V
2.8
V
3.3 V tolerant
Input common mode
voltage (Vcm)
2.5 V compliant, no
internal termination
resister
2.5 V compliant, internal
termination resister
3.3 V tolerant, no internal
termination resister
Vdiff/2
VCCN2P5V_IO-1.6
Vdiff/2
3.3 V tolerant, internal
termination resister
Absolute voltage
VCCN2P5V_IO-1.3
1.4
-0.5
2
66 The supported datarate is for chip-to-chip and backplane links.
67 Two channels are combined to support up to 56 Gbps.
Intel® Stratix 10 Device Datasheet
35
Stratix® 10 Device Datasheet
Transmitter Specifications for Stratix 10 E-Tile Devices
Table 43.
E-Tile Transmitter Specifications—Preliminary
Symbol/Description
Transmitter differential
output voltage peak-topeak
Condition
Minimum
No precursor/postcursor
de-emphasis
Transmiter commom mode
voltage
Typical
Maximum
Unit
0.965
V
VCCERT/2
V
Receiver Specifications for Stratix 10 E-Tile Devices
Table 44.
E-Tile Receiver Specifications—Preliminary
Symbol/Description
Condition
Minimum
Typical
Receiver run length68
DC input impedance
40
DC differential input
impedance
80
Powered down DC input
impedance
Receiver pin impendance
when the receiver
termination is powered
down
Electrical Idle detection
voltage
-
65
Differential termination
From DC to 100 Mhz
80
PPM tolerance
Allowed frequency
mismatch between
REFCLK and RX data
68 No additional transition density requirements apply.
69 The incoming data must be statistically DC-balanced.
Intel® Stratix 10 Device Datasheet
36
100
Maximum
Unit
10069
symbols
60
ohm
120
ohm
100k
ohm
100
175
mV
120
ohm
750
ppm
Stratix® 10 Device Datasheet
Core Performance Specifications
Clock Tree Specifications
Table 45.
Clock Tree Performance for Stratix 10 Devices—Preliminary
Parameter
Performance
Unit
–E1V, –I1V
–E2V, –E2L, –I2V, –I2L
–E3V, –E3X, –I3V, –I3X
1,100
900
780
Programmable clock routing
MHz
PLL Specifications
Fractional PLL Specifications
Table 46.
Fractional PLL Specifications for Stratix 10 Devices—Preliminary
These specifications are applicable when fPLL is used in core mode.
Symbol
Parameter
Condition
Min
Typ
Max
800
70
Unit
fIN
Input clock frequency
—
29
—
MHz
fINPFD
Input clock frequency to the phase
frequency detector (PFD)
—
29
—
700
MHz
fVCO
PLL voltage-controlled oscillator (VCO)
operating range for transceiver applications
—
6
—
12.5
GHz
PLL voltage-controlled oscillator (VCO)
operating range for core applications
—
4.3
—
12.5
GHz
tEINDUTY
Input clock duty cycle
—
40
—
60
%
fOUT
Output frequency for internal clock
—
—
—
1
GHz
fDYCONFIGCLK
Dynamic configuration clock for
—
—
—
125
MHz
reconfig_clk
continued...
70 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard
and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS
simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
Intel® Stratix 10 Device Datasheet
37
Stratix® 10 Device Datasheet
Symbol
tLOCK
Parameter
Time required to lock from end-of-device
configuration or deassertion of
Condition
Min
Typ
Max
Unit
—
—
—
1
ms
pll_powerdown
tDLOCK
Time required to lock dynamically (after
switchover or reconfiguring any non-postscale counters/delays)
—
—
—
1
ms
fCLBW
PLL closed-loop bandwidth
—
0.3
—
4
MHz
tPLL_PSERR
Accuracy of PLL phase shift
Non-SmartVID
—
—
±50
ps
SmartVID
—
—
±75
ps
—
10
—
—
ns
FREF ≥ 100 MHz
—
—
0.13
UI (p-p)
FREF < 100 MHz
—
—
±650
ps (p-p)
FOUT ≥ 100 MHz
—
—
600
ps (p-p)
FOUT < 100 MHz
—
—
60
mUI (p-p)
FOUT ≥ 100 MHz
—
—
600
ps (p-p)
FOUT < 100 MHz
—
—
60
mUI (p-p)
—
—
32
—
bit
tARESET
tINCCJ
tOUTPJ
71, 72
73
tOUTCCJ
dKBIT
Minimum pulse width on the
pll_powerdown signal
73
Input clock cycle-to-cycle jitter
Period jitter for clock output
Cycle-to-cycle jitter for clock output
Bit number of Delta Sigma Modulator (DSM)
Related Links
Memory Output Clock Jitter Specifications on page 49
Provides more information about the external memory interface clock output jitter specifications.
71 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with
jitter < 120 ps.
72 FREF is fIN/N, specification applies when N = 1.
73 External memory interface clock output jitter specifications use a different measurement method, which are available in Memory
Output Clock Jitter Specifications for Stratix 10 Devices table.
Intel® Stratix 10 Device Datasheet
38
Stratix® 10 Device Datasheet
I/O PLL Specifications
Table 47.
I/O PLL Specifications for Stratix 10 Devices—Preliminary
Symbol
fIN
Parameter
Input clock frequency
fINPFD
Input clock frequency to the PFD
fVCO
PLL VCO operating range
Condition
Min
Typ
–1 speed grade
10
—
1,100
Max
Unit
–2 speed grade
10
—
900
74
MHz
–3 speed grade
10
—
750
74
MHz
—
10
—
325
MHz
–1 speed grade
600
—
1,600
MHz
–2 speed grade
600
—
1,434
MHz
–3 speed grade
600
—
1,250
MHz
74
MHz
fCLBW
PLL closed-loop bandwidth
—
0.5
—
10
MHz
tEINDUTY
Input clock or external feedback clock input
duty cycle
—
40
—
60
%
fOUT
Output frequency for internal clock (C counter)
–1 speed grade
—
—
1,100
MHz
–2 speed grade
—
—
900
MHz
–3 speed grade
—
—
750
MHz
–1 speed grade
—
—
800
MHz
–2 speed grade
—
—
720
MHz
–3 speed grade
—
—
650
MHz
Non-SmartVID
45
50
55
%
SmartVID
42
50
58
%
—
—
—
5
fOUT_EXT
tOUTDUTY
tFCOMP
Output frequency for external clock output
Duty cycle for dedicated external clock output
(when set to 50%)
External feedback clock compensation time
ns
continued...
74 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard
and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS
simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
Intel® Stratix 10 Device Datasheet
39
Stratix® 10 Device Datasheet
Symbol
fDYCONFIGCLK
Parameter
Condition
Min
Typ
Max
Unit
Dynamic configuration clock for mgmt_clk and
—
—
—
200
MHz
scanclk
tLOCK
Time required to lock from end-of-device
configuration or deassertion of areset
—
—
—
1
ms
tDLOCK
Time required to lock dynamically (after
switchover or reconfiguring any non-post-scale
counters/delays)
—
—
—
1
ms
tPLL_PSERR
Accuracy of PLL phase shift
—
—
—
±50
ps
Minimum pulse width on the areset signal
—
10
—
—
ns
FREF ≥ 100 MHz
—
—
0.15
UI (p-p)
FREF < 100 MHz
—
—
±750
ps (p-p)
FOUT ≥ 100 MHz
—
—
175
ps (p-p)
FOUT < 100 MHz
—
—
17.5
mUI (p-p)
FOUT ≥ 100 MHz
—
—
175
ps (p-p)
FOUT < 100 MHz
—
—
17.5
mUI (p-p)
FOUT ≥ 100 MHz
—
—
600
ps (p-p)
FOUT < 100 MHz
—
—
60
mUI (p-p)
FOUT ≥ 100 MHz
—
—
600
ps (p-p)
FOUT < 100 MHz
—
—
60
mUI (p-p)
FOUT ≥ 100 MHz
—
—
175
ps (p-p)
FOUT < 100 MHz
—
—
17.5
mUI (p-p)
tARESET
tINCCJ
7576
Input clock cycle-to-cycle jitter
tOUTPJ_DC
Period jitter for dedicated clock output
tOUTCCJ_DC
tOUTPJ_IO
Cycle-to-cycle jitter for dedicated clock output
77
tOUTCCJ_IO
77
tCASC_OUTPJ_DC
75
Period jitter for clock output on the regular I/O
Cycle-to-cycle jitter for clock output on the
regular I/O
Period jitter for dedicated clock output in
cascaded PLLs
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with
jitter < 120 ps.
76 FREF is fIN/N, specification applies when N = 1.
77 External memory interface clock output jitter specifications use a different measurement method, which are available in Memory
Output Clock Jitter Specifications for Stratix 10 Devices table.
Intel® Stratix 10 Device Datasheet
40
Stratix® 10 Device Datasheet
Related Links
Memory Output Clock Jitter Specifications on page 49
Provides more information about the external memory interface clock output jitter specifications.
DSP Block Specifications
Table 48.
DSP Block Performance Specifications for Stratix 10 Devices—Preliminary
Mode
Performance
Unit
–E1V, –I1V
–E2V, –E2L, –I2V, –
I2L
–E3V, –E3X, –I3V, –
I3X
1,000
771
667
MHz
1,000
771
667
MHz
1,000
771
667
MHz
1,000
771
667
MHz
Fixed-point 18 × 19 systolic mode
1,000
771
667
MHz
Complex 18 × 19 multiplication mode
1,000
771
667
MHz
Floating point multiplication mode
750
579
500
MHz
Floating point adder or subtract mode
750
579
500
MHz
Floating point multiplier adder or subtract mode
750
579
500
MHz
Floating point multiplier accumulate mode
750
579
500
MHz
Floating point vector one mode
750
579
500
MHz
Floating point vector two mode
750
579
500
MHz
Fixed-point 18 × 19 multiplication mode
Fixed-point 27 × 27 multiplication mode
78
Fixed-point 18 × 18 multiplier adder mode
78
Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode
78
78 When chainin or chainout is enabled, the performance specifications for the following speed grades are as follows:
• –E1V and –I1V: 750 MHz
• –E2V, –E2L, –I2V, and –I2L: 578 MHz
• –E3V, –E3X, –I3V, and –I3X: 507 MHz
Intel® Stratix 10 Device Datasheet
41
Stratix® 10 Device Datasheet
Memory Block Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from
an on-chip PLL and set to 50% output duty cycle. Use the Quartus Prime software to report timing for the memory block
clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.
Table 49.
Memory Block Performance Specifications for Stratix 10 Devices—Preliminary
Memory
MLAB
Mode
–E1V, –I1V
–E2V, –E2L, –I2V,
–I2L
–E3V, –E3X, –I3V,
–I3X
Unit
Single port, all supported widths (×16/×32)
1,000
782
667
MHz
Simple dual-port, all supported widths (×16/×32)
1,000
782
667
MHz
550
450
400
MHz
ROM, all supported width (×16/×32)
1,000
782
667
MHz
Single-port, all supported widths
1,000
782
667
MHz
Simple dual-port, all supported widths
1,000
782
667
MHz
Simple dual-port, coherent read enabled
1,000
782
667
MHz
Simple dual-port with the read-during-write option set to
Old Data, all supported widths
800
640
560
MHz
Simple dual-port with ECC enabled, 512 × 32
600
480
420
MHz
1,000
782
667
MHz
True dual port, all supported widths
600
480
420
MHz
Simple quad-port, all supported widths
600
480
420
MHz
1,000
782
667
MHz
500–750
500–700
500–640
MHz
Simple dual-port with read-during-write option
M20K Block
Simple dual-port with ECC and optional pipeline registers
enabled, 512 × 32
ROM, all supported widths
eSRAM
Performance
Simple dual-port
Intel® Stratix 10 Device Datasheet
42
Stratix® 10 Device Datasheet
Internal Temperature Sensing Diode Specifications
Table 50.
Internal Temperature Sensing Diode Specifications for Stratix 10 Devices—Preliminary
Temperature Range
Accuracy
Offset Calibrated Option
Sampling Rate
Conversion
Time
Resolution
Minimum Resolution with
no Missing Codes
–40 to 125 °C
±5 °C
No
1 KSPS
< 5 ms
11 bits
11 bits
Internal Voltage Sensor Specifications
Table 51.
Internal Voltage Sensor Specifications for Stratix 10 Devices—Preliminary
Parameter
Resolution
Minimum
Typical
Maximum
Unit
—
8
—
Bit
Sampling rate
—
—
Differential non-linearity (DNL)
—
—
±1
LSB
Integral non-linearity (INL)
—
—
±1
LSB
Input capacitance
—
—
40
pF
Clock frequency
—
—
550
MHz
Input signal range for Vsigp
0
—
1.5
V
Common mode voltage on Vsign
0
—
0.25
V
Input signal range for Vsigp – Vsign
0
—
1.25
V
Unipolar Input Mode
1.0
79
KSPS
Periphery Performance Specifications
This section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and
perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable
frequency in your system.
79 Pending silicon characterization.
Intel® Stratix 10 Device Datasheet
43
Stratix® 10 Device Datasheet
High-Speed I/O Specifications
Table 52.
High-Speed I/O Specifications for Stratix 10 Devices—Preliminary
When serializer/deserializer (SERDES) factor J = 3 to 10, use the SERDES block.
For LVDS applications, you must use the PLLs in integer PLL mode.
You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter
channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
Symbol
Condition
–E1V, –I1V
–E2V, –E2L, –I2L, –I2V
–E3V, –E3X, –I3X, –I3V
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fHSCLK_in (input clock frequency) True
Differential I/O Standards
Clock boost factor
W = 1 to 40 80
10
—
800
10
—
700
10
—
625
MHz
fHSCLK_in (input clock frequency) SingleEnded I/O Standards
Clock boost factor
W = 1 to 40 80
10
—
625
10
—
625
10
—
525
MHz
—
—
—
—
—
—
—
SERDES factor
J = 4 to 10 838584
85
—
1600
SERDES factor
J = 3 838584
85
—
86
fHSCLK_OUT (output clock frequency)
Transmitter
True Differential I/O
Standards - fHSDR (data
rate) 82
800
81
86
700
85
—
1434
85
—
86
81
86
81
625
85
—
1250
85
—
86
86
MHz
Mbps
Mbps
continued...
80 Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
81 This is achieved by using the PHY clock network.
82 Requires package skew compensation with PCB trace length.
83 The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain
which is design dependent and requires timing analysis.
84 The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
85 The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global,
regional, or local) that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.
86 Pending silicon characterization.
Intel® Stratix 10 Device Datasheet
44
Stratix® 10 Device Datasheet
Symbol
Condition
–E1V, –I1V
Min
tx Jitter - True
Differential I/O
Standards
tDUTY
88
tRISE & tFALL
TCCS
Receiver
8489
8882
True Differential I/O
Standards - fHSDRDPA
(data rate)
Typ
–E2V, –E2L, –I2L, –I2V
Typ
Max
Min
Typ
Max
840
85
—
8687
85
—
8687
Mbps
420
8687
85
—
8687
85
—
8687
Mbps
160
—
—
200
—
—
250
ps
—
0.1
—
—
0.12
—
—
0.15
UI
45
50
55
45
50
55
45
50
55
%
True Differential I/O
Standards
—
—
160
—
—
180
—
—
200
ps
True Differential I/O
Standards
—
—
150
—
—
150
—
—
150
ps
SERDES factor
J = 4 to 10 838584
—
—
1600
—
—
1434
—
—
1250
Mbps
SERDES factor
J = 3 838584
—
—
86
—
—
86
—
—
86
Mbps
SERDES factor J =
2, uses DDR
registers
—
SERDES factor J =
1, uses DDR
registers
85
—
Total jitter for data
rate, 600 Mbps –
1.6 Gbps
—
—
Total jitter for data
rate, < 600 Mbps
—
TX output clock duty
cycle for Differential
I/O Standards
Min
Unit
8687
85
Max
–E3V, –E3X, –I3X, –I3V
continued...
87 The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design
timing and the signal integrity meets the interface requirements.
88 Not applicable for DIVCLK = 1.
89 This applies to default pre-emphasis and VOD settings only.
Intel® Stratix 10 Device Datasheet
45
Stratix® 10 Device Datasheet
Symbol
Condition
–E1V, –I1V
Min
fHSDR (data rate)
(without DPA) 82
–E2V, –E2L, –I2L, –I2V
–E3V, –E3X, –I3X, –I3V
Unit
Typ
Max
Min
Typ
Max
Min
Typ
Max
SERDES factor
J = 3 to 10
85
—
90
85
—
90
85
—
90
Mbps
SERDES factor J =
2, uses DDR
registers
85
—
87
85
—
87
85
—
87
Mbps
SERDES factor J =
1, uses DDR
registers
85
—
87
85
—
87
85
—
87
Mbps
DPA (FIFO mode)
DPA run length
—
—
—
10000
—
—
10000
—
—
10000
UI
DPA (soft CDR
mode)
DPA run length
SGMII/GbE protocol
—
—
5
—
—
5
—
—
5
UI
All other protocols
—
—
50 data
transition
per 208 UI
—
—
50 data
transition
per 208 UI
—
—
50 data
transition
per 208 UI
—
Soft CDR mode
Soft-CDR ppm
tolerance
—
–300
—
300
–300
—
300
–300
—
300
ppm
Non DPA mode
Sampling Window
—
—
—
300
—
—
300
—
—
300
ps
DPA Lock Time Specifications
Figure 2.
DPA Lock Time Specifications with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
96 core
clock cycles
256 data
transitions
96 core
clock cycles
256 data
transitions
90 You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider
the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
Intel® Stratix 10 Device Datasheet
46
Stratix® 10 Device Datasheet
Table 53.
DPA Lock Time Specifications for Stratix 10 Devices—Preliminary
The specifications are applicable to both commercial and industrial grades. The DPA lock time is for one channel. One data transition is defined as a 0-to-1 or 1to-0 transition.
Standard
SPI-4
Training Pattern
Number of Data Transitions in
One Repetition of the Training
Pattern
Number of Repetitions per 256
Data Transitions 91
Maximum Data
Transition
00000000001111111111
2
128
640
00001111
2
128
640
10010000
4
64
640
10101010
8
32
640
01010101
8
32
640
Parallel Rapid I/O
Miscellaneous
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Figure 3.
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
25
Jitter Amplitude(UI)
8.5
0.35
0.1
F1
F2
F3
F4
Jitter Frequency (Hz)
91 This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Intel® Stratix 10 Device Datasheet
47
Stratix® 10 Device Datasheet
Table 54.
LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps—Preliminary
Jitter Frequency (Hz)
Figure 4.
Sinusoidal Jitter (UI)
F1
10,000
25.00
F2
17,565
25.00
F3
1,493,000
0.35
F4
50,000,000
0.35
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications for a Data Rate Less than 1.6 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
baud/1667
20 MHz
Frequency
DLL Range Specifications
Table 55.
DLL Frequency Range Specifications for Stratix 10 Devices—Preliminary
Stratix 10 devices support memory interface frequencies lower than 667 MHz, although the reference clock that feeds the DLL must be at least 667 MHz. To
support interfaces below 667 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported range.
Parameter
DLL operating frequency range
Intel® Stratix 10 Device Datasheet
48
Performance (for All Speed Grades)
Unit
600 – 1,333
MHz
Stratix® 10 Device Datasheet
DQS Logic Block Specifications
Table 56.
DQS Phase Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR) for Stratix 10 Devices—Preliminary
This error specification is the absolute maximum and minimum error.
Symbol
Performance
Unit
–1 Speed Grade
–2 Speed Grade
–3 Speed Grade
4
6
8
tDQS_PSERR
ps
Memory Output Clock Jitter Specifications
Table 57.
Memory Output Clock Jitter Specifications for Stratix 10 Devices—Preliminary
The clock jitter specification applies to the memory output clock pins clocked by an I/O PLL, or generated using differential signal-splitter and double data I/O
circuits clocked by a PLL output routed on a PHY clock network as specified. Intel recommends using PHY clock networks for better jitter performance.
The memory output clock jitter is applicable when an input jitter of 10 ps peak-to-peak is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
Clock
Network
Parameter
PHY clock
Symbol
Performance
Unit
–1 Speed Grade
–2 Speed Grade
–3 Speed Grade
Clock period jitter
tJIT(per)
58
58
58
ps
Cycle-to-cycle period jitter
tJIT(cc)
58
58
58
ps
tJIT(duty)
58
58
58
ps
Duty cycle jitter
OCT Calibration Block Specifications
Table 58.
OCT Calibration Block Specifications for Stratix 10 Devices—Preliminary
Symbol
Description
Min
Typ
Max
Unit
—
—
20
MHz
> 2000
—
—
Cycles
OCTUSRCLK
Clock required by OCT calibration blocks
TOCTCAL
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
TOCTSHIFT
Number of OCTUSRCLK clock cycles required for OCT code to shift out
—
32
—
Cycles
TRS_RT
Time required between the dyn_term_ctrl and oe signal transitions
in a bidirectional I/O buffer to dynamically switch between RS OCT and
RT OCT
—
TBD
—
ns
Intel® Stratix 10 Device Datasheet
49
Stratix® 10 Device Datasheet
Figure 5.
Timing Diagram for on oe and dyn_term_ctrl Signals
RX
Tristate
TX
Tristate
oe
dyn_term_ctrl
TRS_RT
Intel® Stratix 10 Device Datasheet
50
TRS_RT
RX
Stratix® 10 Device Datasheet
HPS Performance Specifications - Preliminary
This section provides hard processor system (HPS) specifications and timing for Stratix 10 devices.
HPS Clock Performance - Preliminary
Table 59.
Maximum HPS Clock Frequencies for Stratix 10 Devices
Performance
–E1V, –I1V
–E2V, –I2V
–E3V, –I3V
–E2L, –I2L93
–E3X, –I3X
93
VCCL_HPS (V)
MPU Frequency (MHz)
SDRAM Interconnect
Frequency92 (MHz)
L3 Interconnect Frequency
(MHz)
SmartVID
1200
533
400
0.9
1200
533
400
0.94
1500
533
400
SmartVID
1000
467
400
0.9
1000
467
400
0.94
1000
467
400
SmartVID
800
400
333
0.9
800
400
333
0.94
1000
400
400
0.9
1200
467
400
0.94
1350
467
400
0.9
1200
400
400
0.94
1350
400
400
Related Links
External Memory Interface Spec Estimator
Provides the specific details of the maximum allowed SDRAM operating frequency, which is twice the frequency of
hmc_free_clk.
92 hmc_free_clk
93 Note that VCCL_HPS can not be connected to SmartVID for –E2L, –I2L, –E3X, and –I3X devices.
Intel® Stratix 10 Device Datasheet
51
Stratix® 10 Device Datasheet
HPS PLL Specifications - Preliminary
HPS PLL Input Requirements - Preliminary
Table 60.
HPS PLL Input Requirements for Stratix 10 Devices
Description
Clock input range
Clock input accuracy
Clock input duty cycle
Min
Typ
Max
Unit
25
TBD
125
MHz
TBD
TBD
50
PPM
45
50
55
%
HPS PLL Performance - Preliminary
Table 61.
HPS PLL Performance for Stratix 10 Devices
Description
Min
Max
Unit
Main PLL VCO output
TBD
3000
MHz
Peripheral PLL VCO output
TBD
3000
MHz
s2f_user0_clk
TBD
500
MHz
s2f_user1_clk
TBD
500
MHz
Intel® Stratix 10 Device Datasheet
52
Stratix® 10 Device Datasheet
SPI Timing Characteristics - Preliminary
Table 62.
SPI Master Timing Requirements for Stratix 10 Devices
You can adjust the input delay timing by programming the rx_sample_dly register.
Symbol
Description
Min
Typ
Max
Unit
16.67
—
—
ns
Tclk
SPIM_CLK clock period
Tdutycycle
SPIM_CLK duty cycle
45
50
55
%
Tck_jitter
SPIM_CLK output jitter
—
—
2
%
Tdio
Master-out slave-in (MOSI) output skew
–3
TBD
2
ns
(1.5 × Tspi_ref_clk) –
2
TBD
TBD
ns
Tspi_ref_clk – 2
TBD
TBD
ns
4 .5 –
(rx_sample_dly
× Tspi_ref_clk) 96 97
TBD
TBD
ns
1.3 +
(rx_sample_dly×
Tspi_ref_clk)
TBD
TBD
ns
Tdssfrst
Tdsslst
Tsu
Th
95
95
94
94
SPI_SS_N asserted to first SPIM_CLK edge
Last SPIM_CLK edge to SPI_SS_N deasserted
SPIM_MISO setup time with respect to SPIM_CLK capture edge
Input hold in respect to SPIM_CLK capture edge
94 SPI_SS_N behavior differs depending on Motorola SPI, TI SSP or Microwire operational mode.
95 The capture edge differs depending on the operational mode. For Motorola SPI, the capture edge can be the rising or falling edge
depending on the scpol register bit; for TI SSP, the capture edge is the falling edge; for Microwire, the capture edge is the rising
edge.
96 A rx_sample_dly value of 0 is an invalid setting.
97 Tspi_ref_clk is the internal reference clock of the SPI Slave, which is l4_main_clk.
Intel® Stratix 10 Device Datasheet
53
Stratix® 10 Device Datasheet
Figure 6.
SPI Master Output Timing Diagram
scph* = 0
Tdssfrst
SPI_SS
Tdsslst
Tdio (max)
Tdio (min)
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
OUT0
OUT1
OUTn
SPI_MISO
scph* = 1
SPI_SS
Tdssfrst
Tdio (max)
Tdsslst
Tdio (min)
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
OUT0
OUT1
SPI_MISO
*Serial clock phase configuration bit, in the SPI controller’s CTRLR0 register
Intel® Stratix 10 Device Datasheet
54
OUTn
Stratix® 10 Device Datasheet
Figure 7.
SPI Master Input Timing Diagram
scph = 0
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
Tsu
SPI_MISO
IN0
Th
IN1
INn
scph = 1
SPI_SS
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MOSI
Tsu
SPI_MISO
IN0
IN1
Th
INn
Intel® Stratix 10 Device Datasheet
55
Stratix® 10 Device Datasheet
Table 63.
SPI Slave Timing Requirements for Stratix 10 Devices
Symbol
Description
Min
Typ
Max
Unit
Tclk
SPIM_CLK clock period
30
—
—
ns
Tdutycycle
SPIM_CLK duty cycle
45
50
55
%
Td
Master-in slave-out (MISO) output skew
(2 × Tspi_ref_clk)
+ 3 98
—
(3 × Tspi_ref_clk)
+ 11 98
ns
Tsu
Master-out slave-in (MOSI) setup time
4
TBD
TBD
ns
Th
Master-out slave-in (MOSI) hold time
0
TBD
TBD
ns
Tsuss
SPI_SS_N asserted to first SPIM_CLK edge
Tspi_ref_clk + 4
TBD
TBD
ns
Thss
Last SPIM_CLK edge to SPI_SS_N deasserted
Tspi_ref_clk + 4
TBD
TBD
ns
98 Tspi_ref_clk is the internal reference clock of the SPI Slave, which is l4_main_clk.
Intel® Stratix 10 Device Datasheet
56
Stratix® 10 Device Datasheet
Figure 8.
SPI Slave Output Timing Diagram
scph = 0
Td (max)
SPI_SS
Td (min)
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
OUT0
OUT1
OUTn
SPI_MOSI
scph = 1
Td (max)
SPI_SS
Td (min)
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
OUT0
OUT1
OUTn
SPI_MOSI
Intel® Stratix 10 Device Datasheet
57
Stratix® 10 Device Datasheet
Figure 9.
SPI Slave Input Timing Diagram
scph = 0
Tsuss
SPI_SS
Thss
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
SPI_MOSI
IN0
scph = 1
SPI_SS
Th
Ts
IN1
INn
Tsuss
Thss
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO
SPI_MOSI
Ts
IN0
IN1
Th
INn
Related Links
SPI Controller
For more information about the SPI controller and timing, refer to the SPI Controller chapter in the Stratix 10 Hard
Processor System Technical Reference Manual
Intel® Stratix 10 Device Datasheet
58
Stratix® 10 Device Datasheet
SD/MMC Timing Characteristics - Preliminary
Table 64.
Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Stratix 10 Devices
These timings apply to SD, MMC, and embedded MMC (eMMC) cards operating at 1.8 V.
Symbol
Min
Typ
Max
Unit
2500
—
—
ns
SDMMC_CCLK clock period (SDR12)
40
—
—
ns
SDMMC_CCLK clock period (SDR25)
20
—
—
ns
Tdutycycle
SDMMC_CCLK duty cycle
45
50
55
%
Tsdmmc_cclk_jitter
SDMMC_CCLK output jitter
—
—
2
%
Tsdmmc_clk
Internal reference clock before division by 4. Sourced by
I4_mp_clk
5
—
—
ns
Td
SDMMC_CMD/SDMMC_DATA[7:0] output delay
Tsdmmc_clk ×
—
3 + (Tsdmmc_clk ×
drvsel/2) 100
ns
Tsu
SDMMC_CMD/SDMMC_DATA[7:0] input setup
6 – (Tsdmmc_clk ×
smplsel/2)
—
—
ns
Th
SDMMC_CMD/SDMMC_DATA[7:0] input hold
0.5 + (Tsdmmc_clk ×
smplsel/2)
—
—
ns
Tsdmmc_cclk
Description
SDMMC_CCLK clock period (Identification mode)
99
101
101
drvsel/2100
These I/Os do not support 3 V mode, so SD/MMC cards must operate at 1.8 V.
Note:
SD cards power up at 3 V. To support SD, your design must include a level shifter.
99 When the drvsel bitfield in the sdmmc register is set to 3 (in the system manager) and the reference clock (l4_mp_clk) is 200 MHz
for example, the output delay time is 7.5 to 10.5 ns.
100 sdmmc_clk, sourced from l4_mp_clk, is the SD/MMC controller reference clock.
101 When the smplsel bitfield in the sdmmc register is set to 2 (in the system manager) and the reference clock (l4_mp_clk) is 200
MHz for example, the setup time is 1 ns and the hold time is 5.5 ns.
Intel® Stratix 10 Device Datasheet
59
Stratix® 10 Device Datasheet
Figure 10.
SD/MMC Timing Diagram
SDMMC_CCLK
Td
SDMMC_CMD and SDMMC_DATA (Out)
Command/Data Out
TSU
Th
SDMMC_CMD and SDMMC_DATA (In)
Command/Data In
Related Links
SD/MMC Controller
For more information about the SD/MMC controller and timing, refer to the SD/MMC Controller chapter in the Stratix 10
Hard Processor System Technical Reference Manual
Intel® Stratix 10 Device Datasheet
60
Stratix® 10 Device Datasheet
USB UPLI Timing Characteristics - Preliminary
Table 65.
USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Stratix
10 Devices
Symbol
Min
Typ
Max
Unit
USB_CLK clock period
TBD
16.667
TBD
ns
Clock to USB_STP/USB_DATA[7:0] output delay
1.5
TBD
7
ns
Tsu
Setup time for USB_DIR/USB_NXT/USB_DATA[7:0]
3.5
TBD
TBD
ns
Th
Hold time for USB_DIR/USB_NXT/USB_DATA[7:0]
0.5
TBD
TBD
ns
Tusb_clk
Td
102
Figure 11.
Description
USB ULPI Timing Diagram
USB_CLK
USB_STP
USB_DATA[7:0]
Td
To PHY
USB_DIR and USB_NXT
From PHY
TSU
Th
Related Links
•
USB Interface Design Guidelines, Stratix 10 SoC Device Design Guidelines
•
USB 2.0 OTG Controller
For more information about the USB 2.0 OTG controller and timing, refer to the USB 2.0 OTG Controller chapter in the
Stratix 10 Hard Processor System Technical Reference Manual
102 For the maximum trace length, refer to the Stratix 10 SoC Device Design Guidelines.
Intel® Stratix 10 Device Datasheet
61
Stratix® 10 Device Datasheet
Ethernet Media Access Controller (EMAC) Timing Characteristics - Preliminary
Table 66.
Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Stratix 10 Devices
Symbol
Description
Min
Typ
Max
Unit
Tclk (1000Base-T)
TX_CLK clock period
8 ± 50 PPM
ns
Tclk (100Base-T)
TX_CLK clock period
40 ± 50 PPM
ns
Tclk (10Base-T)
TX_CLK clock period
400 ± 50 PPM
ns
Tdutycycle (1000Base-T)
TX_CLK duty cycle
45
50
55
%
Tdutycycle(10/100Base-T)
TX_CLK duty cycle
40
50
60
%
–0.5
—
0.5
ns
Min
Typ
Max
Unit
ns
Td
103
TXD/TX_CTL to TX_CLK output skew
104
Figure 12.
RGMII TX Timing Diagram
TX_CLK
TX_D[3:0]
D0
D1
Td
TX_CTL
Table 67.
RGMII RX Timing Requirements for Stratix 10 Devices
Symbol
Description
Tclk (1000Base-T)
RX_CLK clock period
8 - 50 PPM
8
8 + 50 PPM
Tclk (100Base-T)
RX_CLK clock period
40 - 50 PPM
40
40 + 50 PPM
ns
continued...
103 Rise and fall times depend on the I/O standard, drive strength, and loading. Intel recommends simulating your configuration.
104 If you connect a PHY that does not implement clock-to-data skew, you can delay TX_CLK by 1.5—2.0 ms with the HPS I/O
programmable delay, to meet the PHY's 1-ns data-to-clock skew requirement.
Intel® Stratix 10 Device Datasheet
62
Stratix® 10 Device Datasheet
Symbol
Description
Min
Typ
Max
Unit
400 - 50 PPM
400
400 + 50 PPM
ns
Tclk (10Base-T)
RX_CLK clock period
Tdutycycle(1000Base-T)
RX_CLK duty cycle
45
50
55
%
Tdutycycle(10/100Base-T)
RX_CLK duty cycle
40
50
60
%
Tsu
RX_D/RX_CTL to RX_CLK setup time
1
—
—
ns
RX_CLK to RX_D/RX_CTL hold time
1
—
—
ns
Th
105
Figure 13.
RGMII RX Timing Diagram
RX_CLK
TSU
RX_D[3:0]
Th
D0
D1
RX_CTL
Table 68.
Reduced Media Independent Interface (RMII) Clock Timing Requirements for Stratix 10 Devices
Symbol
Tclk
Description
Min
Typ
Max
Unit
REF_CLK clock period, sourced by HPS TX_CLK
20 - 50 PPM
20
20 + 50 PPM
ns
REF_CLK clock period, sourced by external clock source
20 - 50 PPM
20
20 + 50 PPM
ns
Tdutycycle_int
Clock duty cycle, REF_CLK sourced by TX_CLK
35
50
65
%
Tdutycycle_ext
Clock duty cycle, REF_CLK sourced by external clock source
35
50
65
%
Min
Typ
Max
Unit
2
—
10
ns
Table 69.
RMII TX Timing Requirements for Stratix 10 Devices
Symbol
Td
Description
TX_CLK to TXD/TX_CTL output data delay
105 If you connect a PHY that does not implement clock-to-data skew, you can meet the HPS EMAC’s 1 ns setup time by delaying RX_CLK
by 1.5-2 ns, using the HPS I/O programmable delay.
Intel® Stratix 10 Device Datasheet
63
Stratix® 10 Device Datasheet
Table 70.
RMII RX Timing Requirements for Stratix 10 Devices
Symbol
Description
Min
Typ
Max
Unit
Tsu
RX_D/RX_CTL setup time
2
—
—
ns
Th
RX_D/RX_CTL hold time
1
—
—
ns
Table 71.
Management Data Input/Output (MDIO) Timing Requirements for Stratix 10 Devices
Symbol
Description
Min
Typ
Max
Unit
Tclk
MDC clock period
—
400
—
ns
Td
MDC to MDIO output data delay
10
—
20
ns
Tsu
Setup time for MDIO data
10
—
—
ns
Th
Hold time for MDIO data
0
—
—
ns
Figure 14.
MDIO Timing Diagram
MDC
Td
MDIO_OUT
Dout0
Dout1
TSU
MDIO_IN
Th
Din0
Related Links
•
I/O Pin Timing, Stratix 10 SoC Device Design Guidelines
•
Ethernet Media Access Controller
For more information about the Ethernet MAC and timing, refer to the Ethernet Media Access Controller chapter in the
Stratix 10 Hard Processor System Technical Reference Manual
Intel® Stratix 10 Device Datasheet
64
Stratix® 10 Device Datasheet
I2C Timing Characteristics - Preliminary
I2C Timing Requirements for Stratix 10 Devices
Table 72.
Symbol
Tclk
Tclk_jitter
THIGH
TLOW
106
109
TSU;DAT
THD;DAT
Description
Standard Mode
Unit
Min
Max
Min
Max
Serial clock (SCL) clock period
10
—
2.5
—
μs
I2C clock output jitter
—
2
—
SCL high period
SCL low period
4
107
4.7
Setup time for serial data line (SDA) data to SCL
112
Fast Mode
110
—
—
2
%
0.6
108
—
μs
1.3
111
—
μs
μs
0.25
—
0.1
—
0
3.15
0
0.6
Hold time for SCL to SDA data
μs
continued...
106 You can adjust Thigh using the ic_ss_scl_hcnt or ic_fs_scl_hcnt register.
107 The recommended minimum setting for ic_ss_scl_hcnt is 440.
108 The recommended minimum setting for ic_fs_scl_hcnt is 71.
109 You can adjust Tlow using the ic_ss_scl_lcnt or ic_fs_scl_lcnt register.
110 The recommended minimum setting for ic_ss_scl_lcnt is 500.
111 The recommended minimum setting for ic_fs_scl_lcnt is 141.
112 THD;DAT is affected by the rise and fall time.
Intel® Stratix 10 Device Datasheet
65
Stratix® 10 Device Datasheet
Symbol
Description
Standard Mode
Min
TVD;DAT and
TVD;ACK 113
SCL to SDA output data delay
TSU;STA
Setup time for a repeated start condition
THD;STA
—
Fast Mode
Max
3.45
114
Min
—
Unit
Max
0.9
115
μs
4.7
—
0.6
—
μs
Hold time for a repeated start condition
4
—
0.6
—
μs
TSU;STO
Setup time for a stop condition
4
—
0.6
—
μs
TBUF
SDA high pulse duration between STOP and START
4.7
—
1.3
—
μs
1000
20
300
ns
Tscl:r
116
SCL rise time
—
Tscl:f
116
SCL fall time
—
300
6.54
300
ns
Tsda:r
116
SDA rise time
—
1000
20
300
ns
Tsda:f
116
SDA fall time
—
300
6.54
300
ns
113 TVD;DAT and TVD;ACK is affected by the rise and fall time, in addition to the SDA hold time that is set by adjusting the ic_sda_hold
register.
114 Use maximum SDA_HOLD = 240 to be within the specification.
115 Use maximum SDA_HOLD = 60 to be within the specification.
116 Rise and fall time parameters vary depending on the external factors such as: characteristics of IO driver, pull-out resistor value, and
total capacitance on the transmission line.
Intel® Stratix 10 Device Datasheet
66
Stratix® 10 Device Datasheet
Figure 15.
I2C Timing Diagram
tf
tr
tSU;DAT
70%
30%
SDA
tHD;DAT
tf
tHIGH
tr
tVD;DAT
70%
30%
SCL
tHD;STA
Tclk
tLOW
tBUF
70%
30%
SDA
tSU;STA
tHD;STA
tVD;ACK
tSU;STO
70%
30%
SCL
Related Links
I2C Controller
For more information about the I2C controller and timing, refer to the I2C Controller chapter in the Stratix 10 Hard
Processor System Technical Reference Manual
Intel® Stratix 10 Device Datasheet
67
Stratix® 10 Device Datasheet
NAND Timing Characteristics - Preliminary
Table 73.
NAND ONFI 1.0 Timing Requirements for Stratix 10 Devices
Symbol
Description
TWP
117
Write enable pulse width
TWH
117
Write enable hold time
TRP
117
Read enable pulse width
TREH
117
Read enable hold time
TCLS
117
Command latch enable to write enable setup time
TCLH
117
Command latch enable to write enable hold time
TCS
117
Chip enable to write enable setup time
TCH
117
Chip enable to write enable hold time
TALS
117
Address latch enable to write enable setup time
TALH
117
Min
Max
Unit
10
—
ns
7
—
ns
10
—
ns
7
—
ns
10
—
ns
5
—
ns
15
—
ns
5
—
ns
10
—
ns
Address latch enable to write enable hold time
5
—
ns
TDS
117
Data to write enable setup time
7
—
ns
TDH
117
Data to write enable hold time
5
—
ns
TWB
117
Write enable high to R/B low
—
200
ns
TCEA
Chip enable to data access time
—
100
ns
TREA
Read enable to data access time
—
40
ns
TRHZ
Read enable to data high impedance
—
200
ns
TRR
Ready to read enable low
20
—
ns
117 This timing is software programmable. Refer to the NAND Flash Controller chapter in the Stratix 10 Hard Processor System Technical
Reference Manual for more information about software-programmable timing in the NAND flash controller.
Intel® Stratix 10 Device Datasheet
68
Stratix® 10 Device Datasheet
Figure 16.
NAND Command Latch Timing Diagram
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALS
tALH
ALE
tDS
IO0-7
R/B
tDH
Command
tWB
Intel® Stratix 10 Device Datasheet
69
Stratix® 10 Device Datasheet
Figure 17.
NAND Address Latch Timing Diagram
tCLS
CLE
tCS
CE
tWP
WE
ALE
IO0-7
Intel® Stratix 10 Device Datasheet
70
tWH
tALS
tALH
tDS
tDH
Address
Stratix® 10 Device Datasheet
Figure 18.
NAND Data Output Cycle Timing Diagram
tCLH
CLE
tCH
CE
tWP
WE
tWH
tALS
ALE
tDS
tDH
tDS
DOUT 0
IOx
Figure 19.
tWP
tWP
tDH
tDS
DOUT 1
tDH
DOUT n
NAND Data Input Cycle Timing Diagram
tCEA
CE
tRP
tRP
RE
tREH
tRR
R/B
IOx
tRP
tREA
tRHZ
DIN 0
tREA
tRHZ
DIN 1
tREA
tRHZ
DIN n
Intel® Stratix 10 Device Datasheet
71
Stratix® 10 Device Datasheet
Figure 20.
NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
CE
tRP
RE
tREH
tRR
tREA
R/B
tRHZ
IOx
DIN 0
tCEA
Intel® Stratix 10 Device Datasheet
72
tREA
DIN 1
DIN n
Stratix® 10 Device Datasheet
Figure 21.
NAND Read Status Timing Diagram
CLE
tCLS
tCLH
tCS
tCH
tCEA
CE
WE
RE
IO0-7
tWP
tRHZ
tDS
tDH
70h
Status
tREA
Intel® Stratix 10 Device Datasheet
73
Stratix® 10 Device Datasheet
Figure 22.
NAND Read Status Enhanced Timing Diagram
CLE
tCLS
tCLH
tCH
tCS
tCEA
CE
tWP
WE
tALH
tWP
tALS
tWH
tALH
ALE
RE
tDS
IO0-7
tREA
tDH
78h
R1
R2
R3
tRHZ
Status
Related Links
NAND Flash Controller
Refer to the NAND Flash Controller chapter in the Stratix 10 Hard Processor System Technical Reference Manual for more
information about the NAND flash controller and timing, particularly software-programmable timing.
Intel® Stratix 10 Device Datasheet
74
Stratix® 10 Device Datasheet
Trace Timing Characteristics - Preliminary
Table 74.
Trace Timing Requirements for Stratix 10 Devices
To increase the trace bandwidth, Intel® recommends routing the trace interface to the FPGA in the HPS Qsys component. The FPGA trace interface offers a 64-bit
single data rate path that can be converted to double data rate to minimize FPGA I/O usage.
Depending on the trace module that you connect to the HPS trace interface, you may need to include board termination to achieve the maximum sampling speed
possible. Refer to your trace module datasheet for termination recommendations.
Most trace modules implement programmable clock and data skew, to improve trace data timing margins. Alternatively, you can change the clock-to-data timing
relationship with the HPS programmable I/O delay.
Symbol
Description
Min
Typ
Max
Unit
6.667
—
—
ns
Tclk
Trace clock period
Tclk_jitter
Trace clock output jitter
—
—
2
%
Tdutycycle
Trace clock maximum duty cycle
45
50
55
%
Td
Tclk to D0–D15 output data delay
0
—
1.8
ns
Figure 23.
Trace Timing Diagram
Clock (DDR)
Trace Data (DDR)
Td
Intel® Stratix 10 Device Datasheet
75
Stratix® 10 Device Datasheet
GPIO Interface - Preliminary
The general-purpose I/O (GPIO) interface has debounce circuitry included to remove signal glitches. The debounce clock
frequency ranges from 125 Hz to 32 kHz. The minimum pulse width is 1 debounce clock cycle and the minimum detectable
GPIO pulse width is 62.5 µs (at 32 kHz). Any pulses shorter than 2 debounce clock cycles are filtered by the GPIO peripheral.
If the external signal is less than one clock cycle, the external signal is filtered. If the external signal is between one and two
clock cycles, the external signal may or may not be filtered depending on the phase of the signal. If the external signal is
more than two clock cycles, the external signal will not be filtered.
Related Links
General-Purpose I/O Interface
For more information about the GPIO interface and timing, refer to the General-Purpose I/O Interface chapter in the
Stratix 10 Hard Processor System Technical Reference Manual
Intel® Stratix 10 Device Datasheet
76
Stratix® 10 Device Datasheet
HPS JTAG Timing Characteristics - Preliminary
Table 75.
HPS JTAG Timing Requirements for Stratix 10 Devices
Symbol
Description
Min
Typ
Max
Unit
41.66
—
—
ns
tJCP
TCK clock period
tJCH
TCK clock high time
20
—
—
ns
tJCL
TCK clock low time
20
—
—
ns
tJPSU (TDI)
TDI JTAG port setup time
5
—
—
ns
tJPSU (TMS)
TMS JTAG port setup time
5
—
—
ns
tJPH
JTAG port hold time
0
—
—
ns
tJPCO
JTAG port clock to output
0
—
8
ns
tJPZX
JTAG port high impedance to valid output
—
—
10
ns
tJPXZ
JTAG port valid output to high impedance
—
—
10
ns
Intel® Stratix 10 Device Datasheet
77
Stratix® 10 Device Datasheet
Programmable I/O Timing Characteristics - Preliminary
Table 76.
Programmable I/O Delay for Stratix 10 Device
Each delay step is approximately 150 ps.
Programmable
Delay
0, 2, 4, 6, 8, 10,
12, 14, 16, 18, 20,
22, 24, 26, 28, 30
Description
No I/O delay enabled
Min
Typ
Max
Unit
0
0
0
ps
1
Delay Step 1
TBD
TBD
TBD
ps
3
Delay Step 2
TBD
TBD
TBD
ps
5
Delay Step 3
TBD
TBD
TBD
ps
7
Delay Step 4
TBD
TBD
TBD
ps
9
Delay Step 5
TBD
TBD
TBD
ps
11
Delay Step 6
TBD
TBD
TBD
ps
13
Delay Step 7
TBD
TBD
TBD
ps
15
Delay Step 8
TBD
TBD
TBD
ps
17
Delay Step 9
TBD
TBD
TBD
ps
19
Delay Step 10
TBD
TBD
TBD
ps
21
Delay Step 11
TBD
TBD
TBD
ps
23
Delay Step 12
TBD
TBD
TBD
ps
25
Delay Step 13
TBD
TBD
TBD
ps
27
Delay Step 14
TBD
TBD
TBD
ps
29
Delay Step 15
TBD
TBD
TBD
ps
31
Delay Step 16
TBD
TBD
TBD
ps
Intel® Stratix 10 Device Datasheet
78
Stratix® 10 Device Datasheet
Configuration Specifications
POR Specifications
Power-on reset (POR) delay is defined as the delay between the time when all the power supplies monitored by the POR
circuitry reach the minimum recommended operating voltage to the time when the nSTATUS is released high and your device
is ready to begin configuration.
Table 77.
POR Delay Specification for Stratix 10 Devices
POR Delay
Minimum
Maximum
Unit
12
20
ms
2
6.5
ms
AS (Normal mode), AVST ×8, AVST ×16, AVST ×32, NAND,
SD/MMC
AS (Fast mode)
External Configuration Clock Source Requirements
Table 78.
External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements—Preliminary
Description
Clock input frequency
118
External Clock Source
Min
Powered by VCCIO_SDM
Typ
Max
25/100/125
Unit
MHz
Clock input jitter tolerance
—
—
2
%
Clock input duty cycle
45
50
55
%
118 The acceptable clock frequencies are 25 MHz, 100 MHz, and 125 MHz only. Other frequencies in the range are not supported.
Intel® Stratix 10 Device Datasheet
79
Stratix® 10 Device Datasheet
JTAG Configuration Timing
Table 79.
JTAG Timing Parameters and Values for Stratix 10 Devices—Preliminary
Symbol
Description
Requirement
Minimum
tJCP
TCK clock period
tJCH
TCK clock high time
tJCL
TCK clock low time
tJPSU (TDI)
Maximum
—
ns
14
—
ns
14
—
ns
TDI JTAG port setup time
2
—
ns
tJPSU (TMS)
TMS JTAG port setup time
3
—
ns
tJPH
JTAG port hold time
5
—
ns
tJPCO
JTAG port clock to output
—
7
ns
tJPZX
JTAG port high impedance to valid output
—
14
ns
tJPXZ
JTAG port valid output to high impedance
—
14
ns
Figure 24.
30, 167
119
Unit
JTAG Timing Diagram
TMS
TDI
tJCH
TCK
tJCP
tJCL
tJPZX
tJPSU
tJPCO
tJPH
tJPXZ
TDO
119 The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.8 V when you perform the volatile key programming.
Intel® Stratix 10 Device Datasheet
80
Stratix® 10 Device Datasheet
AS Configuration Timing
Table 80.
AS Timing Parameters for Stratix 10 Devices—Preliminary
Intel recommends performing trace length matching for nCSO and AS_DATA pins to AS_CLK to minimize the skew. The maximum tolerance for skew between
nCSO and AS_CLK is less than 200 ps. The tolerance for skew between AS_DATA and AS_CLK ranges between 200 ps – 400 ps.
Symbol
Description
Tclk
AS_CLK clock period
Tdutycycle
AS_CLK duty cycle
Minimum
Typical
Maximum
Unit
7.52
—
—
ns
45
50
55
%
Tdcsfrs
AS_nCSO[3:0] asserted to first AS_CLK edge
4.21
120
Tdcslst
Last AS_CLK edge to AS_nCSO[3:0] deasserted
5.18
120
Tdo
AS_DATA0 output delay
0
—
1.31
ns
Total external propagation delay on AS signals
0
—
15
ns
Text_skew
Skew delay for AS_DATA signals
—
—
2
ns
Tdcsb2b
Minimum delay of slave select deassertion between two backto-back transfers
1
—
—
AS_CLK
Text_delay
121
—
—
6.05
120
ns
7.03
120
ns
120 AS operating at maximum clock frequency = 133 MHz. The delay is larger when operating at AS clock frequency lower than 133 MHz.
121 Text_delay = Tbd_clk + Tco + Tbd_data + Tadd
Tbd_clk: Propagation delay for AS_CLK between FPGA and flash device.
Tco: Output hold time of flash device.
Tbd_data: Propagation delay for AS_DATA bus between FPGA and flash device.
Tadd: Propagation delay for active/passive components on AS_DATA interfaces.
Intel® Stratix 10 Device Datasheet
81
Stratix® 10 Device Datasheet
Figure 25.
AS Configuration Serial Output Timing Diagram
Tdcsfrs Tdo (min)
Tdcslst
Tdo (max)
nCSO
AS_CLK
OUT0
AS_DATA
Figure 26.
OUT1
OUTn
AS Configuration Serial Input Timing Diagram
nCSO
AS_CLK
Text_delay
AS_DATA
IN0
IN1
INn
Avalon-ST Configuration Timing
Table 81.
Avalon-ST Timing Parameters for ×8, ×16, and ×32 Configurations in Stratix 10 Devices—Preliminary
Symbol
Description
Minimum
Maximum
Unit
tST0
nSTATUS low pulse during configuration error
0.5
1.5
ms
tACLKH
AVST_CLK high time
3.6
—
ns
tACLKL
AVST_CLK low time
3.6
—
ns
tACLKP
AVST_CLK period
8
—
ns
5.5
—
tADSU
122
AVST_DATA setup time before rising edge of AVST_CLK
ns
continued...
Intel® Stratix 10 Device Datasheet
82
Stratix® 10 Device Datasheet
Symbol
tADH
122
Description
Maximum
Unit
0
—
ns
5.5
—
ns
0
—
ns
AVST_DATA hold time after rising edge of AVST_CLK
tAVSU
AVST_VALID setup time before rising edge of AVST_CLK
tAVDH
AVST_VALID hold time after rising edge of AVST_CLK
Figure 27.
Minimum
Avalon-ST Configuration Timing Diagram
tACLKP
tACLKH
tACLKL
AVSTx8_CLK (1)
AVST_READY (2)
tAVSU
tAVDH
tADSU
tADH
AVSTx8_VALID (3), (4)
AVSTx8_DATA (5), (6)
Byte 1 Byte 2 Byte 3
Notes:
1. For Avalon-ST x16 and x32, this signal is AVST_CLK. These clocks must be running throughout the configuration
(until CONF_DONE goes high).
2. AVST_READY is valid only when nSTATUS is high. AVST_READY is an asynchronous signal to AVSTx8_CLK.
3. For Avalon-ST x16 and x32, this signal is AVST_VALID.
4. The waveforms shows the interface signals with a host which uses ready latency =2. The AVSTx8_VALID signal is delayed from
AVST_READY signal by 2 clock cycles.
5. For Avalon-ST x16 and x32, this signal is AVST_DATA[15:0] and AVST_DATA[31:0] respectively.
6. Host may send up to 6 more data after AVST_READY has de-asserted.
122 Data sampled by the FPGA (sink) at the next rising clock edge.
Intel® Stratix 10 Device Datasheet
83
Stratix® 10 Device Datasheet
NAND Configuration Timing
Table 82.
NAND ONFI 1.0 Mode 0-5 Timing Requirements for Stratix 10 Devices—Preliminary
This table shows Mode 5 timing.
Symbol
Description
Minimum
Maximum
Unit
10
—
ns
7
—
ns
10
—
ns
7
—
ns
10
—
ns
5
—
ns
15
—
ns
5
—
ns
10
—
ns
tWP
Write enable pulse width
tWH
Write enable hold time
tRP
Read enable pulse width
tREH
Read enable hold time
tCLS
Command latch enable to write enable setup time
tCLH
Command latch enable to write enable hold time
tCS
Chip enable to write enable setup time
tCH
Chip enable to write enable hold time
tALS
Address latch enable to write enable setup time
tALH
Address latch enable to write enable hold time
5
—
ns
tDS
Data to write enable setup time
7
—
ns
tDH
Data to write enable hold time
5
—
ns
tCEA
Chip enable to data access time
—
100
ns
tREA
Read enable to data access time
—
40
ns
tRHZ
Read enable to data high impedance
—
200
ns
tRR
Ready to read enable low
20
—
ns
tWB
Write enable high to R/B low
—
200
ns
Intel® Stratix 10 Device Datasheet
84
Stratix® 10 Device Datasheet
Figure 28.
NAND Command Latch Timing Diagram
NAND_CLE
tCLS
tCLH
tCS
tCH
NAND_CE_N
tWP
NAND_WE_N
tALS
tALH
NAND_ALE
tDS
NAND_ADQ[7:0]
NAND_RB
tDH
Command
tWB
Intel® Stratix 10 Device Datasheet
85
Stratix® 10 Device Datasheet
Figure 29.
NAND Address Latch Timing Diagram
tCLS
NAND_CLE
tCS
NAND_CE_N
tWP
NAND_WE_N
NAND_ALE
NAND_ADQ[7:0]
Intel® Stratix 10 Device Datasheet
86
tWH
tALS
tALH
tDS
tDH
Address
Stratix® 10 Device Datasheet
Figure 30.
NAND Data Output Cycle Timing Diagram
tCLH
NAND_CLE
tCH
NAND_CE_N
tWP
NAND_WE_N
tWH
tALS
NAND_ALE
tDS
tDH
tDS
DOUT 0
NAND_ADQ[7:0]
Figure 31.
tWP
tWP
tDH
tDS
DOUT 1
tDH
DOUT n
NAND Data Input Cycle Timing Diagram
tCEA
NAND_CE_N
tRP
tRP
NAND_RE_N
tREH
tRR
NAND_RB
NAND_ADQ[7:0]
tRP
tREA
tRHZ
DIN 0
tREA
tRHZ
DIN 1
tREA
tRHZ
DIN n
Intel® Stratix 10 Device Datasheet
87
Stratix® 10 Device Datasheet
Figure 32.
NAND Data Input Timing Diagram for Extended Data Output (EDO) Cycle
CE
tRP
RE
tREH
tRR
tREA
R/B
tRHZ
IOx
DIN 0
tCEA
Intel® Stratix 10 Device Datasheet
88
tREA
DIN 1
DIN n
Stratix® 10 Device Datasheet
Figure 33.
NAND Read Status Timing Diagram
CLE
tCLS
tCLH
tCS
tCH
tCEA
CE
WE
RE
IO0-7
tWP
tRHZ
tDS
tDH
70h
Status
tREA
Intel® Stratix 10 Device Datasheet
89
Stratix® 10 Device Datasheet
Figure 34.
NAND Read Status Enhanced Timing Diagram
CLE
tCLS
tCLH
tCH
tCS
tCEA
CE
tWP
WE
tALH
tWP
tALS
tWH
tALH
ALE
RE
tDS
78h
IO0-7
tREA
tDH
R1
R2
R3
tRHZ
Status
SD/MMC Configuration Timing
Table 83.
SD/MMC Timing Parameters for Stratix 10 Devices—Preliminary
Symbol
Minimum
Typical
Maximum
Unit
SDMMC_CFG_CCLK clock period (Identification mode)
2,500
—
—
ns
SDMMC_CFG_CCLK clock period (Standard SD mode)
40
—
—
ns
SDMMC_CFG_CCLK clock period (High-speed SD mode)
20
—
—
ns
tDUTYCYCLE
SDMMC_CFG_CCLK duty cycle
45
50
55
%
td
SDMMC_CFG_CMD/SDMMC_CFG_DATA output delay
7.3
—
10.1
ns
tSU
SDMMC_CFG_CMD/SDMMC_CFG_DATA input setup
4.37
—
—
ns
tH
SDMMC_CFG_CMD/SDMMC_CFG_DATA input hold
0
—
—
ns
tSDCLKP
Description
Intel® Stratix 10 Device Datasheet
90
Stratix® 10 Device Datasheet
Figure 35.
SD/MMC Timing Diagram
SDMMC_CFG_CCLK
td
SDMMC_CFG_CMD and SDMMC_CFG_DATA (Out)
Command/Data Out
tSU
tH
SDMMC_CFG_CMD and SDMMC_CFG_DATA (In)
Command/Data In
Initialization
Table 84.
Initialization Time for Stratix 10 Devices—Preliminary
Configuration Scheme
AS, AVST ×8, AVST ×16, AVST ×32, NAND, SD/MMC
Maximum duration required for initialization
2 ms
123
Configuration Bit Stream Sizes
Table 85.
Configuration Bit Stream Sizes for Stratix 10 Devices—Preliminary
This table shows the estimated configuration bit stream sizes of the EPCQ-L serial configuration device or external flash size before design compilation. The sizes
are for compressed bit stream. The actual sizes may vary based on your design. The actual sizes may be equal or smaller than the bit stream sizes in this table.
Variant
Stratix 10 GX
Product Line
Compressed Configuration Bit Stream Size (Mbits)
GX 400, GX 650
79
GX 850, GX 1100
133
GX 1650, GX 2100
227
GX 2500, GX 2800
336
continued...
123 This specification is the initialization time that indicates the time from CONF_DONE signal goes high to INIT_DONE signal goes high.
Intel® Stratix 10 Device Datasheet
91
Stratix® 10 Device Datasheet
Variant
Stratix 10 SX
Product Line
Compressed Configuration Bit Stream Size (Mbits)
GX 4500, GX 5500
448
SX 400, SX 650
79
SX 850, SX 1100
133
SX 1650, SX 2100
227
SX 2500, SX 2800
336
SX 4500, SX 5500
448
Minimum Configuration Time Estimation
Hyper Initialization is an option that can be enabled or disabled through the setting in the Quartus Prime software to initialize
or reset the HyperFlex registers to a known state at device configuration.
Maximum configuration time does not exceed 2× of the minimum configuration time.
Table 86.
Minimum Configuration Time Estimation for Stratix 10 Devices (JTAG and Avalon-ST)—Preliminary
Variant
Product Line
Minimum Configuration Time (ms) [Hyper Initialization Off/Hyper Initialization On]
JTAG
Stratix 10 GX
AVST ×8
AVST ×16
AVST ×32
170 – 230
MHz Internal
Clock (Using
Internal
Clock
Source)
250 MHz
Internal
Clock (Using
External
Clock
Source)
170 – 230
MHz Internal
Clock (Using
Internal
Clock
Source)
250 MHz
Internal
Clock (Using
External
Clock
Source)
170 – 230
MHz Internal
Clock (Using
Internal
Clock
Source)
250 MHz
Internal
Clock (Using
External
Clock
Source)
170 – 230
MHz Internal
Clock (Using
Internal
Clock
Source)
250 MHz
Internal
Clock (Using
External
Clock
Source)
GX 400, GX
650
3000/3100
3000/3100
137/167
91/111
77/108
51/72
60/92
40/61
GX 850, GX
1100
5300/5600
5300/5600
228/284
152/189
123/179
82/119
95/150
63/100
GX 1650, GX
2100
9000/9500
9000/9500
377/426
251/284
197/248
131/165
107/158
71/105
GX 2500, GX
2800
13300/14000
13300/14000
551/620
367/413
284/354
189/236
150/221
100/147
continued...
Intel® Stratix 10 Device Datasheet
92
Stratix® 10 Device Datasheet
Variant
Product Line
Minimum Configuration Time (ms) [Hyper Initialization Off/Hyper Initialization On]
JTAG
Stratix 10 SX
Table 87.
AVST ×8
AVST ×16
AVST ×32
170 – 230
MHz Internal
Clock (Using
Internal
Clock
Source)
250 MHz
Internal
Clock (Using
External
Clock
Source)
170 – 230
MHz Internal
Clock (Using
Internal
Clock
Source)
250 MHz
Internal
Clock (Using
External
Clock
Source)
170 – 230
MHz Internal
Clock (Using
Internal
Clock
Source)
250 MHz
Internal
Clock (Using
External
Clock
Source)
170 – 230
MHz Internal
Clock (Using
Internal
Clock
Source)
250 MHz
Internal
Clock (Using
External
Clock
Source)
GX 4500, GX
5500
17600/18700
17600/18700
723/831
482/554
371/480
247/320
194/303
129/202
SX 400, SX
650
3000/3100
3000/3100
137/167
91/111
77/108
51/72
60/92
40/61
SX 850, SX
1100
5300/5600
5300/5600
228/284
152/189
123/179
82/119
95/150
63/100
SX 1650, SX
2100
9000/9500
9000/9500
377/426
251/284
197/248
131/165
107/158
71/105
SX 2500, SX
2800
13300/14000
13300/14000
551/620
367/413
284/354
189/236
150/221
100/147
SX 4500, SX
5500
17600/18700
17600/18700
723/831
482/554
371/480
247/320
194/303
129/202
Minimum Configuration Time Estimation for Stratix 10 Devices (AS, NAND, and SD/MMC)—Preliminary
Variant
Product Line
Minimum Configuration Time (ms) [Hyper Initialization Off/Hyper Initialization On]
AS ×4
Stratix 10 GX
NAND
SD/MMC
170 – 230 MHz
Internal Clock
(Using Internal
Clock Source)
250 MHz Internal
Clock (Using
External Clock
Source)
170 – 230 MHz
Internal Clock
(Using Internal
Clock Source)
250 MHz Internal
Clock (Using
External Clock
Source)
170 – 230 MHz
Internal Clock
(Using Internal
Clock Source)
250 MHz Internal
Clock (Using
External Clock
Source)
GX 400, GX 650
284/315
189/210
366/396
244/264
366/396
244/264
GX 850, GX 1100
450/506
300/337
597/653
398/435
597/653
398/435
GX 1650, GX 2100
716/767
477/511
966/1017
644/678
966/1017
644/678
GX 2500, GX 2800
1029/1100
686/733
1403/1472
935/981
1403/1472
935/981
GX 4500, GX 5500
1338/1449
892/966
1800/1950
1200/1300
1800/1950
1200/1300
continued...
Intel® Stratix 10 Device Datasheet
93
Stratix® 10 Device Datasheet
Variant
Product Line
Minimum Configuration Time (ms) [Hyper Initialization Off/Hyper Initialization On]
AS ×4
Stratix 10 SX
NAND
SD/MMC
170 – 230 MHz
Internal Clock
(Using Internal
Clock Source)
250 MHz Internal
Clock (Using
External Clock
Source)
170 – 230 MHz
Internal Clock
(Using Internal
Clock Source)
250 MHz Internal
Clock (Using
External Clock
Source)
170 – 230 MHz
Internal Clock
(Using Internal
Clock Source)
250 MHz Internal
Clock (Using
External Clock
Source)
SX 400, SX 650
284/315
189/210
366/396
244/264
366/396
244/264
SX 850, SX 1100
450/506
300/337
597/653
398/435
597/653
398/435
SX 1650, SX 2100
716/767
477/511
966/1017
644/678
966/1017
644/678
SX 2500, SX 2800
1029/1100
686/733
1403/1472
935/981
1403/1472
935/981
SX 4500, SX 5500
1338/1449
892/966
1800/1950
1200/1300
1800/1950
1200/1300
I/O Timing
The Quartus Prime Timing Analyzer provides accurate and precise I/O timing data based on the specifics of the design after
you complete place-and-route.
The I/O Timing specifications will be available in a future release of the Stratix 10 Device Datasheet.
Glossary
Table 88.
Glossary
Term
Differential I/O Standards
Definition
Receiver Input Waveforms
continued...
Intel® Stratix 10 Device Datasheet
94
Stratix® 10 Device Datasheet
Term
Definition
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
Ground
Differential Waveform
VID
p-n=0V
VID
Transmitter Output Waveforms
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
VCM
Ground
Differential Waveform
VOD
p-n=0V
VOD
fHSCLK
I/O PLL input clock frequency.
fHSDR
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
fHSDRDPA
High-speed I/O block—Maximum/minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
J
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications
JTAG Timing Specifications:
continued...
Intel® Stratix 10 Device Datasheet
95
Stratix® 10 Device Datasheet
Term
Definition
TMS
TDI
t JCH
t JCP
t JCL
tJPH
t JPSU
TCK
tJPZX
t JPXZ
tJPCO
TDO
RL
Receiver differential input discrete resistor (external to the Stratix 10 device).
Sampling window (SW)
Timing Diagram—the period of time during which the data must be valid in order to capture it correctly. The setup and hold
times determine the ideal strobe position in the sampling window, as shown:
Bit Time
0.5 x TCCS
Single-ended voltage referenced I/O standard
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the
voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which
the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to
provide predictable receiver timing in the presence of input waveform ringing.
Single-Ended Voltage Referenced I/O Standard
continued...
Intel® Stratix 10 Device Datasheet
96
Stratix® 10 Device Datasheet
Term
Definition
V CCIO
V OH
V IH(AC)
V REF
V IH(DC)
V IL(DC)
V IL(AC)
V OL
V SS
tC
High-speed receiver/transmitter input and output clock period.
TCCS (channel-to-channel-skew)
The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across
channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure
under SW in this table).
tDUTY
High-speed I/O block—Duty cycle on high-speed transmitter output clock.
tFALL
Signal high-to-low transition time (80–20%).
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input.
tOUTPJ_IO
Period jitter on the GPIO driven by a PLL.
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL.
tRISE
Signal low-to-high transition time (20–80%).
Timing Unit Interval (TUI)
The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w).
VCM(DC)
DC Common mode input voltage.
VICM
Input Common mode voltage—The common mode of the differential signal at the receiver.
VICM(DC)
VCM(DC) DC Common mode input voltage.
VID
Input differential voltage swing—The difference in voltage between the positive and complementary conductors of a
differential transmission at the receiver.
VDIF(AC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
VDIF(DC)
DC differential input voltage— Minimum DC input differential voltage required for switching.
continued...
Intel® Stratix 10 Device Datasheet
97
Stratix® 10 Device Datasheet
Term
Definition
VIH
Voltage input high—The minimum positive voltage applied to the input which is accepted by the device as a logic high.
VIH(AC)
High-level AC input voltage.
VIH(DC)
High-level DC input voltage.
VIL
Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as a logic low.
VIL(AC)
Low-level AC input voltage.
VIL(DC)
Low-level DC input voltage.
VOCM
Output Common mode voltage—The common mode of the differential signal at the transmitter.
VOD
Output differential voltage swing—The difference in voltage between the positive and complementary conductors of a
differential transmission line at the transmitter.
VSWING
Differential input voltage.
VIX
Input differential cross point voltage.
VOX
Output differential cross point voltage.
VX(AC)
VIX Input differential cross point voltage.
W
High-speed I/O block—Clock Boost Factor.
Document Revision History
Date
May 2017
Version
2017.05.08
Changes
•
•
•
•
•
Updated description for VCCERAM in Absolute Maximum Ratings for Stratix 10 Devices table.
Added Maximum Allowed Overshoot During Transitions for Stratix 10 Devices table.
Updated Recommended Operating Conditions for Stratix 10 Devices table.
— Updated VCC, VCCIO, and VCCBAT specifications.
— Updated symbol from VCCPFUSE_SDM to VCCFUSEWR_SDM.
— Updated description for VCCERAM and VCCIO_UIB .
— Added VCCM specifications.
— Added footnotes to tRAMP and V suffix speed grades.
Removed table: Temperature Compensation for SmartVID for Stratix 10 Devices.
Updated the note in the "Transceiver Power Supply Operating Conditions" section.
continued...
Intel® Stratix 10 Device Datasheet
98
Stratix® 10 Device Datasheet
Date
Version
Changes
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
February 2017
2017.02.17
Updated HPS Power Supply Operating Conditions for Stratix 10 Devices table.
— Updated VCCL_HPS and VCCPLLDIG_HPS specifications.
— Added footnote for SmartVID.
Updated footnote to IOL and IOH in Single-Ended I/O Standards Specifications for Stratix 10 Devices table.
Updated Differential I/O Standards Specifications for Stratix 10 Devices table.
— Changed DMAX to data rate.
— Added a note to VOD.
Updated tOUTPJ_DC and tOUTCCJ_DC specifications in I/O PLL Specifications for Stratix 10 Devices.
Changed the units of measure for the minimum frequency in the "L-Tile CMU PLL Performance" table.
Changed the units of measure for the minimum frequency in the "H-Tile CMU PLL Performance" table.
Updated tINCCJ specification for FREF < 100 MHz in the following tables:
— Fractional PLL Specifications for Stratix 10 Devices
— I/O PLL Specifications for Stratix 10 Devices
Added footnote to the following modes in DSP Block Performance Specifications for Stratix 10 Devices table:
— Fixed-point 27 × 27 multiplication mode
— Fixed-point 18 × 18 multiplier adder mode
— Fixed-point 18 × 18 multiplier adder summed with 36-bit input mode
Updated soft CDR mode specifications in High-Speed I/O Specifications for Stratix 10 Devices table.
Added POR specifications.
Updated Tdo maximum specification in AS Timing Parameters for Stratix 10 Devices table.
Updated notes in Avalon-ST Configuration Timing Diagram.
Added description in NAND ONFI 1.0 Mode 0-5 Timing Requirements for Stratix 10 Devices table.
Updated tSU, tH, and td specifications in SD/MMC Timing Parameters for Stratix 10 Devices table.
Updated table title from "Initialization Clock Source Option and the Maximum Frequency for Stratix 10 Devices" to
"Initialization Time for Stratix 10 Devices".
Updated description in Configuration Bit Stream Sizes for Stratix 10 Devices to mention that the actual sizes may be equal
or smaller than the bit stream sizes in this table.
Updated description in Minimum Configuration Time Estimation section.
Removed AS ×1 specifications in Minimum Configuration Time Estimation for Stratix 10 Devices (AS, NAND, and SD/MMC)
table.
Added Glossary.
Removed PowerPlay text from tool name.
Made the following changes:
• Added the "Transceiver Power Supply Operating Conditions for Stratix 10 GX/SX E-Tile Devices" table.
• Added the "E-Tile Transceiver Performance Specifications" section.
• Added the "Transceiver Performance forStratix 10 E-Tile Devices" section.
• Added the "Transceiver Reference Clock Specifications" section.
continued...
Intel® Stratix 10 Device Datasheet
99
Stratix® 10 Device Datasheet
Date
Version
Changes
•
•
•
•
December 2016
2016.12.09
Made the following changes:
• Changed the max tLTR value and unit of measure in the "L-Tile Receiver Specifications" table.
• Made the following changes to the "Transceiver Clocks Specifications for Stratix 10 GX/SX L-Tile Devices" table:
— Changed the value of the reconfig_clk signal
•
•
•
•
October 2016
Intel® Stratix 10 Device Datasheet
100
2016.10.31
Added the "Transmitter Specifications for Stratix 10 E-Tile Devices" section.
Added the "Receiver Specifications for Stratix 10 E-Tile Devices" section.
Updated the "AS Timing Parameters for Stratix 10 Devices" table.
— Updated Tdcsfrs and Tdcslst.
— Added Text_delay and Text_skew.
— Removed Tsu and Th.
Updated AS Configuration Serial Input Timing Diagram.
— Added a new footnote to the GX channel
— Changed the minimum values for the GXT channel
Changed the max tLTR value and unit of measure in the "H-Tile Receiver Specifications" table.
Removed the QPI footnote from the "H-Tile Transmitter Specifications" table.
Changed the value of the reconfig_clk signal in the "Transceiver Clocks Specifications for Stratix 10 GX/SX H-Tile
Devices" table.
Changed the minimum value of fINPFD in the "Fractional PLL Specifications for Stratix 10 Devices" table.
Initial release.