JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 22, NO. 6, DECEMBER 2013 1347 Wafer-Level Vacuum Sealing by Coining of Wire Bonded Gold Bumps Mikael Antelius, Andreas C. Fischer, Niclas Roxhed, Member, IEEE, Göran Stemme, Fellow, IEEE, and Frank Niklaus, Member, IEEE Abstract—This paper reports on the investigation of a novel room-temperature vacuum sealing method based on compressing wire bonded gold bumps which are placed to partially overlap the access ports into the cavity. The bump compression, which is done under vacuum, causes a material flow into the access ports, thereby hermetically sealing a vacuum inside the cavities. The sealed cavity pressure was measured by residual gas analysis to 8×10−4 mbar two weeks after sealing. The residual gas content was found to be mainly argon, which indicates the source as outgassing inside the cavity and no measurable external leak. The seals are found to be mechanically robust and easily implemented by the use of standard commercial tools and processes. [2013-0003] Index Terms—Vacuum, packaging, MEMS, wire bonding, sealing, hermetic. I. Introduction V Fig. 1. Principle drawing of the sealing process. (a) First, a gold bump is wire bonded partially overlapping the access port of a cavity. (b) Second, the bump is compressed inside a vacuum chamber, causing plastic deformation and a flow of the bump material into the access port, thereby sealing the cavity. Manuscript received January 3, 2013; revised March 8, 2013; accepted March 23, 2013. Date of publication June 25, 2013; date of current version November 25, 2013. This work was supported by the European Research Council through the advanced grant project xMEMs (267528). Subject Editor N. de Rooij. The authors are with the Department of Micro and Nanosystems, KTH Royal Institute of Technology, 100 44, Stockholm Sweden (e-mail: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JMEMS.2013.2262594 Hermetic sealing at room-temperature is challenging since most bonding methods require elevated temperatures. Earlier reported room-temperature sealing methods include plasma activated direct bonding [5] and, in a sense, sealing structures heated locally on the wafer [6]. However, these methods are not straightforward and either impose restrictions on the choice of materials due to surface chemistry or add significant process complexity. Recently, plastic deformation of two types of gold structures has been used for room-temperature packaging applications [1], [7]–[9]. First, cold welding by deformation of electroplated gold sealing rings was used for both cavity formation and sealing of liquids [7] or vacuum [8]. Later, wire bonded ball bumps were used for liquids sealing by wire bonding gold stud bumps directly on the access ports of liquidfilled microcavities [9]. Low-temperature deformation of gold is extensively used in a process called coining, where wire bonded gold bumps are plastically deformed in order to both make the top surface flat and to achieve a predetermined bump height. This process was originally introduced in order to increase the electrical and mechanical reliability of stud bumps used in flip chip packaging [10]. Recently it has also been used for 3-dimensional micro structuring, where the bumps were imprinted with a structured mold [11]. In this paper we report on a novel wafer-level roomtemperature vacuum sealing process consisting of two steps. ACUUM packaging [1], [2], the process of enclosing a device under vacuum, is crucial for the performance of a wide range of MEMS devices. For example, vacuum packaging enables better thermal insulation of microbolometers in infrared imaging sensors, absolute pressure sensors with stable reference pressures and reduced gas damping effects in inertial MEMS sensors. Ensuring a high vacuum environment for a packaged device over its entire lifetime requires both a low residual gas pressure in the cavity directly after sealing as well as a small flux of gasses into the package during its lifetime. This flux has three sources, leaks through cracks and voids, internal outgassing and permeation through the sealing materials. Sealing a high vacuum at low temperature is difficult due to the often inherently high pressures and temperatures of sealing processes, e.g. the deposition pressure and temperature of a CVD sealing or the outgassing from anodic or glass-frit bonding processes [3], [4]. Furthermore, vacuum sealing at a low temperature, down to room-temperature, is beneficial in order to avoid thermal expansion mismatch, thermally induced performance degradation and thermally induced outgassing. c 2013 IEEE 1057-7157 1348 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 22, NO. 6, DECEMBER 2013 Fig. 2. Fabrication scheme. (a) Recess formation by KOH etching. (b) Access port formation by DRIE. (c) Wafer fusion bonding and gold sputter deposition (d) 1. Using a wire bonder, an electrical discharge forms a ball at the end of a gold wire. 2. Ball bonding with an offset to the access ports. (e) At a chamber pressure of 10−5 mbar a bond force of 3.2 kN is applied, forcing the bumps into the access ports and thereby hermetically sealing the vacuum cavities. (f) Silicon diaphragm deflection induced by the external atmospheric pressure. First, wire bonded gold bumps are placed in such a way that they partially overlap the access port to a cavity (Fig. 1a). Second, a wafer-level coining process is performed in a vacuum chamber by applying a force that causes the bump to plastically deform, flatten, and flow into the access ports, thereby clogging the ports as shown in Fig. 1b. This sealing process is performed using the combination of a high-speed wire bonder and a commercial wafer bonder, ensuring a costefficient implementation with standard tools. The placement of the bumps using a high-speed wire bonder can be a cost-efficient solution even for a large number of cavities since wire bonding is an extremely mature back-end technology with very high throughput [12]. For very high volume applications the cost of wire bonding processes has been reported to be on the order of 14 USD / 100,000 bumps [13]. The only prerequisites for using this method are (1) sufficiently small ports into the cavity, (2) a sufficient stiffness of the package material, and (3) a wire-bondable surface. II. Fabrication For evaluating the sealing method, test cavities were fabricated according to the process scheme shown in Fig. 2. The evaluation structures consist of two bonded silicon wafers, where one has etched cavities and ports. The cavity wafer was a 545μm thick double-side polished 100 mm diameter silicon substrate with a 2.2 μm thick silicon dioxide layer on both sides, created by thermal wet oxidization at 1100°C. The patterned silicon dioxide acted as a hard mask for a wet etching step in KOH, which formed the cavities in the cavity wafer, shown in Fig. 2a. The etch depth was 440 μm, which resulted in a cavity diaphragm thickness of approximately 105 μm and a final cavity volume of 50 μl. The silicon dioxide layer was subsequently removed on the top side by etching in BHF. A standard lithography on the top side of the substrate defined the circular openings for the access ports, as indi- cated in Fig. 2b. These ports were intentionally placed above the tapered side-wall of the (111) crystal plane exposed by the KOH etch. This placement had three purposes: (1) this prevented the fragile 12 × 12 mm2 pressure sensitive silicon diaphragms from being damaged by the pressure applied by the wire bonding tool in a later step; (2) this ensures minimal mechanical deformation of the sealed ports by deflection of the pressure sensitive diaphragm; and (3) the ports are connected to the cavity with a single etching step. However, without the thin pressure sensitive diaphragm, made here for evaluation purposes, this placement restriction could be avoided. The access ports were etched into the cavities by a deep reactive ion etch (DRIE) process. In preparation for the following wafer fusion bonding, the bottom protective silicon dioxide layer on the cavity wafer was removed in 5% HF. The two wafers were thereafter cleaned and surface activated for bonding by a 10 minute hydroxylation in a boiling piranha etch, followed by a rinse in deionized water and spin drying. The fusion bonding was initiated by joining of the wafers in 1 mbar of N2 , with a tool force of 1 kN at 300°C. The wafer bond was finally strengthened by a 3 hour N2 -anneal at 900°C. A 100 nm TiW + 500 nm Au sputter deposition on the frontside provided a bondable layer for the subsequent gold bump sealing process. This metallization also covers the top of the side-walls of the access ports, as shown in Fig. 2c. The vacuum sealing was performed in two steps. First, gold bumps were wire bonded off-center on the 30 μm diameter cavity access ports, as illustrated in Fig. 2d. The gold bumps were bonded at a rate of 14 bumps/s using a fully automated wire bonder (ESEC 3100+, ESEC Ltd, Switzerland). The bumping process was optimized to obtain high and narrow bump shapes. The wire bonding tool is of a thermo-compression type, where temperature, force and ultrasonics are applied to bond the gold bumps to the gold layer on the wafer surface. Increased ultrasonic power and ANTELIUS et al.: WAFER-LEVEL VACUUM SEALING BY COINING OF WIRE BONDED GOLD BUMPS 1349 Fig. 3. SEM micrographs of wire bonded gold bumps. (a) A gold bump prior to vacuum sealing. The bump has a diameter of approximately 90 μm and a height of 50 μm. It is placed with an offset of 35 μm from the center of the 30 μm diameter port. (b) A coined gold bump after the vacuum sealing. A force of approximately 9 N per bump was used to plastically deform the bumps and seal the access ports. The bump is flattened and its height is reduced to 15 μm. (c) Cross sectional view of a sealed access port. The cross section was made by grinding and polishing. The gold has been pressed approximately 90 μm into the access port. duration was used in order to optimize the bond process for a low substrate temperature. Typical wire-bonding chuck temperatures of 100–160°C could thereby be decreased to 40°C in order to maintain a low thermal budget throughout the whole bump-sealing process. The cavity wafer was finally transferred to a substrate bonder (Süss CB8, Süss MicroTec AG, Germany) where the cavities were sealed at wafer-level by compressing the bumps in a vacuum environment. A 525 μm thick oxidized silicon wafer was placed on top of the cavity wafer in order to ensure a flat and evenly distributed compression of the bumps over the entire wafer area, as indicated in Fig. 2e. The wafer stack was placed in the bond chamber and after pumping down for 60 hours, to a vacuum level of 10−5 mbar, a force of 3.2 kN was applied on the wafer stack by the bond tool. The wafer contained 350 bumps which means that the corresponding force per bump was approximately 9 N. The entire compression process was performed with a bond chuck temperature of 30°C. The plastic deformation of the bumps into the access ports resulted in hermetic sealing of the cavities, as illustrated in Fig. 2e and f. After removing the wafers from the vacuum chamber, the pressure difference between the cavity volume and the atmosphere caused a deflection of the diaphragm as indicated in Fig. 2f. The completed devices were diced without extra protection in a Disco DAD 320 dicing saw. III. Results and Discussion Fig. 3a shows an SEM image of a gold bump that has been wire bonded with an offset of 35 μm with respect to the center of the access port. The effect of the plastic deformation is clearly visible when comparing the SEM images of the gold bump before, Fig. 3a, and after compression, Fig. 3b. Gold bumps that initially had a diameter of 90 μm and a height of 50 μm were flattened to a diameter of 160 μm and a height of 15 μm by the coining process. The access port has been completely covered by the coined bump and the top surface of the bump is flat. An SEM image of a polished cross section of a sealed access port is shown in Fig. 3c. The image shows that the compression caused the gold from the bump to completely fill and seal the access port to a depth of 90 μm. Fig. 4. Comparison of different gold bump offset positions before and after coining. The three rows show the same gold bump at an angle, from above and from above after coining, respectively. The different columns correspond to different offsets, in μm. The port position is indicated in white. The used wire bonding tool has a pattern recognition system, which is able to detect the access port and to place the stud bump with an accuracy of 2.5 μm (3σ) on the wafer surface. A comparison of placing gold bumps with offsets between 35 and 50 μm with respect to the port center is shown in Fig. 4. This figure shows that an offset of 35 μm was sufficient for both maintaining an open port before the compression and being able to seal the port completely by the compression. Therefore, an offset of 35 μm was used for the bump-sealing process. A. Residual Gas Analysis Two bump-sealed cavity chips were used for a residual gas analysis (performed by SAES Getters S.p.A, Lainate, Italy). This is a test where the sealed cavity is mechanically opened in a vacuum chamber connected to a mass spectrometer. The mass spectrometer measures the amount and composition of the gas that escapes from the cavity. The measured results for the two cavities, one with 80 ports and one with 2 ports, is reported in Table I. The achieved vacuum level is lower for the sample with more ports. This difference correlates to the difference in evacuation rate caused by the different amount of ports. The 1350 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 22, NO. 6, DECEMBER 2013 TABLE I Measured Residual Gas Pressures in Two Sealed Cavities with Different Amounts of Access Ports Gas H2 O Ar N2 H2 CH4 O2 CO2 He Ne C2 H6 C 3 H8 CO Kr Total Pressure, 2 ports [mbar] % 3.33 × 10−3 56.96a 1.00 × 10−3 17.17 8.52 × 10−4 14.56 5.25 × 10−4 8.97 8.75 × 10−5 1.50 2.77 × 10−5 0.47 2.18 × 10−5 0.37 0 0 0 0 0 0 0 0 0 0 0 0 5.85 × 10−3 100.00 Pressure, 80 [mbar] 0 6.15 × 10−4 0 0 0 0 2.04 × 10−4 1.89 × 10−7 0 0 0 0 0 8.19 × 10−4 ports % 0 75.11 0 0 0 0 24.86 0.02 0 0 0 0 0 100.00 [a] The test was performed at room-temperature, and so the content of water could be underestimated. evacuation rate is addressed further in section III-C. The measured cavity pressure, 8.19×10−4 mbar, is sufficient even for very demanding applications such as microbolometers, assuming a low leak rate [14]. The achieved cavity pressure is well below reported values for cavity sealing using CVD depositions [15], aluminum sputtering [16] or glass frit reflow [4], [17], which achieve pressures between 1 and 10 mbar. A sealing method using epitaxial silicon deposition has been reported to achieve a comparable pressure of 8×10−3 mbar, although at a temperature of 950°C [18]. Implementing a getter material would further reduce the cavity pressure at the cost of an anneal at >300°C for getter activation [14], [19]. The gas analysis revealed a high concentration of argon. Although argon is present in the ambient air, the main source of argon in the sealed cavities is considered to be from the sputter deposited gold, since argon used in thin-film sputter deposition is known to be incorporated into the sputtered thinfilms during deposition processes, causing argon outgassing in microcavities [20], [21]. If argon had been leaking into the bump-sealed cavity from the atmosphere, there would also have been other species from the atmosphere present in the cavities, mainly nitrogen and oxygen. However, in the measured samples, no traces of nitrogen or oxygen could be measured, indicating a full hermeticity and no measurable external leak. Internal outgassing on the other hand is inherently finite and decreasing over time. The presumably argon outgassing gold is located near the sealed openings of the ports, and has no function here. This means that the argon contribution could be reduced by depositing the gold by evaporation instead, reducing the incorporation of argon. The other internal cavity surfaces are either pristine or previously annealed at 900°C, thus there should be no argon outgassing from these surfaces. However, the measured pressures of argon does not correlate with the larger surface area of gold in the device with 80 ports, which has a lower argon pressure. But several other factors could also be affecting the argon level: the two cavities had different positions on the wafer, which could affect the pumping rate; a part of the measured argon could come from the gold sputtered on the outside of the devices, which is released when the diaphragm is broken during testing; the chip to chip pressure variations are unknown since the reported data is only from two packages. The relatively high water pressure in the cavity with two ports is typical of an incomplete evacuation, since water is the most problematic species to desorb from unbaked vacuum chambers [22]. As water is adsorbed on the chamber walls, it is dissociated, which in turn can lead to desorption of H2 CH4 and CO2 into the vacuum chamber [23], [24]. It should be noted that in [23], [24] the vacuum chamber walls were studied, which are made of different materials than the microcavities in this work. B. Leak Rate The leak rate of a package is important for estimating the lifespan of vacuum packaged devices. A short term “worst case” estimate of the leak rate is to assume that at the time of the residual gas analysis, two weeks after the vacuum sealing, the cavity had leaked to the measured vacuum level, essentially neglecting gas contributions from an incomplete pump-down of the cavity during sealing. This conservative assumption yields a leak rate of 2.9 × 10−14 mbarL/s for the cavities in this work. This leak rate would indicate an extrapolated cavity pressure of 2 × 10−2 mbar after one year. This is considered a worst case, since it is not known what cavity pressure was enclosed during the bump-sealing, and hence this gives a maximal leak rate. Although the leak rate level reported here is not as impressive as, e.g., the 8 × 10−17 mbarL/s recently reported by Santagata et al. [15], the cavity pressure increase in mbar after one year reported in this work is 500 times lower than [15], mainly due to the smaller cavity volume in [15]. For a longer term leak rate evaluation, the deflections of the diaphragms suspended over the vacuum cavities were monitored over 30 days by white light interferometry. These measurements yielded the deflection at the center of the diaphragm, which is directly proportional to the ambient pressure over the diaphragm [25]. The varying ambient pressure was compensated for using pressure data from a nearby weather station. The reduction in diaphragm deflection over time can in turn be used to evaluate the leak rate La using equation 1 [26], [27], V W t1 (1) La = ln Wt2 t2 − t1 where W is the surface deformation, V the cavity volume and t2 − t1 is the time passed between the two deformation measurements. The measured deflection is presented in Fig.5. This figure shows that no leak can be detected, and from the noise level of the measurement, a limit of detection can be estimated. The variation of the measured deflection data is determined to be about ±0.25 μm. This variation was higher than the limit of the measurement system, which had been measured to less than ±0.14 μm (2σ, including the pressure compensation) for a 24 h long continuous measurement of the diaphragm deflections. This limit was however achieved ANTELIUS et al.: WAFER-LEVEL VACUUM SEALING BY COINING OF WIRE BONDED GOLD BUMPS Fig. 5. Measurement made with an optical profilometer of the diaphragm deflection over time in order to evaluate the sealing. The data has been normalized and compensated for varying ambient pressure. 11 out of 15 cavities are followed over a month, the remaining four were removed from the experiment and used in other tests. 1351 Fig. 6. Calculated cavity pressures during evacuation through a single square access port of five different dimensions. Port dimensions are in μm2 . without unloading and loading the wafer onto the stage of the white light interferometer, which may be the source of the additional uncertainty. The variation in the deflection data yields a leak rate better than 9×10−11 mbarL/s. This estimated leak rate is lower than the typical range of the helium fine leak test [26]. However, it is 3000 times higher than the leak rate value from the residual gas analysis data, meaning that this method would only detect sharp and unexpected pressure increases over much longer time intervals. No such events have been observed here. For comparison, the leak rate measured by residual gas analysis after 15 days corresponds to a deflection change of 2 nm after one year. as gas sinks, trapping gas species with a long residence time, when only the wafer chucks are heated in the tool. A way to increase the evacuation rate would be to increase the diameter of the access ports. The maximal port diameter is limited by the available volume of gold in the bump, and the applied pressure for deformation. The gold bump volume, or the size of the gold ball, is limited by the wire diameter, which in this work was fixed by the wire bonding tool configuration to 25 μm. The preferred way to increase the wafer throughput for the sealing step would be to evacuate and seal more wafers at the same time. This is possible, since the process step performed in the wafer bonder can be run as a batch process. Several wafers could be stacked on top of each other without any anticipated adverse effects on pumping and sealing, thereby drastically increasing the throughput. C. Evacuation Rate D. Stress Testing The evacuation rate of the cavities is important for the fabrication throughput. The rate of evacuation can be modeled by treating the evacuation port as a resistor draining a fluidic capacitor, the cavity [6], [28]. Using this model the cavity pressure decrease during evacuation through one rectangular port, of different sizes, was calculated and plotted in Fig. 6. This figure shows that the model predicts sufficient pumping of the cavity already with a single port. However, this simple model omits the slow surface desorption of certain species, i.e. water, meaning that the pumping can take longer time than predicted. This slow surface desorption, or “surface stickiness”, of water is most likely the dominating reason for the slow evacuation of the cavity with only two ports. This analysis corresponds to the higher pressure measured by residual gas analysis of the chip with only two ports, where the dominating pressure contribution was from H2 O. The situation would have been different if the wafers had been heated in the vacuum chamber before the sealing process. For example, the residence time for water on a metal surface is reduced from 105 to 10−5 s when the metal surface is heated from 22 to 450°C [22]. Additionally, the cold chamber walls would act Two vacuum sealed packages were temperature cycled 500 times between -10 and 70°C. The cycling was done using a single-chamber setup at a rate of 1.5 cycles/h with a 5 minutes wait at the endpoint temperatures, all in accordance to JEDEC test method A104D [29]. The hermeticity of the cycled packages were evaluated using the diaphragm deflection described in section III-B. This evaluation showed no change in diaphragm deflection and no leaks, with a cavity pressure limit of detection of 3 mbar. Two vacuum sealed cavities were subjected to additional overpressures of compressed air to test the mechanical robustness of the seals. The cavities were put in a chamber with overpressures of 0.5, 1.5, 3 and 5 bar, each for a duration of 15–20 h. The packages were evaluated using the diaphragm deflection method as above and showed no measurable leaks. IV. Conclusion We have described and demonstrated a novel roomtemperature vacuum sealing process using coining and deformation of wire bonded gold bumps into access ports of 1352 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 22, NO. 6, DECEMBER 2013 cavities. The measured cavity pressure was 8×10−4 mbar, and the content of the residual gas is dominated by argon and carbon dioxide after 60 hours of pumping, indicating that the source is internal outgassing. The corresponding leak rate for the evaluated cavity is less than 2.9×10−14 mbarL/s, presumably with no measurable external leak contribution. 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Niklaus, “Small footprint wafer-level vacuum packaging using compressible gold sealing rings,” J. Micromech. Microeng., vol. 21, no. 8, p. 085011+, Aug. 2011. B. H. Stark and K. Najafi, “A low-temperature thin-film electroplated metal vacuum package,” J. Microelectromech. Syst., vol. 13, no. 2, pp. 147–157, Apr. 2004. Temperature Cycling, JEDEC Std. JESD22-A104D, Mar. 2009. Mikael Antelius received the M.Sc. degree in chemical engineering from Uppsala University, Uppsala, Sweden, in 2007. After a one year stay in the industry, he joined the Department of Micro and Nanosystems, School of Electrical Engineering, KTH Royal Institute of Technology, Stockholm, Sweden, where he will defend his Ph.D. thesis in April 2013. His current research interests include silicon photonics and wafer-level vacuum and liquid packaging, particularly regarding gas sensors. Andreas C. Fischer was born in Baden-Baden, Germany. He received the Diploma degree in microsystems engineering from the University of Freiburg, Freiburg, Germany, and the Ph.D. degree in microsystem technology from the KTH Royal Institute of Technology, Stockholm, Sweden, in 2008 and 2013, respectively. He is currently a Post-Doctoral Researcher at the Department of Micro and Nanosystems, School of Electrical Engineering, KTH Royal Institute of Technology. His current research interests include the development of novel integration and fabrication techniques for 3-D microand nanodevices, heterogeneous integration of MEMS, and IC technology as well as advanced wire bonding technology. Niclas Roxhed (M’09) was born in Stockholm, Sweden, in 1978. He received the M.Sc. degree in electrical engineering and the Ph.D. degree in microsystem technology from KTH Royal Institute of Technology, Stockholm, Sweden, in 2003 and 2007, respectively. He is currently an Assistant Professor and a Team Leader of Medical MEMS with the Department of Micro and Nanosystems, School of Electrical Engineering, KTH Royal Institute of Technology. His current research interests include sensors for medical diagnostics and medical-aid microsystems. He is also involved in highprecision etching using DRIE for RF-MEMS switches and 3-D integration of MEMS on ICs for infrared imagers. He has authored or coauthored more than 50 scientific papers. ANTELIUS et al.: WAFER-LEVEL VACUUM SEALING BY COINING OF WIRE BONDED GOLD BUMPS Göran Stemme (F’06) received the M.Sc. degree in electrical engineering and the Ph.D. degree in solid-state electronics from Chalmers University of Technology, Gothenburg, Sweden, in 1981 and 1987, respectively. In 1981, he joined the Department of Solid State Electronics, Chalmers University of Technology, where he became an Associate Professor (docent) heading the silicon sensor research group in 1990. Since 1991, he has been a Professor at KTH Royal Institute of Technology, Stockholm, Sweden, where he is the Head of the Department of Micro and Nanosystems, School of Electrical Engineering. His research is devoted to microsystem technology based on micromachining of silicon. He has published more than 300 research journal and conference papers and has more than 22 patent proposals or granted patents. Dr. Stemme is a member of the Royal Swedish Academy of Sciences (KVA). 1353 Frank Niklaus (M’06) received the M.Sc. degree in mechanical engineering from the Technical University of Munich, Munich, Germany, in 1998, and the Ph.D. degree in MEMS from KTH Royal Institute of Technology, Stockholm, Sweden, in 2002. He was a Consultant to the industry and a Visiting Scholar at Rensselaer Polytechnic Institute, Troy, NY, USA, where he was with 3-D-IC technologies. He is currently an Associate Professor at the Department of Micro and Nanosystems, School of Electrical Engineering, KTH Royal Institute of Technology, where he is the Team Leader for all micro- and nanosystem integration activities.
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