what is the remainder about?
MANAGING COMPLEXITY IN THE BACKEND!
• conventional (idealistic) flows
– environment
– silicon compilers
• floorplan design and optimization
– what is a floorplan?
– floorplanning
– partitioning
• placement
– optimization and legalization
• wiring
– global wiring
– detailed wiring
• modern "flows"
– restore iteration free design
first PHILIPS transistor
a digital filter (3000 transistors)
digital audio broadcasting chip
(4000000 transistors)
programmed logic device(9000000 transistors)
chandu's chip
moore's law
[Gordon Moore, 1964]
proportionality constant,
"moore exponent m",
0.2 for processors, and
0.4 for memory
dN
∝N
dt
static memory
intel microprocessors
number of transistors
the growth rate
of chip complexity
will be proportional
to the achieved
complexity to date
1011
1010
1 G
109
256 M
108
64 M
107
4 M
106
1 M
256 K
105
104
64 K
16 K
4 K
1 K
103
70
80
90
00
→
year
N=numerical complexity of the module (e.g. the chip)
moore's law
intel processor
80286
80386
80486
pentium
pentium pro
itanium
entry date
feb.
oct.
apr.
mar.
nov.
june
1982
1985
1989
1993
1995
2000
nr. transistors feature size
134000
275000
1200000
3100000
5500000
>1000000
1.5
1.5
1.0
0.8
0.6
0.25
micron
micron
micron
micron
micron
micron
chip complexity grows proportional to chip complexity!
∂N
∝N
∂T
from an empirical rule it became a goal setter
moore's exponential growth law
feature size
feature size
feature size
feature size
feature size
feature size
corollaries to moore's law
the reduction rate
of device sizes
will be proportional
to the achieved
device size
[Status2000,ICE, 2000]
[ µ m]
101
s ou
rc e
100
mi
/d
r
proportionality constants
are pretty close in value,10-1
and will be called
the "process exponent p",
ai n
ga
te
10-2
dL
∝ −L
dt
nim
um
jun
fe
a
cti
o
ox
id
tu
re
siz
e
nd
ep
th
et
h ic
kn
es
s
≈ 3 atom
layers
10-3
1960
1970
1980
1990
Year
2000
2010
today
• the chip industry
– the complexity growth integrated circuits
– miniaturization
• design styles
– fabrication perspective
– designer's perspective
• design flows
– fully automatic iteration free chip design
– the back-end: layout synthesis
• what is a floorplan?
– data structures for capturing relative positions
– floorplans in hierarchical back-end tools
– graphs as floorplans
classifications: fabrication perspective
off-the-shelf
programmable
semicustom (master image)
full custom
classifications: designer's perspective
component
field programmable
off-the-shelf
programmable
mask programmable
semicustom (master image)
full custom
sea-of-gates
gate array
gate array
sea-of-gates (channelless array)
PHILIPS microprocessor
macrocell assembly
polycell versus gate array
• rows, longitudinally aligned
• variable width channels
• bonding pads as required
• rows of identical cells
• fixed width channels
• fixed footprint
polycell layout style
power pc processor
where are we?
• the chip industry
– the complexity growth integrated circuits
– miniaturization
• design styles
– fabrication perspective
– designer's perspective
• conventional design flows
– fully automatic iteration free chip design
– the back-end: layout synthesis
• what is a floorplan?
– data structures for capturing relative positions
– floorplans in hierarchical back-end tools
– graphs as floorplans
classifications
component
field programmable
off-the-shelf
programmable
mask programmable
semicustom (master image)
sea-of-gates
gate array
polycell (standard cell)
compiled
pluricell
macrocell
full custom
hand-crafted
fixed
mixed
soft
choosing a style
cumulative
cost
semicustom
full custom
field
programmable
number of
products
produced
choosing a style
cumulative
cost
semicustom
full custom
field
programmable
number of
products
produced
conventional iteration-free synthesis
conceptual
design
gate
and net
list
foot print
behavioral
synthesis
data
preparation
weighted
no global
iteration!
incidence
wire length and area
structure
minimization under
if fully automatic:
technology constraints
silicon compilation
logic
synthesis
library
technology
layout
synthesis
layout design
c
o
m
m
o
n
functional
specification
silicon compilation
d
a
t
a
b
a
s
e
technology
file (design rules)
layout design
layout
layout design
c
o
m
m
o
n
functional
specification
silicon compilation
d
a
t
a
b
a
s
e
technology
file (design rules)
layout design
layout
the output:
mask
=
2-block partition of the plane
("opaque", "transparent")
("write" , "no-write")
specification of "masks"
layout
=
=
layout
files of rectangles with a color
layout design
c
o
m
m
o
n
functional
specification
silicon compilation
d
a
t
a
b
a
s
e
technology
file (design rules)
layout design
layout
design rules
3λ
2λ
3λ
8λ
2λ
2λ
3λ
2λ
2λ
2λ
2λ
1λ
2λ
2λ
1λ
2λ
2λ
2λ
2λ
2λ
technology constraints (design rules)
• technology rules are translated into design rules
• the design rule set is the interface between designer and
foundry
• rules are simplified and often on the safe side
• certain rules are always assumed!
• for synthesis we distinguish
– numeric rules
• small total area
• reduction to "pitches"
R1: wire width per layer
R2: wire separation per layer
R3: contact rules
• structural rules
layout design
c
o
m
m
o
n
d
a
t
a
b
a
s
e
functional
specification
silicon compilation
course
5P310
technology
file (design rules)
layout design
layout
incidence structures (net lists)
modules:
M supermodule of m1,m2 and m3
m1,m2, and m3 submodules of M
p2
p4
m1
p7
p12
p6
N1
N2
p3
N5
p11
also:
a bipartite graph,
"the potential graph"
(M ∪N ,P )
m3
p13 p3
p10
m2
M
p1
N3
pins p1 ... p13
relating nets
with modules
N4
p9
local nets: N1, N3
global nets: N2, N4, N5
functional hierarchy
chip
compounds
cells
rectangle constraint
• top down design
– initially very little geometrical knowledge is available
– stepwise refinement
• postpone decisions to get as much information as possible
• each decision adds knowledge to the next step or the
other part
– decompose the whole design task into subtasks
• apply as much as possible the same approach to each part
this produces true hierarchy:
hierarchy = a set of hierarchies and leaf cells
• special problems are treated by special dedicated routines
• flexibility
– built-in capability to update the available information
• fast optimization algorithms
• easily adaptable configurations
• self fulfilling shape requirement
deviations contained in inset cells
layout design
c
o
m
m
o
n
functional
specification
silicon compilation
d
a
t
a
b
a
s
e
technology
file (design rules)
layout design
layout