1. Using a Gray code for state encoding/assignment, write the Boolean equations for the
next-state
state and output logic for the FSM below, assuming it is implemente
implemented
d using D
flip-flops.
2. Below is a state diagram of a Mealy FSM with one input, x, and one output, z.
z Using
a one-hot
hot code state assignment, write the Boolean eq
equations
uations for the next state logic
for the flip-flops
flops corresponding to states B and C (i.e., equations for the D inputs to
those flip-flops).. Also provide the equation for the output logic.
3. Write out the next-state
state and output equations for the circuit below and construct the
corresponding state graph/diagram.
4. Now, complete the timing waveform below, assuming Q1 and Q2 are initially zero.
5. Below is a sequential circuit. The flip-flop
flop outputs are numbered left to right, S0-S2.
S0
Note that the reset signal initializes the flip-flops to a one-hot code (100).
a. Construct the portion of the state transition table that corresponds to current states
that are not valid one-hot
hot codes (e.g., 110).
b. If the circuit were to power
power-up
up in one of these states (except all zeroes) with A=1,
A=1
what is the maximum number of clock cycles required to reach a 11-hot
hot code?
Explain.
c. What happens to the circuit state after subsequent clock cycles?
6. Assuming the following timing parameters and constraints, what is the maximum
clock frequency for the above circuit in the absence of clock skew? How much clock
skew can be tolerated without
out experiencing a hold time violation?
tpcq - max FF clock to Q delay
tccq - min FF clock to Q delay
tsetup - FF setup requirement
thold - FF hold requirement
tpd - max prop delay per logic gate
tcd min prop delay per logic gate
15 ns
5 ns
10 ns
5 ns
20 ns
10 ns