196 / CLEO'S7 / WEDNESDAY MORNING
SOOA
AlAs
p-GaAs
+=
=>5oA
MgFRnSe
AlGaAs
1050A -I
DBR(x6)
-
GaAs
p-AlAs
Etch Trench
f
'Oxide
W2
T
E
I-
OxidelGaAs
DBR(xl1)
Ai2
-w
n-GaAs
0
CWA5 Fig. 1 Schematic illustration of the
X/2-cavity
VCSEL
with
AlxOy/GaAslower DBRs. Strain resulting from
oxidation is reduced by use of less than quarterwave Al,Oy layers.
Ith = 53pA
q=15%
0
a
/
Oxide/GaAs DBRs
(11 pairs)
0
200
300
400
500
600
700
Anneal Temperature ("C)
GaAs Substrate
oxide-confined
I00
100
200
300
Current (PA)
CWAS Fig. 2 Light versus current curve for a
2-km diameter Xi2-cavity device. Lasing threshold is 53 p A and the differentialslope efficiencyis
15%.
the oxideiGaAs DBRs of the low index spacer,
half-wave cavity VCSEL is shown in Fig. 1.
The low index X/2 spacer devices demonstrate lasing characteristics that indicate that
the oxide/GaAs DBRs decrease diffraction loss
for small (<2 p m ) devices compared with very
similar AlAs/GaAs-DBR-based VCSELs.'
Light output versus current for a 2-pm diameter device is plotted in Fig. 2 and shows 53 pA
(1687 A/cm2).A slightlyhigher threshold of 68
pA (8658A/cm2) is achieved for a 1-pm diameter active region. Besides diffraction loss of
the optical mode, spectral data indicates that
these devices suffer from effects of significant
carrier leakage over the p-type heterobarrier
for current densities over 1000A/cm2,which
significantly increases the threshold current
for the smallest devices.
In an attempt to control the carrier injection over the p-type heterobarrier we have designed a second VCSEL also using the 1l-pair
oxide/GaAs DBR, but with a high index GaAs
spacer layer and tunnel injection barrier^,^ as
shown in Fig. 3. Spectral data for a single QW
light-emitting diode indicates that the tunnel
injection is effective in reducing carrier leakage
over the heterobarrier. To our knowledge, this
is the first demonstration of tunnel injection in
a VCSEL. As Fig. 3 shows, the adjacent p-type
AlGaAs layer is oxidized to achieve lateral in-
Schematic cross section of a
tunnel injection VCSEL with use of oxide (700
.&)/GAS (1050 8)DBRs.
CWAS Fig. 3
dex confinement. To further control carrier
leak$ge over the p-type heterobarrier, tw?
60-A Ino~,oGao
soAs QWs separated by a 50-A
GaAs barrier are placed next to the AlGaAs
layer for maximum index confinement. Although the cavities are somewhat detuned to a
wavelength longer than optimum for the gain
region, the tunnel injection VCSELs yield lasingthresholds of -190 pAand -160 pAfor 4
p m and 1 p m diameter VCSELs, respectively.
These initial results demonstrate the effectiveness of tunnel injection in a VCSEL, and the
first high index h/2 cavity spacer layer.
1. T.-H. Oh, D. L. Huffaker, D. G. Deppe,
Appl. Phys. Lett. 69, (Nov. 18, 1996).
2. M. H. MacDougal, H. Zhao, P. D. Dapkus, M. Ziari, W. H. Steier, Electron. Lett.
30,1147 (1994).
3. P. Bhattacharya, J. Singh, H. Yoon, X.
Zhang, A. Gutierrez-Aitken, Y. Lam, IEEE
J. Quant. Electron. 32, 1620.
CWA6
9:30 am
Indium tin oxide transparent electrodes
for vertical-cavity surfaceemitting
lasers fabricated with use of a single
lithography step
C. L. Chua, R. L. Thornton, D. W. Treat,
V. K. Yang, C. C. Dunnrowicz, Xerox Palo
Alto Research Center, 3333 Coyote Hill Road,
Palo Alto, California 94304; E-mail:
[email protected]
Indium tin oxide (ITO) films have gained
widespread use in many optoelectronic devices
because of their unique ability to simultaneously provide high electrical conductivity
and high optical transparency. Under appropriate thermal treatment, I T 0 can also be
made to form good ohmic contacts with GaAs
while retaining its high conductivity and transparency. This latter property has only recently
been exploited for use in vertical-cavity semiconductor lasers (VCSELs). In this presentation, we examine the use of I T 0 for greatly
simplifymg VCSEL fabrication.
In our device, a 2,000-A-thick top I T 0 electrode was first sputter-deposited on the
VCSEL wafer in an oxygen atmosphere that
was optimized to yield high film transparency
CWA6 Fig. 1 Specific contact resistance of
IT0 contacts o n p = 5 X 10'' GaAs as a function
of anneal temperature. After film anneal at
600 "C, the specific contact resistance dropped
abruptly by two orders of magnitude.
and conductivity. Figure 1 plots the specific
contact resistance of the I T 0 contacts on p =
5 X loL8GaAs as a function of anneal temperature. The abrupt drop in contact resistance at
600 "C was accompanied by a similar reduction in film resistivity from an as-deposited
value of 14 X lo-* 0,-cm to a value of 2.5 X
lop40,-cm after anneal. The optical transmission coefficient of the film, on the other hand,
increased monotonically with increasing anneal temperature, and reached a value of 93%
at the VCSEL emission wavelength of 801 nm
after film anneal at 600 "C.
The I T 0 fdm was patterned into 75 pm, 80
pm, and 100 p m squares, and annealed at
600 "C in a nitrogen ambient. The entire top
DBR was then wet etched down to the quantum well cladding layers by use of the annealed
I T 0 top electrode as mask. The resulting mesa
structures had exposed AlAs mirror sidewall
layers that were laterally oxidized in a wet oxidation furnace to define current apertures of
dimensions 18 pm, 24 pm, and 30 p m on a
side. A eutectic GelAu was then deposited for
the backside contact. It should be noted that
this device was fabricated in a single selfaligned lithography process, makmg the process a useful characterization tool for providing rapid feedback to VCSEL epitaxial material
growers. A cross-sectional schematic of the device is shown in Fig. 2.
Figure 3 displays the L-I and I-V characteristics of an 18-pm device under roomtemperature cw pumping. As expected for
large area devices, all three device sizes examined showed evidence of multi-transverse
mode operation.
In summary, we report top-emitting laterally oxldized vertical-cavity surface-emitting
lasers employing transparent indium tin oxide
electrodes. We show that I T 0 films, when
properly deposited and annealed, attain high
optical transparency and high electrical conductivity. Their ability to form good ohmic
contacts with GaAs makes them suitable for
use as a transparent electrode for top-emitting
VCSELs. Annealed I T 0 electrodes retain their
desirable optical and electrical properties even
after subjecting them to the elevated temperature and humid environment of the AL4s wet
oxidation process. These characteristics enable
the fabrication of simple broad area VCSELs in
a single photolithography step. The resulting
WEDNESDAY MORNING / CLE0'97 / 197
light output
S-ICH,
t
Giorgio Giaretta et al.
6
"Oxide Isolated VCSELs"
IVCSEL post1 Intercon- I Contact I Top
4 quantum wells+
n-metal contact
CWA6 Fig. 2 Cross section schematic of the
device. The partially oxidized AlAs layers in each
of the top DBR mirror pairs form a current channel at the center of the mesa. A transparent con-
ductive IT0 film is used for the top electrode, an
architecturethat enablesbroad area VCSELs to be
quickly fabricated in a single lithography step.
Two-mask process
Interconnect lithography
Au evaporation
Au lift-off
Isolation lithography
o.8
I
I
0.6
;
3
Typical VCSELstructure with the top DBR mirror removed to showthe oxidation layer.
Top View
Em
1.a
-g
CWA7 Fig. 1
Vertical Section
0.4
0.2
0.0
Current (mA)
CWA6 Fig. 3 L-I and I-V characteristicsof an
18-pm device under room temperature cw
pumping. The spectrum at I = 2 Ith is shown as
an inset.
fast turnaround time from semiconductor materials to devices provides a valuable tool for
evaluating and optimizing VCSEL epitaxial
structures.
CWA7
9:45 am
A novel simple oxide isolation process
to fabricate high performance VCSEL
arrays
G. Giaretta, W. Yuen, L. Aronson,* B.
Lemoff,* C. J. Chang-Hasnain, Box 38 Cory
Hall, U&vevsity ofCal;forn;a Berkeley,
Berkeley, California, 94720-1744; E-mail:
[email protected]
Vertical-cavitysurface-emittinglasers (VCSELs)
are ideal sources for two-dimensional array
applications as optical scanners, displays, computer interconnects, signal processing, and optical data storage. These applications require
uniform characteristics of the devices across
the array, ease of fabrication, and high yields.
Uniform independently addressable VCSEL
CWA7 Fig. 2 Very simple two-mask independentlyaddressableoxide isolated VCSEL array process.
arrays have been previously demonstrated
with use of proton implantation.' Recent advances in oxide-confined VCSELs show dramatic improvements over proton implanted
lasers in threshold currents and wall plug efficiency.* Thus oxide-confined VCSELs seem
ideal for array applications. However, the
oxide-confined VCSEL has a nonplanar structure that makes fabricating the electrical interconnects difficult. In this paper we introduce a
novel and extremely simple two-mask process
that uses a single oxidation layer to define the
laser aperture and to isolate the interconnects
without the use of polyimide.
Figure 1 shows a typical VCSEL structure
with the oxidation layer. This layer is used to
define the oxide aperture and at the same time
isolate the electrical interconnects. The thickness of the layer is typically a quarter wavelength and is introduced just above the quantum wells. Figure 2 shows the two masks
fabrication process. The first step is the deposition and lift-off of the top Ti/Au contacts.
Next, an array of VCSEL posts connected by
the interconnects to the contact pads are
etched just below the active layer. Next, the
single AlAs layer is oxidized at 425 "C in N,H,O ambient. The oxidation process is
stopped when the pads and the interconnects
are completely oxidized and the laser aperture
has reached a desired aperture size. This is
accomplished by making the VCSEL posts
have a larger diameter than the width or length
of the contact pads. A thicker oxidation layer
can be used to reduce parasitic capacitance and
to increase the modulation speed. Using this
design we fabricated a complete 8 X 8 topemitting addressable array.
Figure 3a shows the L-I curve and Fig. 3b
the bit error rate measurements of a VCSEL
fabrication with -300-pm-long oxide interconnects. The laser was modulated at 622
Mbit/sec with a pseudorandom bit sequence
lZ31. The BER shows no error rate floor and a
BER of 10F9 was achieved. This speed is already comparable to that reported for protonimplanted VCSEL arrays3 Furthermore, an
open eye diagram was measured at 1 GBit/sec.
In summary we have proposed and demonstrated a novel very simple two-mask process
to fabricate very uniform independently addressable VCSEL arrays that combine the simplicity of fabrication of proton-implanted
VCSELs with the low threshold, high wall plug
efficiency, and uniformity of oxide-confined
VCSEL arrays.