Upgrade of the ATLAS Tile Calorimeter Electronics
P. Moreno1 on behalf of the ATLAS Tile Calorimeter System
1- IFIC/UV
Poster presented on the ICHEP 2014 International Conference on High Energy Physics
The ATLAS Tile Calorimeter
in Phase II)
In the LHC Phase II (in 2024) the peak luminosity A second concern in the design of the electronics
is to increase the reliability and robustness of the
will be increased by a factor of 5x compared to
system. Full redundancy in readout channels
the design luminosity (1032 cm-2 s-1) with
maintained beam energy 14 TeV at the center of from PMTs to the data links to the back-end is
foreseen. Modularity will be increased in frontmass. The average luminosity can also be
increased by a factor of 2 by luminosity leveling. end by reducing the minimum set of PMTs to be
operated at a time to 6 (instead of the present
This luminosity increase implies the redesign of
the majority of the read out electronics in TileCal. 48). Redundancy will be also present at the level
The TileCal Phase II upgrade aims to digitize all of low voltage power supplies.
Higher radiation tolerance electronics will be
the read out channels of the detector per bunch
needed on the front-end due to the luminosity
crossing, send the information to the back end
increase.
for storage and wait for the L1A for event
selection. This translates in a notorious increase
of the BW between front and back-end
electronics (from 165 Gbps in Phase I to 80 Tbps
Phase II Upgrade
TileCal is an hadronic calorimeter of the ATLAS experiment at the LHC. It
is composed of steel as absorber medium and plastic scintillating tiles as
active material. TileCal is a cylinder divided in four partitions: LBA, LBC,
EBA and EBC. Each partition contains 64 modules, which are
instrumented with scintillating tiles and up to 48 photomultiplier tubes
(PMTs). Every charged particle produces light in its interaction with the
active tiles which is converted the to an electrical pulse on the
correspondent PMT. This pulse is digitized on a subsequent step and
stored in pipeline memories waiting for the Level-1 trigger accept (L1A) to
be sent to the back-end electronics for further processing, forming a
readout channel. TileCal read-out is composed of roughly 10.000 of these
channels.
Future read-out architecture
TileCal Demonstrator Project
In order to evaluate and qualify the new electronics for the Phase II upgrade, a
demonstrator prototype is being developed. It will be equipped with the new calorimeter
front-end and back-end electronics, but will maintain compatibility with the present analog
trigger system. The hybrid slice of the detector is planned to be inserted in ATLAS during
2014.
Present read-out architecture
TileCal module
Hybrid architecture for the Demonstrator
ATLAS
Option 2: QIE ASIC
QIE is a Charge Integrator and Encoder designed in
Fermilab. Based on a current splitter with multiple
ranges and gated integrator + on-board flash ADC,
it works at 40 MHz with a 17 bit dynamic range
using 10 bits. The dead-timeless digitization avoids
the need for pulse shaping. It performs also
calibration functions. There are 20 chips available
and another 40 coming in the near future. TID test
up to 50 kRad showed good results.
Front-end Boards
Option 1: Modified 3-in-1 cards
These cards are based in the design of the
current system 3-in-1 cards from University.
Of Chicago. All components are discrete
Commercial OFF-The-Shelf
(COTS).Reception and shaping of the PMT
signals are performed in these boards,
providing analog output in two different gains
(32 and 64). They provide also calibration
capabilities and controls (charge injection,
integrator for physics calibration). These
cards show better linearity and lower noise
than previous version. Radiation tests have
been preformed on the modified 3-in-1 with
good results. This has been the selected
option for the demonstrator.
Modified 3-in-1
Option 3: FATALIC
It is a combined ASIC solution developed at
Clermont-Ferrand LPC:
FATALIC 3 ASIC is a current conveyor with a
shaping stage with 3 different gains (1, 8, 64).
TACTIC ADC is a 12-bit pipelined 40 MHz ADC
FATALIC 1 and 2 are already validated, and
version 3 is being tested. TACTIC 2 is being
designed.
QIE v 10.5
TACTIC v1
Main Board
Daughter Board
Optical Links
This board is the data and control interface to the modified 3-in-1 cards. It is in
charge of the digitization of the signals of the 12 PMTs, at a rate of 40 MHz in both
gains using 2 channel LVDS 560 Mbps ADCs. Besides it is responsible of the frontend boards control using Altera FPGAs. In addition, the Main Board transmits the
digitized and serialized data to the Daughter Board through a 400 pin FPGA
Mezzanine Connector (FMC). It is divided in two halves to achieve redundancy in the
low power distribution. The second version has been produced in the University of
Chicago and is under test with satisfactory results.
The Daughter Board provides high speed communication between front
end and back-end electronics. It is designed to preserve 2-fold
redundancy. Similarly to the Main Board, it is separated in two halves that
operate independently. Each side of the Daughter Board hosts a Kintex 7
FPGA that receives the digitized data from the Main Board ADCs and
transmits it to the back-end electronics out of the cavern using a QSFP
optical link (4 lanes at 10 Gbps). A radiation hard GBTx chip receives
control commands and clock information (TTC) from the back-end
electronics at 4.8 Gbps. This chip can take control of a FPGA programming
operation on both sides. The third version of the board has been recently
released in Stockholms Universitet and is being tested with good results.
Different studies about Bit Error Ratio (BER) between Vertical-Cavity
Surface-Emitting Lasers (VCSEL) and QSFPS have been performed
in order to select the best candidate for the optical communication
between front-end and back-end. QSFP+ transceivers based on
modulators (Mach-Zehnder interferometers) have shown the best
results operating above 40 Gbps (4 x 10 gbps lanes) with BER less
than 10-18 (1 error in 1000 days). The electro-optical chip is radiation
hard. No Single Event Upset (SEU) has been observed in a TID of
64kRad, fluence of 8 x 1011 p/cm2. The PIC microcontroller used for
configuration and monitoring also survives up to 20 kRad. Anti-fuse
FPGAs are being also evaluated to replace the microcontroller and
will be tested for radiation tolerance in the near future.
Log(BER)
Noise (mV)
Jitter (ps)
Nice open eye at
BER=10-18
Main Board
of the interface logic to the front-end.
sROD Demonstrator
Electronics. A second FPGA, Xililnx
Super ROD (sROD) will be the main
Kintex 7, equipped with 28 GTX
element on the back-end electronics,
transceivers is used for interfacing the
being the interface to the front-end
electronics and L0/L1 trigger in Phase II. L0/L1 trigger system as well as to
process and pack the readout data in the
It will perform three main tasks: data
current system format in order to
read-out, TTC information distribution to
integrate the demonstrator with the
the front end and propagation of DCS
Phase I electronics. Both FPGAs are
commands and monitoring values.
connected to 512 MB of DDR3 modules
The sROD Demonstrator is a scaled
and 1 Gb flash chip. The sROD is
version (1/8 in terms of input links) of the
compliant with double mid-size AMC
future sROD. It is capable to perform the
form-factor standard (180.6 mm x 148.5
readout of the new hybrid module (4 minimm). It can be plugged in an ATCA
drawers) using 4 QSFP connectors. One
carrier or a uTCA chassis.
Avago MiniPOD TX module is used for
communication with the L0/L1 trigger and The board, designed in the Universidad
one RX module for evaluation purposes. de Valencia, is already manufactured and
mounted and is test phase.
A Xilinx Virtex 7 FPGA equipped with 48
GTX transceivers (10 Gbps) is in charge
QSFP with optical modulator
Detail of the optical modulator
Daughter Board v3
Mini-drawers Mechanics
A new design has been made in order to
replace the present super-drawers. The
approach is to mechanically divide the module
structure in four parts to improve operability,
maintainability and handling. Cooling water is
conducted internally through pipe links. All
cabling is organized inside flexible carrier
trays.
Each mini-drawer will host 12 front-end boards
and their correspondent PMTs, one Main
Board and one Daughterboard with the optical
link to send the information to the sROD, one
HV regulation board and one adder base
board equipped with 3 adder cards needed for
the analog trigger of the hybrid module.
testing the present system
analog trigger outputs (only in
TileCal modules have to be
the hybrid module). All
tested inside ATLAS cavern
hardware components are
during maintenance periods.
already in hand. Integration of
PROMETEO (a Portable
them inside the portable
ReadOut Module for Tilecal
aluminum case and cabling is
ElectrOnics) is a standalone
ongoing.
system that will provide full
certification of the new front-end The software used for
communication with the system
electronics.
uses the IPbus protocol, which
It is based on a Xilinx VC707
evaluation board as processing is based on firmware on one
core of the system and a QSFP hand and in C++ or Python
libraries on the other. All
FMC module, for optical
interface with the mini-drawers. necessary software and
firmware is under development
Custom HV and LED Driver
stage.
boards are used for testing the
PMTs and a custom 16 channel
ADC FMC board is used for
Portable Test-bench
Mini-drawer cross section
sROD Demonstrator functionality
Mini-drawer
sROD Demonstrator protoype
Xilinx VC707
Read out Tests
The communication between the front-end
and back-end interfaces has been tested
using the Daughter board and an emulated
version of the sROD (a VC707 development
board). The transmission of data through
optical links (downlink working at 5 Gbps
and an uplink running at 10 Gbps) has been
proven using data generators and checkers
with satisfactory results.
The Daughterboard is assembled on top of
the Main board through the FMC connector.
Propagation of commands from the backend electronics to specific front-end boards
is performed using the 5Gbps downlink.
These commands are generated and sent
from a laptop to the sROD using the IPbus
protocol. The sROD forwards the commands
to the Daughter board were they are
redirected to the proper FPGA in the Main
board, which targets the 3-in-1 card. These
commands perform actions like setting a
pedestal value or triggering a charge
injection pulse on the read out channel. The
first results have been be observed directly
in test-points in the 3-in-1 cards using an
oscilloscope. In a further step the serial
stream of digitized data coming from the
ADCs in the Main board is de-serialized in
the Daughter board and sent to the sROD
for the read out. Once the correct pulses
have been observed, linearity tests of each
channel using offset and charge injection
pulses have been performed in the 12 read
out channels of a mini-drawer. These tests
have been necessary in order to debug and
validate different parts of the system from
hardware to firmware or software. The
results of these tests belong to an early
phase of the project development but have
been considered as promising by the TileCal
community. Plots on the right show the
linearity for one of the channels in pedestal
and charge injection measures as well as
the digitized samples of a charge injection
pulse shape.
Test setup for 1
TileCal module
IPbus graphical tool