CPVLIS Laminated Interconnection System for CPV
Receiver Panels, Development and Tests
Ricard Pardell1, a), Eric Martínez1, b) and Daniel Bernal1, c)
1
Valldoreix Greenpower, S.L.U.
a)
[email protected]
[email protected]
c)
[email protected]
b)
Abstract. Within the development of a new CPV system (CPVRS), a novel approach for receiver interconnection and
encapsulation has been developed. This paper explains the different material combinations which have been tested and
the intermediate and final results.
INTRODUCTION
The main objective of the CPVLIS technology is to increase the electrical insulation level and long term
reliability of CPV modules and at the same time provide a good thermal path for heat dissipation.
Several layers of electrically insulating, interconnection and heat conductive materials are heat laminated
together with CPV receivers, obtaining a sandwiched receiver panel which attains an electrical insulation level in the
order 100 G in dry conditions and in the order 10 G in wet conditions.
The paper will explain the development process and accelerated cycling and field test results.
FIGURE 1. CPVLIS receiver panel passing insulation breakdown 3.000V test after being water sprayed
CPVLIS DESCRIPTION
The CPVLIS technology is based on the sandwich concept in which several electrically insulating layers,
electrical interconnection between receiver/receiver and receiver/end connector and heat conductive materials are
heat laminated together with CPV receivers. The result consists in a sandwiched CPV panel measuring 620x770 mm
with all the electrical interconnection components between two dielectric insulation layers which attains an electrical
insulation level in the order 100 G in dry conditions and 12 G in wet conditions. Both dielectric insulation layers
are composed of encapsulating material and a rigid material, so the one under the interconnection level is composed
of EVA and PET layers and the one above the interconnection level is composed of EVA and PVDF layers.
Furthermore, the CPVLIS technology assures that high level insulation requirements are fulfilled both under dry
and wet conditions. This means that CPV panel will not pose any safety risk in case of internal condensation or
water leakages in the CPV module due to water is not able to reach neither the receivers inside nor the
interconnectors because of a complete encapsulation of all this components achieved in the heat lamination.
Moreover, in case of water in contact with the CPV panel, it will not deteriorate the materials that take part in
CPVLIS technology due to water-tight encapsulation and water-proof materials surfaces characteristics.
On the other hand, CPVLIS concept also offers a good thermal path for cell heat dissipation and the main
component is a heat sink aluminum plate acting at the same time as the mechanical substrate for the CPV receivers.
Each receiver includes a secondary optic, a bypass diode and, most important part, a CPV cell mounted on a suitable
thermally conductive DBC substrate. In order to attach and get a good thermal path between cell and heat sink plate
is placed a thermally conductive double-sided structural adhesive tape between DBC back side and aluminum plate
top side.
DETAILED CPVLIS DESIGN
In order to obtain all insulation and heat dissipation advantages that CPVLIS technology offer, the procedure is
actually divided into five main phases: heat sink back plate phase, lower dielectric insulation layer, interconnection
phase, upper dielectric insulation layer and heat lamination process.
Heat Sink Back Plate
The heat sink back plate is based on an aluminum plate made from Al 1050 offering the best high thermal
conductivity and is 3 mm thick to provide enough stiffness and heat spreading. The basic heat dissipation
mechanism is through convection to the environment air through the back side. Also, the heat sink back plate is
anodized, surface treatment that increases emissivity in the infrared spectra.
First step in this phase involves the CPV receivers accurate placement on the heat sink plate using an own
designed tooling that offers the required positioning tolerances of them.
FIGURE 2. Receiver placement tooling
In addition, it should be added that each CPV receiver is made from a CPV cell mounted on a suitable thermally
conductive DBC substrate, a secondary optic that is attached on the cell using transparent potting and a bypass diode
included in the DBC receiver circuit. Then, on the back side of DBC substrate is attached one side of a thermally
conductive double-sided structural adhesive tape that will attach the CPV receiver to the heat sink plate.
Lower Dielectric Insulation Layer
The lower dielectric insulation layer is the one located between top side of heat sink back plate and CPV panel
interconnection. In this phase the basic design requirement includes that total layer thickness must be the same than
the height between the heat sink plate and the interconnection pad to avoid empty points or zones with less
insulation material once lamination is done.
FIGURE 3. Distance “h” to be covered with the sum of the thicknesses of lower electrically insulation layers
The height to be covered in CPV receiver panel is about 1,08 mm, so lower dielectric insulation layer is
composed by the following layers configuration:
TABLE 1. Lower electrically insulating layers configuration
Lower dielectric layer configuration Electrically insulating material Thickness [mm]
First layer
Second layer
Third layer
EVA
EVA
Primer + PET + Primer
0,460
0,460
0,165
Dielectric strength [kV/mm]
21
21
17
Dielectric strength reached between heat sink plate and CPV panel interconnection using this configuration is
about more than 20kV.
Design requirement for EVA layer (encapsulant material) relies on having windows with same dimensions than
DBC receiver and end connector external boundaries in order to allow both components to protrude through the
insulation layer.
FIGURE 4. EVA layer windows
Design requirement for PET layer (rigid material) is based on having windows with interconnection pads
boundary dimensions. At the same time should be considered secondary optic dimensions in order to allow receiver
and end connector elements to pass through the insulation layer.
FIGURE 5. PET layer windows
Interconnection Phase
The interconnection phase is based on interconnect each interconnection pad, either receiver/receiver or
receiver/end connector, using Cu ribbon strips with a 17 micron 62Sn 36Pb 2Ag coating per side. This operation is
done using HF25 DC RESISTANCE WELDING EQUIPMENT from MIYACHI UNITEK, so each ribbon
interconnector is welded to interconnector pads by the welding resistance principle.
FIGURE 6. Ribbon interconnectors in the welding resistance process
Upper Dielectric Insulation Layer
The upper dielectric insulation layer is the one located on the CPV panel interconnection. In this phase,
electrically insulating layers to lay on ribbon interconnection is based on the following configuration:
TABLE 2. Upper dielectric electrically insulating layers configuration
Upper dielectric layer configuration Electrically insulating material Thickness [mm] Dielectric strength [kV/mm]
Fourth layer
Fifth layer
EVA
PVDF
0,460
0,300
21
13
Dielectric strength reached between ribbon interconnection and PVDF layer external side using this
configuration is about more than 13,5 kV.
Design requirement in this phase is the same for both upper layers, either encapsulant (EVA) layer and rigid
(PVDF) layer due to in this case the main issue lies on cover as much as possible the visible surface. Then,
boundaries for the windows in this phase are limited by secondary optic and end connector fast-ON.
FIGURE 7. Upper dielectric layers windows
Heat Lamination Process
The lamination process which all electrically insulating layers can act like an insulation sandwich around ribbon
interconnection is done using a lamination machine SAP SOLAR L-2000. This equipment includes 7 different heat
plates and is capable to reach the vacuum while applying pressure on the CPV panel.
FIGURE 8. CPVRS receiver panel just before the lamination process
Lamination parameters in CPVLIS procedure are shown in the following table:
TABLE 3. Lamination process parameters
Lamination process parameters
Plates temperature [ºC]
Vacuum phase time [s]
Pressure phase time [s]
Cooling phase time [s] (artificial air ventilation)
Values
110
300
60
240
CPVLIS ELECTRICAL STRESS TESTS
The CPVLIS electrical stress tests are described below:
1.
Test VGP.SS.0: Dry insulation test at SATP (Standard Ambient Temperature and Pressure) conditions:
Resistance measure R>50 MΩ at 500V during 1 minute.
2.
Test VGP.SS.1: Dry insulation test at SATP conditions:
2.1. Resistance measure R>50 MΩ at 500V before doing any insulation stress.
2.2. Test up to 2kV: ramp from 0 to 2kV in 1 minute, then stay at 2kV during 2 minutes.
2.3. Resistance measure R>50 MΩ at 500V during 2 minutes.
3.
Test IEC62108.10.4 [1] [2]:
3.1. Test up to 3kV: ramp from 0 to 3kV in 1 minute, then stay at 3kV during 2 minutes.
3.2. Resistance measure R>50 MΩ at 500V during 2 minutes.
4.
VGP.SS.1: Wet insulation test at SATP conditions.
4.1. Test up to 3kV: ramp from 0 to 3kV in 1 minute, then stay at 3kV during 2 minutes.
4.2. Resistance measure R>50 MΩ at 500V during 2 minutes
CPVLIS ELECTRICAL INSULATION MEASUREMENT EQUIPMENT
The CPVLIS electrical insulation measurement equipment is described below:
 MEGGER MIT-420: equipment used in test VGP.SS.0.
 SEFELEC SMG 500: equipment used in tests VGP.SS.1, IEC62108.10.4 and VGP.SS.1.
FIGURE 9. MEGGER MIT-420 and SEFELEC SMG 500 insulation tester equipment
CPVLIS ELECTRICAL STRESS TESTS RESULTS
The CPVLIS electrical stress VGP.SS.0 test was applied to 165 samples and the electrical insulation results are
positive for all the samples, all samples have passed the test with very satisfying values against R > 0.050 GΩ
requirement:




100% of samples pass VGP.SS.0 test.
More than 67% of the samples offer an electrical insulation more than 75 GΩ.
Electrical insulation mean value for all tested samples is about 84.6 GΩ.
Minimum electrical insulation value is about 30 GΩ.
FIGURE 10. Electrical insulation results for test VGP.SS.0
After 6 months operating and producing electricity in a complete integrated CPVRS 2 axis tracker system, 16
CPV modules have been tested again following the CPVLIS electrical stress VGP.SS.0 test and the electrical
insulation test results are extremely positive. 100% of the 16 samples pass the test offering, all of them, an insulation
level over the 100 GΩ.
The CPVLIS electrical stress VGP.SS.1 + IEC62108.10.4 tests were applied to 8 samples and the electrical
insulation results are positive for all the samples, all samples have passed the test with very satisfying values against
R > 0.050 GΩ requirement:




100% of samples pass the sequence of VGP.SS.1 test + IEC62108.10.4 test.
More than 33% of the samples offer an electrical insulation more than 15 GΩ.
Electrical insulation mean value for all tested samples is about 25.9 GΩ.
Minimum electrical insulation value is about 7.5 GΩ.
FIGURE 11. Electrical insulation results for sequence of tests VGP.SS.1 + IEC62108.10.4
The CPVLIS electrical stress VGP.SS.2 test were applied to 2 samples spraying water simulating water
condensation on the CPV module. Electrical insulation results are positive for both samples, both of them have
passed the test with very satisfying values against R > 0.050 GΩ requirement:




100% of samples pass the VGP.SS.2 test.
More than 100% of the samples offer an electrical insulation more than 8 GΩ.
Electrical insulation mean value for all tested samples is about 10.55 GΩ.
Minimum electrical insulation value is about 8.5 GΩ.
FIGURE 12. Electrical insulation results for test VGP.SS.2
CONCLUSIONS
The CPVLIS technology offers a high level and long term reliable electrical insulation to CPV receiver panels
passing all the CPVLIS electrical stress tests with values with three orders of magnitude higher that the 0.050 GΩ
required.
The CPVLIS is a high electrical insulation and fast and reliable assembly method not only at dry conditions but
to wet conditions too. This means that CPV panel will not pose any safety risk in case of internal condensation or
water leakages in the CPV module due to water is not able to reach neither the receivers inside nor the
interconnectors because of a complete encapsulation of all this components achieved in the heat lamination.
In order to sum up all the results:
 The entire quantity of samples, 100%, passed the electrical stress tests and more than 67% of them with an
electrical insulation level more than 75 GΩ (mean value is about 84.6 GΩ).
 In case of wet conditions, spraying water on CPV receivers panel simulating water condensation or water
leakages in the CPV module, 100% of the tested CPV receivers panels pass the CPVLIS electrical stress
tests reaching an electrical insulation value up to 12.6 GΩ (mean value is about 10.55 GΩ).
Finally, must be noted that 100% of the tested CPV receiver panels that were installed, operating and producing
energy during last 6 months in a CPVRS 2 axis tracking system offer an electrical insulation level about more than
100 GΩ.
REFERENCES
1.
2.
3.
R. Pardell “CPVLIS Concentration Photovoltaics Laminated Interconnection System” U.S. Provisional Patent
Application, 15/10/2012
IEC 62108 International Standard. Concentrator photovoltaic (CPV) modules and assemblies – Design
qualification and type approval. Edition 1.0. 12/2007
IEC 62688 International Standard. Concentrator photovoltaic (CPV) module and assembly safety qualification.
Draft F. 22/7/2011