5 4 3 2 1 01 14" BY6/BY6D Comal Block Diagram PCB STACK UP LAYER 1 : TOP LAYER 2 : GND D DDRIII-SODIMM1 DDRIII-SODIMM2 LAYER 3 : IN1 P12, 13 LAYER 4 : SVCC LAYER 5 : IN2 800~1866 MHZ LAYER 6 : IN3 LAYER 8 : BOT Transformer P28 PCIE-0 10/100M AR8152B P27 PCI-Express FS1r2 socket 722 pin uPGA P28 GPU PCI-E x16 PCIE-1 RJ45 WLAN Con. P28 P32 HDMI CONN 35mm X 35mm Atheros D LVDS PANEL P26 Trinity APU 35W X'TAL 25MHz LAYER 7 : GND TRAVIS_L ANX3111 CPU Dual Channel DDR III P30 P3, 4, 5, 6 VRAM DDR3-128M*8 VRAM DDR3-256M*8 Thames LE USB2-7 VRAM DDRIII P22, 23 29mm X 29mm P14~21, 24 UMI LINK DP1(x4) 2.5GT /s X'TAL 27.0MHz POWER SYSTEM ISL88731CHRTZ-T TPS51123A TPS51216RUKR TPS51211DSCR TPS51211DSCR OSL6277 G9661-25ADJF12U ISL95870AHRUZ-L UMI(x4) SATA - HDD Con. P33 C DMI SATA 0 SATA - ODD Con. VGA-DAC SATA P33 CRT Con. SATA 1 USB3-0 USB 3.0 (Port0~3) USB3.0 USB 2.0 (Port0~13) USB2.0 USB2-10 P25 Hudson M3 USB3-1 USB3.0 re-driver IC P25 P25 FCH Card Reader Con. P31 USB2-5 Card Reader 3 IN 1 (AU6437B53-GDL-GR) P31 24.5mm X 24.5mm USB2-11 USB3.0 Con. X'TAL 32.768KHz USB2-6 CCD P25 RTC BATTERY P7, 8, 9, 10, 11 P8 IHDA LPC SPI EC 885L P36 Port-A Port-B MIC JACK HP HALL Sensor LED SPI Flash K/B Con. SPK Con. P29 P29 P29 P41 P42 P43 P44 CHARGER P37 +15V +3VPCU +3V_S5 +3V +5VPCU +5V_S5 +5V P38 P34 B +1.5VSUS +1.5V_S5 +1.5V P39 +1.2V_VDDPR P40 +1.1V_DUAL +1.1V P41 +VDD_CORE +VDDNB_CORE P42 +2.5V_VDDA DISCHARGE P43 P9 P29 FAN P32 P31 P35 Touch Pad /B Con. P35 Power /B Con. P35 +VGPU_CORE +3V_GPU A A +1.8V_GPU +1.5V_GPU +1V_GPU P44 Quanta Computer Inc. PROJECT :BY6/BY6D Size Document Number Rev A1A Block Diagram Date: 5 4 C P40 NVRAM LPC Audio Codec CX20671-21Z P39 +SMDDR_VTERM +SMDDR_VREF P32 B Azalia P38 USB3.0 Con. AMD USB2-0 USB2.0 Con. P32 P37 3 2 Monday, February 13, 2012 1 Sheet 1 of 47 5 4 3 2 1 02 Table of Contents PAGE DESCRIPTION BOI-FUNCTIONS C 1 Schematic Block Diagram 2 Front Page 3-6 Processor CPU 7 - 11 FCH CLG 8 RTC RTC 12 - 13 DDRIII SO-DIMM DDR 14 - 21 Thames/Seymour(M2) VGA 22 - 23 VRAM - DDR3 VGA 24 PX VGA 25 USB Connector USB USB 3.0 Redriver U3B USB Sleep Charger SLC 26 TRAVIS Decoder LDS 27 HDMI comm part HDM CEC CEC 28 Atheros LAN LAN 29 Codec (CX20671-21Z) ADO 30 MINI Card (Wi-Fi & WIMAX) MNW 31 Card reader MMC LED LED VGA Connector VGA LCD Panel LDS CRT & CRT BUS SWITCH CRT CCD CCD 32 33 34 35 B POWER PLANE HALL SENSOR&BACK LIGHT SWITCH HSR HDD HDD ODD ODD Thermal THC FAN THC KeyBoard KBC TP&FP board TPD,FPD Power SW PSW 36 EC NPCE885LA0DX KBC 37 Charger (ISL88731CHRTZ-T) PWM 38 System 5V/3V DDR 1.5V PWM 39 40 +1.2V_VDDPR PWM 41 PWM 42 +1.1V_DUAL +VCC_CORE 2+1 43 Discharge PWM 44 GPU_CORE PWM 45 Power Sequence 46 Change List PWM VIN +VCCRTC Power States ACTIVE IN CONTROL SIGNAL D VOLTAGE 10V~+19V S0~S5 +3.0V~+3.3V S0~S5 +3V +3.3V MAIN_ON +3V_S5 +3.3V S5_ON S0~S5 +3VPCU +3.3V AC/DC Insert enable S0~S5 +5V +5V MAIN_ON S0 +5V_S5 +5V S5_ON S0~S5 +5VPCU +5V WIMAX_P S0 S0~S5 AC/DC Insert enable +3.3V +1.5V +1.5VSUS D WMAX_P S0 S5_ON S0~S3 +1.5V +1.5V MAIN_ON S0 +1.2V_VDDPR +1.2V VDDA_PWRGD S0 +1.1V_DUAL +1.1V +1.1V_DUAL_EN S0~S5 +1.1V +1.1V MAIN_ON S0 C +VDD_CORE ~ VDDA_PWRGD S0 +VDDNB_CORE ~ VDDA_PWRGD S0 PX_MODE S0 +VGPU_CORE +1.8V_GPU +1.8V PE_GPIO1 S0 +1V_GPU +1V DGPU_PWREN S0 +3V_GPU +3.3V PE_GPIO1 S0 +1.5V_GPU +1.5V PX_MODE_D S0 +2.5V_VDDA +2.5V MAIN_ON S0 B PWM GND PLANE GND_SIGNAL 8769GND PAGE 32 36 28 GND ALL ADOGND 29 A ITEM Value Code FUNCTIONS CEC 1 CEC@ 2 Debug@ HDT+ Debug 3 EV@ DISCRETE 4 IV@ 5 U3@ Internal USB 3.0 6 1G4@ VRAM 1Gb*4 7 1G8@ VRAM 1Gb*8 8 2G@ VRAM 2Gb 9 AMD@ AMD VRAM 10 DIS@ DISCRETE 11 M2@ M2 FCH 12 M3@ M3 FCH 13 NMP@ LPC Debug Card 14 PX4@ PX4 Mode 15 PX5@ PX5 Mode 16 Sam@ Samsung VRAM 17 U2@ USB 2.0 (colay W USB 3.0) UMA A Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev A1A POWER STAGE & BOI-FUNCTION Date: 5 4 3 2 Monday, February 13, 2012 Sheet 1 2 of 47 5 4 3 2 TO WLAN PCIE_RXP_LAN PCIE_RXN_LAN PCIE_RXP_WLAN PCIE_RXN_WLAN [8] [8] [8] [8] [8] [8] [8] [8] B UMI_RXP0 UMI_RXN0 UMI_RXP1 UMI_RXN1 UMI_RXP2 UMI_RXN2 UMI_RXP3 UMI_RXN3 +1.2V_VDDP R1 AE5 AE6 AD8 AD7 AC9 AC8 AC5 AC6 UMI_RXP0 UMI_RXN0 UMI_RXP1 UMI_RXN1 UMI_RXP2 UMI_RXN2 UMI_RXP3 UMI_RXN3 AG8 AG9 AG6 AG5 AF7 AF8 AE8 AE9 196/F_6 P_ZVDDP AG11 P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3 GRAPHICS PCIE_RXP_LAN PCIE_RXN_LAN PCIE_RXP_WLAN PCIE_RXN_WLAN P_UMI_RXP0 P_UMI_RXN0 P_UMI_RXP1 P_UMI_RXN1 P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3 P_GFX_TXP0 P_GFX_TXN0 P_GFX_TXP1 P_GFX_TXN1 P_GFX_TXP2 P_GFX_TXN2 P_GFX_TXP3 P_GFX_TXN3 P_GFX_TXP4 P_GFX_TXN4 P_GFX_TXP5 P_GFX_TXN5 P_GFX_TXP6 P_GFX_TXN6 P_GFX_TXP7 P_GFX_TXN7 P_GFX_TXP8 P_GFX_TXN8 P_GFX_TXP9 P_GFX_TXN9 P_GFX_TXP10 P_GFX_TXN10 P_GFX_TXP11 P_GFX_TXN11 P_GFX_TXP12 P_GFX_TXN12 P_GFX_TXP13 P_GFX_TXN13 P_GFX_TXP14 P_GFX_TXN14 P_GFX_TXP15 P_GFX_TXN15 P_GPP_TXP0 P_GPP_TXN0 P_GPP_TXP1 P_GPP_TXN1 P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3 GPP TO PCIE-LAN [28] [28] [30] [30] P_GFX_RXP0 P_GFX_RXN0 P_GFX_RXP1 P_GFX_RXN1 P_GFX_RXP2 P_GFX_RXN2 P_GFX_RXP3 P_GFX_RXN3 P_GFX_RXP4 P_GFX_RXN4 P_GFX_RXP5 P_GFX_RXN5 P_GFX_RXP6 P_GFX_RXN6 P_GFX_RXP7 P_GFX_RXN7 P_GFX_RXP8 P_GFX_RXN8 P_GFX_RXP9 P_GFX_RXN9 P_GFX_RXP10 P_GFX_RXN10 P_GFX_RXP11 P_GFX_RXN11 P_GFX_RXP12 P_GFX_RXN12 P_GFX_RXP13 P_GFX_RXN13 P_GFX_RXP14 P_GFX_RXN14 P_GFX_RXP15 P_GFX_RXN15 P_UMI_TXP0 P_UMI_TXN0 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3 UMI-LINK C PEG_RXP0 PEG_RXN0 PEG_RXP1 PEG_RXN1 PEG_RXP2 PEG_RXN2 PEG_RXP3 PEG_RXN3 PEG_RXP4 PEG_RXN4 PEG_RXP5 PEG_RXN5 PEG_RXP6 PEG_RXN6 PEG_RXP7 PEG_RXN7 PEG_RXP8 PEG_RXN8 PEG_RXP9 PEG_RXN9 PEG_RXP10 PEG_RXN10 PEG_RXP11 PEG_RXN11 PEG_RXP12 PEG_RXN12 PEG_RXP13 PEG_RXN13 PEG_RXP14 PEG_RXN14 PEG_RXP15 PEG_RXN15 PCI EXPRESS P_ZVDDP P_ZVSS AB2 AB1 AA3 AA2 Y5 Y4 Y2 Y1 W3 W2 V5 V4 V2 V1 U3 U2 T5 T4 T2 T1 R3 R2 P5 P4 P2 P1 N3 N2 M5 M4 M2 M1 PEG_TXP0_C PEG_TXN0_C PEG_TXP1_C PEG_TXN1_C PEG_TXP2_C PEG_TXN2_C PEG_TXP3_C PEG_TXN3_C PEG_TXP4_C PEG_TXN4_C PEG_TXP5_C PEG_TXN5_C PEG_TXP6_C PEG_TXN6_C PEG_TXP7_C PEG_TXN7_C PEG_TXP8_C PEG_TXN8_C PEG_TXP9_C PEG_TXN9_C PEG_TXP10_C PEG_TXN10_C PEG_TXP11_C PEG_TXN11_C PEG_TXP12_C PEG_TXN12_C PEG_TXP13_C PEG_TXN13_C PEG_TXP14_C PEG_TXN14_C PEG_TXP15_C PEG_TXN15_C C1 AD5 AD4 AD2 AD1 AC3 AC2 AB5 AB4 PCIE_TXP_LAN_C PCIE_TXN_LAN_C PCIE_TXP_WLAN_C PCIE_TXN_WLAN_C C33 0.1U/10V_4X C35 0.1U/10V_4X AG2 AG3 AF4 AF5 AF1 AF2 AE2 AE3 UMI_TXP0_C UMI_TXN0_C UMI_TXP1_C UMI_TXN1_C UMI_TXP2_C UMI_TXN2_C UMI_TXP3_C UMI_TXN3_C C37 0.1U/10V_4X C39 0.1U/10V_4X C41 0.1U/10V_4X AH11 P_ZVSS 196/F_6 R2 C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 C29 C31 C43 [email protected]/10V_4X C2 [email protected]/10V_4X C4 [email protected]/10V_4X C6 [email protected]/10V_4X C8 [email protected]/10V_4X C10 [email protected]/10V_4X C12 [email protected]/10V_4X C14 [email protected]/10V_4X C16 [email protected]/10V_4X C18 [email protected]/10V_4X C20 [email protected]/10V_4X C22 [email protected]/10V_4X C24 [email protected]/10V_4X C26 [email protected]/10V_4X C28 [email protected]/10V_4X C30 [email protected]/10V_4X C32 [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_4X C34 0.1U/10V_4X C36 0.1U/10V_4X C38 0.1U/10V_4X C40 0.1U/10V_4X C42 0.1U/10V_4X C44 0.1U/10V_4X 0.1U/10V_4X PEG_TXP0 PEG_TXN0 PEG_TXP1 PEG_TXN1 PEG_TXP2 PEG_TXN2 PEG_TXP3 PEG_TXN3 PEG_TXP4 PEG_TXN4 PEG_TXP5 PEG_TXN5 PEG_TXP6 PEG_TXN6 PEG_TXP7 PEG_TXN7 PEG_TXP8 PEG_TXN8 PEG_TXP9 PEG_TXN9 PEG_TXP10 PEG_TXN10 PEG_TXP11 PEG_TXN11 PEG_TXP12 PEG_TXN12 PEG_TXP13 PEG_TXN13 PEG_TXP14 PEG_TXN14 PEG_TXP15 PEG_TXN15 PEG_TXP0 [14] PEG_TXN0 [14] PEG_TXP1 [14] PEG_TXN1 [14] PEG_TXP2 [14] PEG_TXN2 [14] PEG_TXP3 [14] PEG_TXN3 [14] PEG_TXP4 [14] PEG_TXN4 [14] PEG_TXP5 [14] PEG_TXN5 [14] PEG_TXP6 [14] PEG_TXN6 [14] PEG_TXP7 [14] PEG_TXN7 [14] PEG_TXP8 [14] PEG_TXN8 [14] PEG_TXP9 [14] PEG_TXN9 [14] PEG_TXP10 [14] PEG_TXN10 [14] PEG_TXP11 [14] PEG_TXN11 [14] PEG_TXP12 [14] PEG_TXN12 [14] PEG_TXP13 [14] PEG_TXN13 [14] PEG_TXP14 [14] PEG_TXN14 [14] PEG_TXP15 [14] PEG_TXN15 [14] PCIE_TXP_LAN PCIE_TXN_LAN PCIE_TXP_WLAN PCIE_TXN_WLAN UMI_TXP0 UMI_TXN0 UMI_TXP1 UMI_TXN1 UMI_TXP2 UMI_TXN2 UMI_TXP3 UMI_TXN3 PCIE_TXP_LAN [28] PCIE_TXN_LAN [28] PCIE_TXP_WLAN [30] PCIE_TXN_WLAN [30] UMI_TXP0 UMI_TXN0 UMI_TXP1 UMI_TXN1 UMI_TXP2 UMI_TXN2 UMI_TXP3 UMI_TXN3 D PEG X 16 [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] [14] D AB8 AB7 AA9 AA8 AA5 AA6 Y8 Y7 W9 W8 W5 W6 V8 V7 U9 U8 U5 U6 T8 T7 R9 R8 R5 R6 P8 P7 N9 N8 N5 N6 M8 M7 03 B2A U1F PEG_RXP0 PEG_RXN0 PEG_RXP1 PEG_RXN1 PEG_RXP2 PEG_RXN2 PEG_RXP3 PEG_RXN3 PEG_RXP4 PEG_RXN4 PEG_RXP5 PEG_RXN5 PEG_RXP6 PEG_RXN6 PEG_RXP7 PEG_RXN7 PEG_RXP8 PEG_RXN8 PEG_RXP9 PEG_RXN9 PEG_RXP10 PEG_RXN10 PEG_RXP11 PEG_RXN11 PEG_RXP12 PEG_RXN12 PEG_RXP13 PEG_RXN13 PEG_RXP14 PEG_RXN14 PEG_RXP15 PEG_RXN15 1 C TO PCIE-LAN TO WLAN [8] [8] [8] [8] [8] [8] [8] [8] B Trinity APU Close by HDT+ Conector HDT+ Connector Debug only APU_TRST# [5] APU_TRST# A APU_TDI APU_TCK APU_TMS APU_TRST# +1.5VSUS R9 R25 R24 R23 DEBUG@0_4 DEBUG@10K_4 DEBUG@10K_4 DEBUG@10K_4 R3 R4 R5 R6 1K_4 1K_4 1K_4 1K_4 APU_DBREQ# R7 1K_4 +1.5VSUS J1 1 3 5 7 9 11 13 15 17 19 CPU_VDDIO1 GND1 GND2 GND3 CPU_TRST_L CPU_DBRDY3 CPU_DBRDY2 CPU_DBRDY1 GND4 CPU_VDDIO2 CPU_TCK CPU_TMS CPU_TDI CPU_TDO CPU_PWROK_BUF CPU_RST_L_BUF CPU_DBRDY0 CPU_DBREQ_L CPU_PLLTEST0 CPU_PLLTEST1 2 4 6 8 10 12 14 16 18 20 APU_TCK APU_TMS APU_TDI APU_TDO APU_PWROK_BUF APU_RST_L_BUF APU_DBRDY APU_DBREQ# APU_TEST19_PLLTEST0 APU_TEST18_PLLTEST1 APU_TCK [5] APU_TMS [5] APU_TDI [5] APU_TDO [5] APU_PWROK_BUF [5] APU_RST_L_BUF [5] APU_DBRDY [5] APU_DBREQ# [5] APU_TEST19_PLLTEST0 [5] APU_TEST18_PLLTEST1 [5] A Quanta Computer Inc. PROJECT :BY6/BY6D *DEBUG@HDT+ HEADER Size Document Number Rev 1A APU 1/4(PCIE/UMI/GPP/HDT) Date: 5 4 3 2 Tuesday, February 14, 2012 Sheet 1 3 of 47 5 4 3 M_A_DQ[0..63] U1A [12] M_A_A[15:0] M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 D [12] M_A_BS#[2..0] M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 C [12] [12] [12] [12] M_A_DQSP0 M_A_DQSN0 M_A_DQSP1 M_A_DQSN1 M_A_DQSP2 M_A_DQSN2 M_A_DQSP3 M_A_DQSN3 M_A_DQSP4 M_A_DQSN4 M_A_DQSP5 M_A_DQSN5 M_A_DQSP6 M_A_DQSN6 M_A_DQSP7 M_A_DQSN7 M_A_CLKP0 M_A_CLKN0 M_A_CLKP1 M_A_CLKN1 [12] M_A_CKE0 [12] M_A_CKE1 [12] M_A_ODT0 [12] M_A_ODT1 +1.5VSUS R542 1K/F_4 [12] M_A_CS#0 [12] M_A_CS#1 [12] M_A_RAS# [12] M_A_CAS# [12] M_A_WE# [12] M_A_EVENT# C52 220P/50V_4X E14 J17 E21 F25 AD27 AC23 AD19 AC15 M_A_DQSP0 M_A_DQSN0 M_A_DQSP1 M_A_DQSN1 M_A_DQSP2 M_A_DQSN2 M_A_DQSP3 M_A_DQSN3 M_A_DQSP4 M_A_DQSN4 M_A_DQSP5 M_A_DQSN5 M_A_DQSP6 M_A_DQSN6 M_A_DQSP7 M_A_DQSN7 G14 H14 G18 H18 J21 H21 E27 E26 AE26 AD26 AB22 AA22 AB18 AA18 AA14 AA15 M_A_CLKP0 M_A_CLKN0 M_A_CLKP1 M_A_CLKN1 T21 T22 R23 R24 M_A_CKE0 M_A_CKE1 H28 H27 M_A_ODT0 M_A_ODT1 Y25 AA27 M_A_CS#0 M_A_CS#1 V22 AA26 M_A_RAS# M_A_CAS# M_A_WE# V21 W24 W23 H25 M_A_RST# M_A_EVENT# T24 [12] M_A_RST# B U24 U21 L23 M_A_BS#0 M_A_BS#1 M_A_BS#2 [12] M_A_DM[7..0] [12] [12] [12] [12] [12] [12] [12] [12] [12] [12] [12] [12] [12] [12] [12] [12] U20 R20 R21 P22 P21 N24 N23 N20 N21 M21 U23 M22 L24 AA25 L21 L20 W20 +MEMVREF_CPU +1.5VSUS R543 +M_ZVDDIO 39.2/F_4 W21 2 [12] E13 J13 H15 J15 H13 F13 F15 E15 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 H17 F17 E19 J19 G16 H16 H19 F19 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 H20 F21 J23 H23 G20 E20 G22 H22 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 G24 E25 G27 G26 F23 H24 E28 F27 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 AB28 AC27 AD25 AA24 AE28 AD28 AB26 AC25 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 Y23 AA23 Y21 AA20 AB24 AD24 AA21 AC21 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 AA19 AC19 AC17 AA17 AB20 Y19 AD18 AD17 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 AA16 Y15 AA13 AC13 Y17 AB16 AB14 Y13 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 [13] M_B_BS#[2..0] [13] M_B_DM[7..0] [13] [13] [13] [13] [13] [13] [13] [13] [13] [13] [13] [13] [13] [13] [13] [13] [13] [13] [13] [13] M_B_DQSP0 M_B_DQSN0 M_B_DQSP1 M_B_DQSN1 M_B_DQSP2 M_B_DQSN2 M_B_DQSP3 M_B_DQSN3 M_B_DQSP4 M_B_DQSN4 M_B_DQSP5 M_B_DQSN5 M_B_DQSP6 M_B_DQSN6 M_B_DQSP7 M_B_DQSN7 M_B_CLKP0 M_B_CLKN0 M_B_CLKP1 M_B_CLKN1 [13] M_B_CKE0 [13] M_B_CKE1 [13] M_B_ODT0 [13] M_B_ODT1 +1.5VSUS R14 1K/F_4 [13] M_B_CS#0 [13] M_B_CS#1 [13] M_B_RAS# [13] M_B_CAS# [13] M_B_WE# [13] M_B_RST# [13] M_B_EVENT# C53 220P/50V_4X Place close to APU within 1" M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 T27 P24 P25 N27 N26 M28 M27 M24 M25 L26 U26 L27 K27 W26 K25 K24 M_B_BS#0 M_B_BS#1 M_B_BS#2 U27 T28 K28 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 D14 A18 A22 C25 AF25 AG22 AH18 AD14 M_B_DQSP0 M_B_DQSN0 M_B_DQSP1 M_B_DQSN1 M_B_DQSP2 M_B_DQSN2 M_B_DQSP3 M_B_DQSN3 M_B_DQSP4 M_B_DQSN4 M_B_DQSP5 M_B_DQSN5 M_B_DQSP6 M_B_DQSN6 M_B_DQSP7 M_B_DQSN7 C15 B15 E18 D18 E22 D22 B26 A26 AG24 AG25 AG21 AF21 AG17 AG18 AH14 AG14 M_B_CLKP0 M_B_CLKN0 M_B_CLKP1 M_B_CLKN1 R26 R27 P27 P28 M_B_CKE0 M_B_CKE1 J26 J27 M_B_ODT0 M_B_ODT1 W27 Y28 M_B_CS#0 M_B_CS#1 V25 Y27 M_B_RAS# M_B_CAS# M_B_WE# V24 V27 V28 J25 M_B_RST# M_B_EVENT# T25 04 M_B_DQ[0..63] [13] U1B [13] M_B_A[15:0] MEMORY CHANNEL A MA_ADD0 MA_DATA0 MA_ADD1 MA_DATA1 MA_ADD2 MA_DATA2 MA_ADD3 MA_DATA3 MA_ADD4 MA_DATA4 MA_ADD5 MA_DATA5 MA_ADD6 MA_DATA6 MA_ADD7 MA_DATA7 MA_ADD8 MA_ADD9 MA_DATA8 MA_ADD10 MA_DATA9 MA_ADD11 MA_DATA10 MA_ADD12 MA_DATA11 MA_ADD13 MA_DATA12 MA_ADD14 MA_DATA13 MA_ADD15 MA_DATA14 MA_DATA15 MA_BANK0 MA_BANK1 MA_DATA16 MA_BANK2 MA_DATA17 MA_DATA18 MA_DM0 MA_DATA19 MA_DM1 MA_DATA20 MA_DM2 MA_DATA21 MA_DM3 MA_DATA22 MA_DM4 MA_DATA23 MA_DM5 MA_DM6 MA_DATA24 MA_DM7 MA_DATA25 MA_DATA26 MA_DQS_H0 MA_DATA27 MA_DQS_L0 MA_DATA28 MA_DQS_H1 MA_DATA29 MA_DQS_L1 MA_DATA30 MA_DQS_H2 MA_DATA31 MA_DQS_L2 MA_DQS_H3 MA_DATA32 MA_DQS_L3 MA_DATA33 MA_DQS_H4 MA_DATA34 MA_DQS_L4 MA_DATA35 MA_DQS_H5 MA_DATA36 MA_DQS_L5 MA_DATA37 MA_DQS_H6 MA_DATA38 MA_DQS_L6 MA_DATA39 MA_DQS_H7 MA_DQS_L7 MA_DATA40 MA_DATA41 MA_CLK_H0 MA_DATA42 MA_CLK_L0 MA_DATA43 MA_CLK_H1 MA_DATA44 MA_CLK_L1 MA_DATA45 MA_DATA46 MA_CKE0 MA_DATA47 MA_CKE1 MA_DATA48 MA_ODT0 MA_DATA49 MA_ODT1 MA_DATA50 MA_DATA51 MA_CS_L0 MA_DATA52 MA_CS_L1 MA_DATA53 MA_DATA54 MA_RAS_L MA_DATA55 MA_CAS_L MA_WE_L MA_DATA56 MA_DATA57 MA_RESET_L MA_DATA58 MA_EVENT_L MA_DATA59 MA_DATA60 M_VREF MA_DATA61 MA_DATA62 M_ZVDDIO MA_DATA63 1 MEMORY CHANNEL B MB_ADD0 MB_DATA0 MB_ADD1 MB_DATA1 MB_ADD2 MB_DATA2 MB_ADD3 MB_DATA3 MB_ADD4 MB_DATA4 MB_ADD5 MB_DATA5 MB_ADD6 MB_DATA6 MB_ADD7 MB_DATA7 MB_ADD8 MB_ADD9 MB_DATA8 MB_ADD10 MB_DATA9 MB_ADD11 MB_DATA10 MB_ADD12 MB_DATA11 MB_ADD13 MB_DATA12 MB_ADD14 MB_DATA13 MB_ADD15 MB_DATA14 MB_DATA15 MB_BANK0 MB_BANK1 MB_DATA16 MB_BANK2 MB_DATA17 MB_DATA18 MB_DM0 MB_DATA19 MB_DM1 MB_DATA20 MB_DM2 MB_DATA21 MB_DM3 MB_DATA22 MB_DM4 MB_DATA23 MB_DM5 MB_DM6 MB_DATA24 MB_DM7 MB_DATA25 MB_DATA26 MB_DQS_H0 MB_DATA27 MB_DQS_L0 MB_DATA28 MB_DQS_H1 MB_DATA29 MB_DQS_L1 MB_DATA30 MB_DQS_H2 MB_DATA31 MB_DQS_L2 MB_DQS_H3 MB_DATA32 MB_DQS_L3 MB_DATA33 MB_DQS_H4 MB_DATA34 MB_DQS_L4 MB_DATA35 MB_DQS_H5 MB_DATA36 MB_DQS_L5 MB_DATA37 MB_DQS_H6 MB_DATA38 MB_DQS_L6 MB_DATA39 MB_DQS_H7 MB_DQS_L7 MB_DATA40 MB_DATA41 MB_CLK_H0 MB_DATA42 MB_CLK_L0 MB_DATA43 MB_CLK_H1 MB_DATA44 MB_CLK_L1 MB_DATA45 MB_DATA46 MB_CKE0 MB_DATA47 MB_CKE1 MB_DATA48 MB_ODT0 MB_DATA49 MB_ODT1 MB_DATA50 MB_DATA51 MB_CS_L0 MB_DATA52 MB_CS_L1 MB_DATA53 MB_DATA54 MB_RAS_L MB_DATA55 MB_CAS_L MB_WE_L MB_DATA56 MB_DATA57 MB_RESET_L MB_DATA58 MB_EVENT_L MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63 A14 B14 D16 E16 B13 C13 B16 A16 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 C17 B18 B20 A20 E17 B17 B19 C19 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 C21 B22 C23 A24 D20 B21 E23 B23 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 E24 B25 B27 D28 B24 D24 D26 C27 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 AG26 AH26 AF23 AG23 AG27 AF27 AH24 AE24 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 AE22 AH22 AE20 AH20 AD23 AD22 AD21 AD20 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 AF19 AE18 AE16 AH16 AG20 AG19 AF17 AD16 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 AG15 AD15 AG13 AD13 AG16 AF15 AE14 AF13 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 D C B Trinity APU Trinity APU Soldermask openings for all bottom side vias/TPs under FS1 +1.5VSUS R544 1K/F_4 +MEMVREF_CPU C48 A 0.1U/10V_4X R545 1K/F_4 C54 0.47U/6.3V_4X C49 1000P/50V_4X A Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev 1A APU 2/4(DDR3 MEM I/F) Date: 5 4 3 2 Tuesday, February 14, 2012 Sheet 1 4 of 47 4 3 2 1 INT_HDMI_AUXP INT_HDMI_AUXN U1C 0.1U/10V_4X 0.1U/10V_4X APU_DP_TXP0_C APU_DP_TXN0_C H5 H4 APU_DP_TXP1 APU_DP_TXN1 C734 C735 0.1U/10V_4X 0.1U/10V_4X APU_DP_TXP1_C APU_DP_TXN1_C H2 H1 APU_DP_TXP2 APU_DP_TXN2 C736 C737 0.1U/10V_4X 0.1U/10V_4X APU_DP_TXP2_C APU_DP_TXN2_C G3 G2 APU_DP_TXP3 APU_DP_TXN3 C738 C739 0.1U/10V_4X 0.1U/10V_4X APU_DP_TXP3_C APU_DP_TXN3_C F2 F1 [26] INT_LVDS_TXP0 [26] INT_LVDS_TXN0 INT_LVDS_TXP0 INT_LVDS_TXN0 C741 C742 0.1U/10V_4X 0.1U/10V_4X INT_LVDS_TXP0_C INT_LVDS_TXN0_C L9 L8 [26] INT_LVDS_TXP1 [26] INT_LVDS_TXN1 INT_LVDS_TXP1 INT_LVDS_TXN1 C743 C744 0.1U/10V_4X 0.1U/10V_4X INT_LVDS_TXP1_C INT_LVDS_TXN1_C L5 L6 D DP1 Hudson-M3 VGA output [9] APU_DP_TXP1 [9] APU_DP_TXN1 [9] APU_DP_TXP2 [9] APU_DP_TXN2 [9] APU_DP_TXP3 [9] APU_DP_TXN3 K8 K7 J6 J5 Note: CLK_APU_HCLKP/N is 100MHZ SSC [8] CLK_APU_HCLKP [8] CLK_APU_HCLKN Note: CLK_DP_NSSCP/N is 100MHZ non-SSC +1.5VSUS [8] CLK_DP_NSSCP [8] CLK_DP_NSSCN +1.5VSUS R379 300_4 R385 300_4 AE11 AD11 CLK_DP_NSSCP CLK_DP_NSSCN AB11 AA11 B3 A3 SVC SVD APU_SVT [42] APU_SVT R378 +1.5VSUS *1K/F_4 C3 APU_SIC APU_SID AG12 AH12 AF10 AB12 APU_RST# APU_PWRGD [8] APU_RST# [8] APU_PWRGD C CLK_APU_HCLKP CLK_APU_HCLKN D3A C749 C750 150P/50V_4N 150P/50V_4N R389 +1.5VSUS APU_PROCHOT#_VDDIO APU_THERMTRIP#_VDDIO APU_ALERT 1K/F_4 APU_VDD_RUN_FB_L APU_VDDP_FB_H APU_VDDNB_RUN_FB_H APU_VDDIO_RUN_FB_H APU_VDD_RUN_FB_H APU_VDDR_FB_H APU_VDD_RUN_FB_L APU_VDDP_FB_H APU_VDDNB_RUN_FB_H APU_VDDIO_RUN_FB_H APU_VDD_RUN_FB_H APU_VDDR_FB_H H10 J10 F10 G10 F9 G9 H9 APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ# [3] APU_TDI [3] APU_TDO [3] APU_TCK [3] APU_TMS [3] APU_TRST# [3] APU_DBRDY [3] APU_DBREQ# [42] [40] [42] [39] [42] [40] AC10 AE12 AF12 R394 0_4 VSS_SENSE +1.5VSUS B4 C5 A4 A5 C4 B5 DP3_AUXP DP3_AUXN DP1_TXP0 DP1_TXN0 DP1_TXP1 DP1_TXN1 DP1_TXP2 DP1_TXN2 DP1_TXP3 DP1_TXN3 DP4_AUXP DP4_AUXN DP5_AUXP DP5_AUXN DP2_TXP0 DP2_TXN0 DP0_HPD DP1_HPD DP2_HPD DP3_HPD DP4_HPD DP5_HPD DP_BLON DP_DIGON DP_VARY_BL DP2_TXP1 DP2_TXN1 DP_AUX_ZVSS DP2_TXP2 DP2_TXN2 DP2_TXP3 DP2_TXN3 CLKIN_H CLKIN_L DISP_CLKIN_H DISP_CLKIN_L TEST6 TEST9 TEST10 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 TEST24 TEST25_H TEST25_L TEST28_H TEST28_L TEST30_H TEST30_L TEST31 TEST32_H TEST32_L TEST35 SVC SVD SVT SIC SID RESET_L PWROK PROCHOT_L THERMTRIP_L ALERT_L TDI TDO TCK TMS TRST_L DBRDY DBREQ_L VSS_SENSE VDDP_SENSE VDDNB_SENSE VDDIO_SENSE VDD_SENSE VDDR_SENSE FS1R2 DMAACTIVE_L TEST4 TEST5 D5 D6 INT_LVDS_AUXP_C INT_LVDS_AUXN_C C747 C748 0.1U/10V_4X 0.1U/10V_4X INT_LVDS_AUXP INT_LVDS_AUXN INT_HDMI_AUXP INT_HDMI_AUXN HDMI FCH VGA INT_LVDS_AUXP [26] INT_LVDS_AUXN [26] LVDS F5 F6 D3 E3 D7 E7 F7 G7 INT_HDMI_HPD INT_VGA_HPD_Q INT_LVDS_HPD_Q INT_HDMI_HPD [27] C6 B6 A6 APU_VARY_BL C1 DP_AUX_ZVSS R539 AD12 M18 N18 F11 G11 H11 J11 F12 G12 J12 H12 AE10 AD10 L10 M10 P19 R19 K22 T19 N19 AA12 APU_VARY_BL 1 1 Q71 APU_THERMTRIP#_VDDIO 1 *100K_4 *100K_4 D LVDS +3V 5 Q83B TP25 TP26 TP27 TP28 TP29 TP30 W10 AC12 P18 R18 TP21 TP22 Y10 AA10 Y12 K21 [26] FCH_VGA_HPD [9] R513 10K_4 2N7002KDW_115MA 5 Q82B R536 1K_4 2N7002KDW_115MA 2 FCH_VGA_HPD C Q82A DMAACTIVE_L DMAACTIVE_L [8] DMAACTIVE_L controls entry and exit from the sleep and power states +1.5VSUS APU_TEST9 R504 300_4 R514 100K_4 +1.2V_VDDPR APU_TEST25_L +1.5VSUS M_TEST INT_LVDS_HPD R515 100K_4 INT_VGA_HPD_Q FS1R1 signals is for detect CPU TYPE and protect it. FS1R1 CPU this pin is N.C FS1R2 CPU this pin is LOW can remove it at MP INT_LVDS_HPD +5V R512 1K_4 +1.5VSUS FS1R2 [42] CPU_THERMDA CPU_THERMDC 2 APU_TEST18_PLLTEST1 [3] APU_TEST19_PLLTEST0 [3] TP31 TP32 TP33 TP34 TP35 TP36 TP41 FS1R2 2N7002KDW_115MA Q83A +3V M_TEST APU_TEST35 R516 10K_4 2N7002KDW_115MA 150/F_4 APU_TEST9 APU_TEST10 APU_TEST14_BP0 APU_TEST15_BP1 APU_TEST16_BP2 APU_TEST17_BP3 APU_TEST18_PLLTEST1 APU_TEST19_PLLTEST0 APU_TEST20_SCANCLK2 APU_TEST24_SCANCLK1 APU_TEST25_H APU_TEST25_L APU_TEST28_H APU_TEST28_L R502 *39.2/F_4 R469 510/F_4 R518 *0_4 APU_TEST18_PLLTEST1 APU_TEST19_PLLTEST0 APU_TEST20_SCANCLK2 APU_TEST24_SCANCLK1 R553 R554 R555 R556 1K_4 1K_4 1K_4 1K_4 APU_TEST25_H R476 510/F_4 APU_TEST35 BOOT VOLTAGE M_TEST CONNECTION TBD R505 *300_4 SVC SVD 0 0 1.1 1.1 0 1 1.0 1.2 1 0 0.9 1.0 1 1 0.8 0.8 Note: To override VID,Remove Rd, Re, Rf, install Rc set VID via SVC & SVD option RES. FS1R2 R537 10K_4 100K_4 +1.5VSUS +3V_S5 B2A R525 *1K_4 R532 *1K_4 R540 *2.2K_4 VFIX_+VDD =VCC/GND VFIX_+VDD =OPEN B Q70 METR3904-G_200MA 2 3 INT_LVDS_AUXP R534 INT_LVDS_AUXN R535 FCH VGA +3V +5V [26] R492 1K_4 2 APU_THERMTRIP# [7] APU_THERMTRIP# *100K_4 INT_LVDS_HPD_Q TP20 TP23 2 R493 1K_4 *100K_4 +3V C3A FDV301N_200MA R494 10K_4 B APU_DP_AUXP R531 APU_DP_AUXN R533 R519 1K_4 R503 39.2/F_4 R405 R530 1.8K_4 R524 1.8K_4 G5 G6 3 FCH_PWRGD +1.5VSUS INT_LVDS_AUXP_C INT_LVDS_AUXN_C R522 1.8K_4 Q69 [7,11] FCH_PWRGD R529 1.8K_4 R528 *1.8K_4 LVDS Trinity APU TP50 TP51 R526 *1.8K_4 APU_DP_AUXP [9] APU_DP_AUXN [9] E5 E6 AMD internal test only RSVD_1 RSVD_2 RSVD_3 RSVD_4 [27] [27] 6 C732 C733 DP0_TXP3 DP0_TXN3 APU_DP_AUXP APU_DP_AUXN 1 J3 J2 0.1U/10V_4X 0.1U/10V_4X 6 INT_HDMI_TXCP_C INT_HDMI_TXCN_C C745 C746 1 0.1U/10V_4X 0.1U/10V_4X APU_DP_AUXP_C APU_DP_AUXN_C 3 C730 C731 DP2_AUXP DP2_AUXN INT_HDMI_AUXP INT_HDMI_AUXN E1 E2 4 INT_HDMI_TXCP INT_HDMI_TXCN DP0_TXP2 DP0_TXN2 05 HDMI D1 D2 4 INT_HDMI_TXDP0_C K2 INT_HDMI_TXDN0_C K1 DISPLAY PORT MISC. 0.1U/10V_4X 0.1U/10V_4X DP1_AUXP DP1_AUXN TEST C728 C729 DP0_TXP1 DP0_TXN1 RSVD INT_HDMI_TXDP0 INT_HDMI_TXDN0 ANALOG/DISPLAY/MISC DP0_TXP0 DP0_AUXP DP0_TXN0 DP0_AUXN DISPLAY PORT 0 INT_HDMI_TXDP1_C K5 INT_HDMI_TXDN1_C K4 DISPLAY PORT 1 0.1U/10V_4X 0.1U/10V_4X DISPLAY PORT 2 C726 C727 APU_DP_TXP0 APU_DP_TXN0 [9] APU_DP_TXP0 [9] APU_DP_TXN0 DP2 LVDS INT_HDMI_TXDP1 INT_HDMI_TXDN1 CLK [27] INT_HDMI_TXCP [27] INT_HDMI_TXCN INT_HDMI_TXDP2_C L3 INT_HDMI_TXDN2_C L2 SER. [27] INT_HDMI_TXDP0 [27] INT_HDMI_TXDN0 0.1U/10V_4X 0.1U/10V_4X CTRL DP0 HDMI C372 C725 JTAG [27] INT_HDMI_TXDP1 [27] INT_HDMI_TXDN1 INT_HDMI_TXDP2 INT_HDMI_TXDN2 SENSE [27] INT_HDMI_TXDP2 [27] INT_HDMI_TXDN2 FCH VGA APU_DP_AUXP_C APU_DP_AUXN_C 3 5 3 SYS_SHDN# SYS_SHDN# [15,38] METR3904-G_200MA +1.5VSUS SVC R517 Rd SVD R521 Re APU_PWRGD R523 Rf 0_4 APU_SVC APU_SVC [42] 0_4 APU_SVD APU_SVD [42] 0_4 APU_PWRGD_SVID_REG APU_PWRGD have pull up 300ohm to +1.5V on page 4 R520 *220_4 R527 *220_4 R541 *220_4 Ra Rb Rc C724 *0.1U/10V_4X APU_PWRGD_SVID_REG [42] for normal operation open Ra , Rb,Rc R495 1K_4 +1.5VSUS +1.5VSUS Fan APU_PROCHOT#_VDDIO R498 *0_4 +1.5VSUS +1.5VSUS R508 150_4 A Debug only R475 DEBUG@300_4 R474 DEBUG@300_4 1 2 APU_PWRGD 3 A1 Y1 GND VCC A2 Y2 6 APU_RST_L_BUF 5 +3V 4 APU_PWROK_BUF APU_RST_L_BUF VCC [3] SET GND C533 0.1U/10V_4X 4 HYST [36] 2ND_MBCLK 3 2ND_MBCLK 1 R499 32.4K/F_4 U17 5 U23 APU_RST# R511 2K/F_4 CPU Thermal sensor / MB Local TEMP D3A +3VPCU C3A H_PROCHOT# OT# 1 [36] 2ND_MBDATA 2 3 THER_SHD# R506 *SHORT_4 1 3 Q12 METR3904-G_200MA 1 A APU_SID 2 D43 RB500V-40_100MA G708T1U APU_PWROK_BUF [3] Quanta Computer Inc. Rset(Kohm)=0.0012T*T-0.9308T+96.147,Shut down on 76dgree Hysteresis is 30C *DEBUG@74LVC2G07 C722 [email protected]/10V_4X PROJECT : BY6/BY6D Size 4 3 Document Number Rev 1A APU 3/4(DISPLAY/MISC) Date: 5 R507 1K/F_4 APU_SIC 2 1 SYS_SHDN# R509 1K/F_4 Q11 METR3904-G_200MA D44 RB500V-40_100MA 2ND_MBDATA D3A R510 2K/F_4 2 CORE_PWM_PROCHOT# 2 FCH [8,36] APU_PROCHOT#_VDDIO FCH Fan APU Core Power[42] CORE_PWM_PROCHOT# EC [8,36] H_PROCHOT# 2 Sheet Tuesday, February 14, 2012 1 5 of 47 5 4 3 2 APU POWER TABLE 1 NET NAME VDD +VDD_CORE VDDNB +VDDNB_CORE VDDIO +1.5VSUS +1.5V VDDP +1.2V_VDDP +1.2V VDDR +1.2V_VDDR +1.2V VDDA +2.5V_VDDA +2.5V VOLTAGE EMI +1.1V C58 D ?? +VDD_CORE F8 H6 J1 J14 P6 P10 J16 J18 J9 K19 K3 K17 M3 K6 V10 V18 V3 F3 L18 V6 W1 T18 Y14 AA1 AB6 AC1 R1 P3 K10 H3 M19 +VDDNB_CORE C323 ESD@39P/50V_4N ESD@39P/50V_4N C69 C63 C70 22U/6.3V_6X 22U/6.3V_6X 10U/6.3V_8X C82 C83 Close to C80 and C82 C80 C81 0.22U/10V_4X 0.22U/10V_4X 180P/50V_4N C84 180P/50V_4N 180P/50V_4N VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55 VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 R11 T10 H8 G1 U11 W11 W13 W15 W17 W19 AB3 AD3 AD6 AE1 L1 Y6 M6 N11 N1 T3 T6 U19 U1 Y16 Y18 Y3 D4 F4 AF6 AF3 L11 36A Maximum IDDspike 50A C8 D10 B8 B12 C9 A9 A10 A8 A11 E10 E11 C10 C85 C86 C87 22U/6.3V_6X 22U/6.3V_6X 180P/50V_4N VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 VDDNB_6 VDDNB_7 VDDNB_8 VDDNB_9 VDDNB_10 VDDNB_11 VDDNB_12 VDDNB_13 VDDNB_14 VDDNB_15 VDDNB_16 VDDNB_17 VDDNB_18 VDDNB_19 VDDNB_20 VDDNB_21 VDDNB_22 VDDNB_23 VDDNB_CAP VDDNB_CAP VDDIO=4.6A (Up to DDR3_1600 @ 1.5V) C93 C94 C95 C96 C97 0.22U/10V_4X 0.22U/10V_4X 0.22U/10V_4X 0.22U/10V_4X 0.22U/10V_4X 0.22U/10V_4X C137 C106 180P/50V_4N 180P/50V_4N B D3A R11 +1.2V_VDDP C73 C61 C65 C66 C129 C141 22U/6.3V_6X 22U/6.3V_6X 22U/6.3V_6X 22U/6.3V_6X 22U/6.3V_6X ESD@39P/50V_4N ESD@39P/50V_4N C67 C74 C75 C62 C68 22U/6.3V_6X 22U/6.3V_6X 22U/6.3V_6X 22U/6.3V_6X 22U/6.3V_6X C76 C77 C71 C72 C78 C79 C136 0.22U/10V_4X 0.22U/10V_4X 180P/50V_4N 180P/50V_4N 0.01U/25V_4X 0.01U/25V_4X 0.01U/25V_4X C129 and C141 close to C61 and C65 25A Maximum IDDNBspike 33A +VDDNB_CORE VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDIO_5 VDDIO_6 VDDIO_7 VDDIO_8 VDDIO_9 VDDIO_10 VDDIO_11 VDDIO_12 VDDIO_13 VDDIO_14 VDDIO_15 VDDIO_16 VDDIO_17 VDDIO_18 VDDP_A + VDDP_B = 5A C108 C109 AH6 AH5 AH4 AH3 AH7 C110 22U/6.3V_6X 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X C115 C116 C117 0.22U/10V_4X 0.22U/10V_4X 180P/50V_4N 180P/50V_4N L1 B2A A +1.5VSUS +VDDNB_CAP C88 C89 C90 C91 0.22U/10V_4X 0.22U/10V_4X 180P/50V_4N 180P/50V_4N VDDR VDDR VDDR VDDR VDDA T23 T26 U22 U25 U28 Y26 T20 R28 R25 R22 V20 V23 V26 W22 W25 W28 Y24 G28 AG10 AH8 AH9 AH10 C98 C99 C100 C101 C102 C103 C104 C105 22U/6.3V_6X 22U/6.3V_6X 22U/6.3V_6X 22U/6.3V_6X 4.7U/6.3V_6X 4.7U/6.3V_6X 4.7U/6.3V_6X 4.7U/6.3V_6X VDDR = 3.3A (Up to DDR3_1600 @ 1.2V) +1.2V_VDDR R12 +1.2V_VDDPR *SHORT_8 J20 L4 R7 W18 A15 AB17 AC22 AE21 AF24 AH23 AH25 B7 C14 C16 C2 C20 C22 C24 C26 C28 D13 D15 D17 D19 D23 D25 D27 E4 E9 F14 F16 F18 F20 F22 F26 F28 G13 G15 G17 G19 G21 G23 G25 G4 J22 J24 J4 J7 K11 K14 K9 AC11 L19 L7 M11 AF11 V19 V9 W16 W4 W7 Y11 Y20 Y22 Y9 A17 A13 K16 F24 G8 H7 J8 D3A C111 C112 C113 10U/6.3V_8X 10U/6.3V_8X 10U/6.3V_8X C118 C119 C120 C121 C122 0.22U/10V_4X 0.22U/10V_4X 1000P/50V_4X 180P/50V_4N 180P/50V_4N VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_68 VSS_67 VSS_69 VSS_70 VSS_71 VSS_72 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 A19 A21 A23 A25 A7 AA4 AA7 AB13 AB15 AB19 AB21 AB23 AB25 AB27 AB9 AC14 AC16 AC18 AC20 AC24 AC26 AC28 AC4 AC7 AD9 AE13 AE15 AE17 M9 N10 N4 N7 R10 R4 T11 T9 U10 U18 U4 U7 V11 AE19 AE23 AE25 AE27 AE4 AE7 AF14 AF16 AF18 AF20 AF22 AF26 AF28 AF9 AG4 AG7 AH13 AH15 AH17 AH19 AH21 P9 C18 D21 W14 P11 C7 E8 K18 W12 D C B Trinity APU Trinity APU VDDA = 0.75A +2.5V_VDDA VDDIO_19 VDDIO_20 VDDIO_21 VDDIO_22 VDDIO_23 VDDIO_24 VDDIO_25 VDDIO_26 VDDIO_27 VDDIO_28 VDDIO_29 VDDIO_30 VDDIO_31 VDDIO_32 VDDIO_33 VDDIO_34 VDDIO_35 VDDIO_36 VDDP VDDP VDDP VDDP VDDP AB10 C114 DECOUPLING between PROCESSOR and DIMMs Across VDDIO and VSS split +1.5VSUS H26 K20 J28 K23 K26 L22 L25 L28 M20 M23 M26 N22 N25 N28 P20 P23 P26 AA28 *SHORT_8 C107 U1E K13 K12 +1.5VSUS C92 +1.2V_VDDPR C11 C12 D9 D8 D12 D11 B11 A12 B10 E12 B9 C60 D3A C64 +VDDNB_CORE +VDDNB_CAP C C59 470P/50V_4X 470P/50V_4X 470P/50V_4X U1D +VDD_CORE D3A C281 06 +VDD_CORE PIN NAME D3A HCB1608KF-221T20_2A C123 C124 C125 C573 4.7U/6.3V_6X 0.22U/10V_4X 3300P/50V_4X ESD@39P/50V_4N A Close to L1 Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev 1A APU 4/4(POWER/GND) Date: 5 4 3 2 Tuesday, February 14, 2012 Sheet 1 6 of 47 5 4 3 2 1 07 +3V_S5 NC,no install by default 0_4 PWR_BTN# FCH_TEST0 FCH_TEST1 FCH_TEST2 +3V R272 2.2K_4 SMB_RUN_CLK R270 2.2K_4 SMB_RUN_DAT R271 For Dimm [36] LPCPD# SYS_RST# PCIE_WAKE# GEVENT20# APU_THERMTRIP# R288 10K/F_4 WD_PWRGD [28,30] PCIE_WAKE# T80 [5] APU_THERMTRIP# +3V_S5 R396 2.2K_4 SMB_LAN_CLK R384 2.2K_4 SMB_LAN_DAT R698 *2.2K_4 VGA_PD +3V C379 For Lan&WiFi FCH_PCIE_LAN_CLKREQ# BOARD_ID8 BOARD_ID9 TRAVIS_EN# PCBEEP SMB_RUN_CLK SMB_RUN_DAT SMB_LAN_CLK SMB_LAN_DAT GPIO62 FCH_PCIE_WLAN_CLKREQ# [29] PCBEEP [12,13,35] SMB_RUN_CLK [12,13,35] SMB_RUN_DAT [28,30] SMB_LAN_CLK [28,30] SMB_LAN_DAT T34 [30] FCH_PCIE_WLAN_CLKREQ# APU_THERMTRIP# USB_SC_OC# USB_NORMAL_OC# FCH_JTAG_TCK 4.7K_4 10K_4 10K_4 10K_4 GPIO51 VGA_PD T29 [10] VGA_PD VGA_PD for power control U2 RSMRST# 33P/50V_4N [28] FCH_PCIE_LAN_CLKREQ# [9] BOARD_ID8 [9] BOARD_ID9 [26] TRAVIS_EN# +3V_S5 R685 R368 R374 R377 GEVENT23# T100 GPIO65 10K_4 EC_A20GATE EC_KBRST# EC_EXT_SCI# [36] EC_A20GATE [36] EC_KBRST# [36] EC_EXT_SCI# SPI_HOLD# [9] SPI_HOLD# C GPIO65 Integrated 8.2-kȍ PU +3V_S5 R407 R375 PCIE_WAKE# PWR_BTN# 10K_4 2.2K_4 B2A USB_SC_OC# USB_NORMAL_OC# [25,36] USB_SC_OC# [25,36] USB_NORMAL_OC# HDaudio interface are +3V_S5 Note:LLB#, WAKE# and PWR_BTN need pull up to +3VPCU only if S5+ mode is supported D3A [36] RSMRST_GATE# *SHORT_4 0_4 0_4 PCIE_RST2#/GEVENT4# RI#/GEVENT22# SPI_CS3#/GBE_STAT1/GEVENT21# SLP_S3# SLP_S5# PWR_BTN# PWR_GOOD USBCLK/14M_25M_48M_OSC USB_RCOMP HUDSON-M3 Part 4 of 5 TEST0 TEST1/TMS TEST2 GA20IN/GEVENT0# KBRST#/GEVENT1# PME#/GEVENT3# LPC_SMI#/GEVENT23# LPC_PD#/GEVENT5# SYS_RESET#/GEVENT19# WAKE#/GEVENT8# IR_RX1/GEVENT20# THRMTRIP#/SMBALERT#/GEVENT2# WD_PWRGD USB_FSD1P/GPIO186 USB_FSD1N USB_FSD0P/GPIO185 USB_FSD0N 5 4 3 2 1 RSMRST# 6 7 8 9 10 R734 R432 22K_4 ACZ_BCLK_R ACZ_SDOUT_R ACZ_SDIN0 ACZ_SDIN1 ACZ_SDIN2_R ACZ_SDIN3_R ACZ_SYNC_R ACZ_RST#_R AB3 AB1 AA2 Y5 Y3 Y1 AD6 AE4 *10KX8 K19 J19 J21 [9,35] BOARD_ID10 T42 2 1 PE_GPIO0 PE_GPIO1 [24] PE_GPIO0 [24,44] PE_GPIO1 R662 10K_4 G2 USB_HSD12P USB_HSD12N USB_HSD11P USB_HSD11N USB_HSD10P USB_HSD10N RSMRST# USB_HSD9P USB_HSD9N CLK_REQ4#/SATA_IS0#/GPIO64 CLK_REQ3#/SATA_IS1#/GPIO63 SMARTVOLT1/SATA_IS2#/GPIO50 CLK_REQ0#/SATA_IS3#/GPIO60 SATA_IS4#/FANOUT3/GPIO55 SATA_IS5#/FANIN3/GPIO59 SPKR/GPIO66 SCL0/GPIO43 SDA0/GPIO47 SCL1/GPIO227 SDA1/GPIO228 CLK_REQ2#/FANIN4/GPIO62 CLK_REQ1#/FANOUT4/GPIO61 IR_LED#/LLB#/GPIO184 SMARTVOLT2/SHUTDOWN#/GPIO51 DDR3_RST#/GEVENT7#/VGA_PD GBE_LED0/GPIO183 SPI_HOLD#/GBE_LED1/GEVENT9# GBE_LED2/GEVENT10# GBE_STAT0/GEVENT11# CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD8P USB_HSD8N USB_HSD7P USB_HSD7N USB_HSD6P USB_HSD6N USB_HSD5P USB_HSD5N USB_HSD4P USB_HSD4N USB_HSD3P USB_HSD3N USB_HSD2P USB_HSD2N USB_HSD1P USB_HSD1N BLINK/USB_OC7#/GEVENT18# USB_OC6#/IR_TX1/GEVENT6# USB_OC5#/IR_TX0/GEVENT17# USB_OC4#/IR_RX0/GEVENT16# USB_OC3#/AC_PRES/TDO/GEVENT15# USB_OC2#/TCK/GEVENT14# USB_OC1#/TDI/GEVENT13# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_HSD0P USB_HSD0N USBSS_CALRP USBSS_CALRN AZ_BITCLK AZ_SDOUT AZ_SDIN0/GPIO167 AZ_SDIN1/GPIO168 AZ_SDIN2/GPIO169 AZ_SDIN3/GPIO170 AZ_SYNC AZ_RST# USB_SS_RX3P USB_SS_RX3N USB_SS_TX2P USB_SS_TX2N USB_SS_RX2P USB_SS_RX2N PS2_DAT/SDA4/GPIO187 PS2_CLK/CEC/SCL4/GPIO188 SPI_CS2#/GBE_STAT2/GPIO166 SYS_RST# B2A R329 *EV@10K_4 R354 *EV@10K_4 *SHORT_PAD KSO_5 +3V_S5 +3V_S5 +3V_S5 Provided test points from checklist R286 *10K_4 G5 2 1 KSO_5 *SHORT_PAD D21 C20 D23 C22 F21 E20 F20 A22 E18 A20 J18 H18 G18 B21 K18 D19 A18 C18 B19 B17 A24 D17 USB_SS_TX1P USB_SS_TX1N USB_SS_RX1P USB_SS_RX1N +3V_S5 B USB_HSD13P USB_HSD13N USB_SS_TX3P USB_SS_TX3N GEVENT12# ~18# are +3V_S5 R430 R711 R710 AG24 AE24 AE26 AF22 AH17 AG18 AF24 AD26 AD25 T7 R7 AG25 AG22 J2 AG26 V8 W8 Y6 V10 AA8 AF25 M7 R8 T1 P6 F5 P5 J7 T8 FCH_BLINK GEVENT6# GEVENT17# GEVENT16# FCH_JTAG_TDO FCH_JTAG_TCK FCH_JTAG_TDI FCH_JTAG_RST# T81 T79 T83 T86 T87 T9 T10 V9 AE22 AG19 R9 C26 T5 U4 K1 V7 R10 AF19 U3A USB MISC D AB6 R2 W7 T3 W2 J4 N7 USB 2.0 FCH_TEST2 *2.2K_4 APU_MEMHOT# GEVENT22# GEVENT21# SLP_S3# SLP_S5# DNBSWON# R682 FCH_PWRGD T85 T84 T77 [24,36] SLP_S3# [36] SLP_S5# [36] DNBSWON# [5,11] FCH_PWRGD USB 3.0 R344 remove pull hi ( chip internal have pull hi ) ACPI / WAKE UP EVENTS USB 1.1 FCH_TEST1 GPIO FCH_TEST0 *2.2K_4 USB OC *2.2K_4 R382 HD AUDIO R383 PS2KB_DAT/GPIO189 PS2KB_CLK/GPIO190 PS2M_DAT/GPIO191 PS2M_CLK/GPIO192 USB_SS_TX0P USB_SS_TX0N USB_SS_RX0P USB_SS_RX0N KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217 KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/XDB0/GPIO223 KSO_15/XDB1/GPIO224 KSO_16/XDB2/GPIO225 KSO_17/XDB3/GPIO226 SCL2/GPIO193 SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196 EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 EC_PWM3/EC_TIMER3/GPIO200 KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208 EMBEDDED CTRL G8 B9 USB_RCOMP_SB R647 11.8K/F_6 H1 H3 T157 T156 H6 H5 D Note: USB P/N pairs with trace lengths up to 10" T159 T158 H10 G10 K10 J12 HUB3 G12 F12 USBP11+ USBP11- USBP11+ [25] USBP11- [25] Reserve USB2.0/3.0 option K12 K13 USBP10+ USBP10- USBP10+ [25] USBP10- [25] USB3.0 S&C C10 A10 USBP7+ USBP7- USBP7+ [30] USBP7- [30] WLAN H9 G9 USBP6+_LCD USBP6-_LCD USBP6+_LCD [32] USBP6-_LCD [32] CCD on LVDS A8 C8 USBP5+ USBP5- USBP5+ [31] USBP5- [31] Card Reader B11 D11 E10 F10 HUB2 F8 E8 C6 A6 C5 A5 C USBP2+ USBP2- HUB1 T170 T171 C1 C3 E1 E3 USBP0+ USBP0- C16 A16 USBSS_CALRP USBSS_CALRN USBP0+ [25] USBP0- [25] R646 R642 U3@1K/F_4 U3@1K/F_4 USB2.0 debug port +FCH_VDD_11_SSUSB_S A14 C14 C12 A12 D15 B15 E14 F14 F15 G15 USB3_TXP1 USB3_TXN1 USB3_TXP1 [25] USB3_TXN1 [25] H13 G13 USB3_RXP1 USB3_RXN1 USB3_RXP1 [25] USB3_RXN1 [25] J16 H16 USB3_TXP0 USB3_TXN0 USB3_TXP0 [25] USB3_TXN0 [25] J15 K15 USB3_RXP0 USB3_RXN0 USB3_RXP0 [25] USB3_RXN0 [25] H19 G19 G22 G21 E22 H22 J22 H21 SMB_EC_CLK SMB_EC_DAT R318 R315 MBCLK MBDATA *0_4 *0_4 EC_PWM2 USB3.0 Port 2 USB3.0 S&C B MBCLK [36,37] MBDATA [36,37] GPIO193 ~196 are +3V_S5 EC_PWM2 [11] K21 K22 F22 F24 E24 B23 C24 F18 FCH EC Device I2C_Device(S) Hudson-M3 I2Ce_1(M) I2Cf_2(M) EEPROM I2Ce_2(M) To Azalia R392 33_4 ACZ_SDOUT ACZ_SYNC_R R391 33_4 ACZ_SYNC 33_4 ACZ_BITCLK ACZ_BCLK_R R406 A C571 ACZ_RST#_R R357 33_4 ACZ_SDOUT ACZ_SYNC ACZ_BITCLK [29] ACZ_SDIN0 ALL/S5 APU EC will Conflict with FCH, did not mount R315&R318 ALL I2Cf_3(M) APU S5 [29] [29] *22P/50V_4N ACZ_RST# Battery VGA Thermal I2Ce_3(M) ACZ_SDOUT_R Charger I2Cf_1(M) Lan WLan S5 I2Cf_0(M) Dimm Clk Gen S0 A ACZ_RST# [29] ACZ_SDIN0 [29] Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev 1A FCH 1/5(GPIO/USB/AZ) Date: 5 4 3 2 Tuesday, February 14, 2012 1 Sheet 7 of 47 5 4 3 2 1 08 APU_PCIE_RST# [24,26,28,30] APU_PCIE_RST# R670 33_4 C843 U3E Note: CLK_DP_NSSCP/N is 100MHZ non-SSC AA27 AA26 W27 V27 V26 W26 W24 W23 Note: CLK_PCIE_TRAVISP/N is 100MHZ non-SSC Note: CLK_APU_HCLKP/N is 100MHZ SSC Note: CLK_PCIE_VGAP/N is 100MHZ SSC Note: GPP_CLK(0:8)P/N is 100MHZ SSC capable CLK_CALRN F27 INT_CLK_FCH_SRCP INT_CLK_FCH_SRCN G30 G28 2 4 1 0X2 INT_CLK_DP_NSSCP 3 INT_CLK_DP_NSSCN R26 T26 R274 +1.1V_CKVDD 2K/F_4 TP62 TP63 CLK_DP_NSSCP CLK_DP_NSSCN RP22 CLK_PCIE_TRAVISP CLK_PCIE_TRAVISN RP19 2 4 1 0X2 INT_CLK_PCIE_TRAVISP 3 INT_CLK_PCIE_TRAVISN H33 H31 [5] CLK_APU_HCLKP [5] CLK_APU_HCLKN CLK_APU_HCLKP CLK_APU_HCLKN RP20 2 4 1 0X2 INT_CLK_APU_HCLKP 3 INT_CLK_APU_HCLKN T24 T23 [14] CLK_PCIE_VGAP [14] CLK_PCIE_VGAN CLK_PCIE_VGAP CLK_PCIE_VGAN RP23 2 4 1 0X2 INT_CLK_PCIE_VGAP 3 INT_CLK_PCIE_VGAN [5] CLK_DP_NSSCP [5] CLK_DP_NSSCN [26] CLK_PCIE_TRAVISP [26] CLK_PCIE_TRAVISN J30 K29 H27 H28 CLK_PCIE_WLANP CLK_PCIE_WLANN [30] CLK_PCIE_WLANP [30] CLK_PCIE_WLANN RP12 2 4 1 0X2 INT_CLK_PCIE_WLANP 3 INT_CLK_PCIE_WLANN J27 K26 F33 F31 CLK_PCIE_LANP CLK_PCIE_LANN [28] CLK_PCIE_LANP [28] CLK_PCIE_LANN RP18 2 4 1 0X2 INT_CLK_PCIE_LANP 3 INT_CLK_PCIE_LANN E33 E31 M23 M24 B M27 M26 N25 N26 R23 R24 N27 R27 C380 Card Reader [31] CLK_48M_CARD 15P/50V_4C CLK_48M_CARD R277 22_4 CLK_48M_CARD_R J26 UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N UMI_RX0P UMI_RX0N UMI_RX1P UMI_RX1N UMI_RX2P UMI_RX2N UMI_RX3P UMI_RX3N PCIE_CALRP PCIE_CALRN GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38 PCICLK4/14M_OSC/GPO39 GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N PCIRST# AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9 AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31 CBE0# CBE1# CBE2# CBE3# FRAME# DEVSEL# IRDY# TRDY# PAR STOP# PERR# SERR# REQ0# REQ1#/GPIO40 REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42 GNT0# GNT1#/GPO44 GNT2#/SD_LED/GPO45 GNT3#/CLK_REQ7#/GPIO46 CLKRUN# LOCK# CLK_CALRN PCIE_RCLKP PCIE_RCLKN DISP_CLKP DISP_CLKN DISP2_CLKP DISP2_CLKN APU_CLKP APU_CLKN SLT_GFX_CLKP SLT_GFX_CLKN GPP_CLK0P GPP_CLK0N INTE#/GPIO32 INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35 GPP_CLK1P GPP_CLK1N GPP_CLK4P GPP_CLK4N GPP_CLK5P GPP_CLK5N GPP_CLK6P GPP_CLK6N LPCCLK0 LPCCLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ0# LDRQ1#/CLK_REQ6#/GPIO49 SERIRQ/GPIO48 GPP_CLK7P GPP_CLK7N GPP_CLK8P GPP_CLK8N R715 0_4 25M_X1 C31 25M_X2 1M/F_4 C33 PCI_CLK1 [11] *SHORT_4 PCI_CLK3 *SHORT_4 PCI_CLK4 PCI_CLK3 [11] PCI_CLK4 [11] DMA_ACTIVE# PROCHOT# APU_PG LDT_STP# APU_RST# 25M_X1 32K_X2 25M_X2 22P/50V_4N S5_CORE_EN RTCCLK INTRUDER_ALERT# VDDBT_RTC_G D T135 AJ3 AL5 AG4 AL6 AH3 AJ5 AL1 AN5 AN6 AJ1 AL8 AL3 AM7 AJ6 AK7 AN8 AG9 AM11 AJ10 AL12 AK11 AN12 AG12 AE12 AC12 AE13 AF13 AH13 AH14 AD15 AC15 AE16 AN3 AJ8 AN10 AD12 AG10 AK9 AL10 AF10 AE10 AH1 AM9 AH8 AG15 AG13 AF15 AM17 AD16 AD13 AD21 AK17 AD19 AH9 B2A D37 *RB500V-40_100MA 1 2 R681 *SHORT_6 +3VPCU D27 RTC Circuitry(RTC) +3V_RTC BAT54C-7-F_200MA 20MIL R655 1 +3VRTC 510/F_6 *0_4 1U/10V_4X PCIE_RST#_TRAVIS [26] PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PE_PWRGD HUDSON_MEMHOT# PCI_AD23 [11] PCI_AD24 [11] PCI_AD25 [11] PCI_AD26 [11] PCI_AD27 [11] PE_PWRGD [24,36,44] +VCCRTC_2 C537 +3V R713 2 D38 *RB500V-40_100MA 20MIL 20MIL R680 R428 *2.2K_4 1K/F_4 20MIL C B2A Net GPIO I/O Power Well PE_PWRGD GPIO28 DGPU_PWRGD I +3.3V "0->1" PE_GPIO0 GPIO44 DGPU_RST# O +3.3V "0->1" PE_GPIO1 GPIO45 DGPU_PWREN O +3.3V "0->1" DOS CN21 50273-0027N-001 T40 T39 CLKRUN# CLKRUN# [36] AF18 AE18 AC16 AD18 B25 D25 D27 C28 A26 A29 A31 B27 AE27 AE19 LPC_CLK0_R LPC_CLK1_R G25 E28 E26 G26 F26 DMAACTIVE_L APU_PROCHOT#_VDDIO APU_PWRGD_R R716 APU_STOP# APU_RST# G2 32K_X1 G4 32K_X2 H7 F1 F3 E6 S5_CORE_EN RTC_CLK INTRUDER_ALERT# +3V_RTC NMP@22_4 22_4 R608 R611 LDRQ#0 LDRQ#1 22_4 22_4 T38 T30 0_4 For EMI LPC_CLK0 [11] LPC_CLK1 [11] LAD0 [30,36] LAD1 [30,36] LAD2 [30,36] LAD3 [30,36] LFRAME# [30,36] PCLK_DEBUG C805 *15P/50V_4C PCLK_591 C434 *15P/50V_4C B SERIRQ [36] APU_PWRGD DMAACTIVE_L [5] APU_PROCHOT#_VDDIO [5,36] APU_PWRGD [5] T31 32K_X1 C562 18P/50V_4C Y7 32.768KHZ_10 R390 20M_4 APU_RST# [5] *0.1U/10V_4X 32K_X2 C560 B2A 18P/50V_4C USE GROUND GUARD FOR 32K_X1 AND 32K_X2 R352 20MIL R656 560_4 2 1 Hudson-M3 PCLK_DEBUG [30] PCLK_591 [36] LPC_CLK0 LPC_CLK1 LAD0 LAD1 LAD2 LAD3 LFRAME# SERIRQ C534 R273 1 C381 *SHORT_4 PCI_CLK1 R436 R433 14M_25M_48M_OSC S5 PLUS Y6 25MHZ_30 R434 PCI_CLK3_R PCI_CLK4_R R280 R281 GPP_CLK3P GPP_CLK3N 2 22P/50V_4N AB5 PCI_CLK1_R GPP_CLK2P GPP_CLK2N 32K_X1 C397 AF3 AF1 AF5 AG2 AF6 +BAT V33 V31 W30 W32 AB26 AB27 AA24 AA23 Note: CLK_FCH_SRCP/N is 100MHZ SSC C AF29 AF31 Part 1 of 5 1 590/F_4 PCIE_CALRP 2K/F_4 PCIE_CALRN R275 R276 +1.1V_PCIE_VDDR D3A HUDSON-M3 2 AB33 AB31 AB28 AB29 Y33 Y31 Y28 Y29 UMI_TXP0 UMI_TXN0 UMI_TXP1 UMI_TXN1 UMI_TXP2 UMI_TXN2 UMI_TXP3 UMI_TXN3 UMI_TXP0 UMI_TXN0 UMI_TXP1 UMI_TXN1 UMI_TXP2 UMI_TXN2 UMI_TXP3 UMI_TXN3 PCIE_RST# A_RST# 1 2 AE30 AE32 AD33 AD31 AD28 AD29 AC30 AC32 4 3 UMI_RXP0_C UMI_RXN0_C UMI_RXP1_C UMI_RXN1_C UMI_RXP2_C UMI_RXN2_C UMI_RXP3_C UMI_RXN3_C LPC 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X AE2 AD5 PCI CLKS UMI_RXP0 UMI_RXN0 UMI_RXP1 UMI_RXN1 UMI_RXP2 UMI_RXN2 UMI_RXP3 UMI_RXN3 C767 C764 C765 C766 C770 C771 C773 C774 PCIE_RST#_R A_RST# PCI INTERFACE [3] [3] [3] [3] [3] [3] [3] [3] UMI_RXP0 UMI_RXN0 UMI_RXP1 UMI_RXN1 UMI_RXP2 UMI_RXN2 UMI_RXP3 UMI_RXN3 33_4 APU [30,31,36] PLTRST# R669 PCI EXPRESS INTERFACES PLTRST# D [3] [3] [3] [3] [3] [3] [3] [3] 150P/50V_4N 150P/50V_4N CLOCK GENERATOR C842 *1M/F_4 T41 RTC_CLK [11,36] +3V_RTC +3V_RTC C531 0.1U/10V_4X S5_CORE_EN is necessary to connect enable pin of +3VPCU/+5VPCU regulator for S5+ mode implementation INTRUDER_ALERT# Left not connected (FCH has 50-kohm internal pull-up to VBAT). G6 *SHORT_PAD A A Quanta Computer Inc. PROJECT :BY6/BY6D Size Document Number Rev 1A FCH 2/5(ACPI/PCI/CLK) Date: 5 4 3 2 Tuesday, February 14, 2012 1 Sheet 8 of 47 5 4 3 2 1 09 U3B [33] SATA_RXN0 [33] SATA_RXP0 D SATA ODD AN22 AL22 [33] SATA_TXP1 [33] SATA_TXN1 AH20 AJ20 [33] SATA_RXN1 [33] SATA_RXP1 AJ22 AH22 AM23 AK23 AH24 AJ24 AN24 AL24 AL26 AN26 AJ26 AH26 AN29 AL28 AK27 AM27 AL29 AN31 AL31 AL33 PLACE SATA_CAL RES VERY CLOSE TO BALL OF HUDSON-M2/M3 C AH33 AH31 AJ33 AJ31 R581 +1.1V_AVDD_SATA R583 1K/F_4 931/F_4 T137 SATA_CALRP SATA_CALRN AF28 AF27 SATA_LED# AD22 AF21 SATA_TX0P SATA_TX0N HUDSON-M3 SATA_RX0N SATA_RX0P SATA_TX1P SATA_TX1N SATA_RX1N SATA_RX1P SATA_TX2P SATA_TX2N SATA_RX2N SATA_RX2P SATA_TX3P SATA_TX3N SATA_RX3N SATA_RX3P SATA_TX4P SATA_TX4N SATA_RX4N SATA_RX4P SATA_TX5P SATA_TX5N SATA_RX5N SATA_RX5P NC6 NC7 R648 *10K/F_4 NC10 NC11 VGA_BLUE NC12 NC13 BOARD_ID1 BOARD_ID11 FCH_PROCHOT#_C BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5 BOARD_ID6 BOARD_ID7 TEMPIN3 B R673 10K_4 AH16 AM15 AJ16 AK15 AN16 AL16 K6 K5 K3 M6 VGA_HSYNC/GPO68 VGA_VSYNC/GPO69 VGA_DDC_SDA/GPO70 VGA_DDC_SCL/GPO71 SATA_CALRP SATA_CALRN VGA_DAC_RSET SATA_ACT#/GPIO67 AUX_VGA_CH_P AUX_VGA_CH_N AUXCAL SATA_X1 SATA_X2 Remove Zero Power ODD funciton T138 SPI_DI/GPIO164 SPI_DO/GPIO163 SPI_CLK/GPIO162 SPI_CS1#/GPIO165 ROM_RST#/SPI_WP#/GPIO161 VGA_GREEN VGA MAINLINK AG21 GBE_COL GBE_CRS GBE_MDCK GBE_MDIO GBE_RXCLK GBE_RXD3 GBE_RXD2 GBE_RXD1 GBE_RXD0 GBE_RXCTL/RXDV GBE_RXERR GBE_TXCLK GBE_TXD3 GBE_TXD2 GBE_TXD1 GBE_TXD0 GBE_TXCTL/TXEN GBE_PHY_PD GBE_PHY_RST# GBE_PHY_INTR VGA_RED NC8 NC9 Integrated Clock Mode: Leave unconnected. +3V Part 2 of 5 SD_CLK/SCLK_2/GPIO73 SD_CMD/SLOAD_2/GPIO74 SD_CD#/GPIO75 SD_WP/GPIO76 SD_DATA0/SDATI_2/GPIO77 SD_DATA1/SDATO_2/GPIO78 SD_DATA2/GPIO79 SD_DATA3/GPIO80 SD CARD AL20 AN20 GBE LAN AK19 AM19 SERIAL ATA B2A [33] SATA_TXP0 [33] SATA_TXN0 SPI ROM SATA HDD/SSD VGA DAC PLACE SATA AC COUPLING CAPS CLOSE TO HUDSON-M2/M3 FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54 FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58 HW MONITOR TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173 TEMPIN3/TALERT#/GPIO174 ML_VGA_L0P ML_VGA_L0N ML_VGA_L1P ML_VGA_L1N ML_VGA_L2P ML_VGA_L2N ML_VGA_L3P ML_VGA_L3N ML_VGA_HPD/GPIO229 VIN0/GPIO175 VIN1/GPIO176 VIN2/SDATI_1/GPIO177 VIN3/SDATO_1/GPIO178 VIN4/SLOAD_1/GPIO179 VIN5/SCLK_1/GPIO180 VIN6/GBE_STAT3/GPIO181 VIN7/GBE_LED3/GPIO182 NC1 NC2 NC3 NC4 NC5 W25Q32BVSSIG:AKE391P0N00 W25Q16BVSSIG:AKE38FP0N01 +3V_S5 AL14 AN14 AJ12 AH12 AK13 AM13 AH15 AJ14 AC4 AD3 AD9 W10 AB8 AH7 AF7 AE7 AD7 AG8 AD1 AB7 AF9 AG6 AE8 AD8 AB9 AC2 AA7 W9 A-stage Socket: DG008000031 91960-0084L R496 R376 1 6 5 2 FCH_SPI_SI_R 33_4 3 C557 *22P/50V_4N CE# SCK SI SO HOLD# VDD WP# VSS 8 R372 10K_4 7 SPI_HOLD# [7] 4 C551 0.1U/10V_4X W25Q16BVSSIG B2A +3V_S5 GBE_PHY_INTR R342 10K_4 L30 FCH_CRT_RED FCH_CRT_RED [32] L32 FCH_CRT_GRE FCH_CRT_GRE [32] M29 FCH_CRT_BLU FCH_CRT_BLU [32] R380 R386 R387 33_4 33_4 33_4 R488 10K_4 FCH_SPI_WP +3V_S5 FCH_SPI_SO_R FCH_SPI_CLK_R FCH_SPI_CS0#_R FCH_SPI_WP FCH_SPI_SI FCH_SPI_SO FCH_SPI_CLK FCH_SPI_CS0# R place close to PCH M28 N30 FCH_CRT_RED R291 150/F_4 FCH_CRT_GRE R290 150/F_4 FCH_CRT_BLU R285 150/F_4 C FCH_CRT_HSYNC [32] FCH_CRT_VSYNC [32] M33 N32 +1.5VSUS FCH_DDCDAT [32] FCH_DDCCLK [32] K31 R293 715/F_4 R287 100/F_4 V28 V29 +FCH_VDDAN_11_MLDAC T31 T33 T29 T28 R32 R30 P29 P28 APU_DP_TXP0 APU_DP_TXN0 APU_DP_TXP1 APU_DP_TXN1 APU_DP_TXP2 APU_DP_TXN2 APU_DP_TXP3 APU_DP_TXN3 10K_4 10K_4 10K_4 R675 10K_4 D3A +3V_S5 BOARD ID SETTING Board ID UMA SKU VGA SKU VRAM 900M VRAM 800M USB3.0 USB2.0 W/O LAN W LAN W/O S&C W S&C W/O BT W BT W/O CEC W CEC W/O HDMI W HDMI W/O CRT W CRT Metal/IMR TEXTURE C3A B2A C596 *0.1U/10V_4X T43 T44 Hudson-M3 B2A R427 *1K/F_4 FCH_VGA_HPD [5] R359 R674 R676 C3A A C599 *0.1U/10V_4X R296 *10K/F_4 +3V B2A VIN_VDDR R429 *1K/F_4 AG16 AH10 A28 G27 L4 C3A R426 *1K/F_4 VIN_VDDIO +3V_S5 [5] [5] [5] [5] [5] [5] [5] [5] FCH_VGA_HPD VIN0 VIN1 VIN2 MEM_P1V5 MEM_P1V35 VIN_VDDIO VIN_VDDR VIN7 +1.2V_VDDPR R425 *1K/F_4 APU_DP_AUXP [5] APU_DP_AUXN [5] U28 C29 FCH_SPI_CS0# FCH_SPI_CLK FCH_SPI_SO FCH_SPI_SI [36] FCH_SPI_CS0# [36] FCH_SPI_CLK [36] FCH_SPI_SO [36] FCH_SPI_SI V6 V5 V3 T6 V1 N2 M3 L2 N4 P1 P3 M1 M5 D 10K_4 U18 ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 ID9 ID10 R312 R334 R704 R297 R692 R736 R322 UMA@10K_4 *10K_4 U3@10K_4 NLAN@10K_4 NHM@10K_4 NCRT@10K_4 M3@10K_4 BOARD_ID1 R317 BOARD_ID2 R333 BOARD_ID3 R424 BOARD_ID4 R310 BOARD_ID8 R693 BOARD_ID9 R538 BOARD_ID11 R320 DIS@10K_4 10K_4 U2@10K_4 LAN@10K_4 HM@10K_4 CRT@10K_4 M2@10K_4 R684 R671 R699 NS&C@10K_4 10K_4 NCEC@10K_4 BOARD_ID5 R683 BOARD_ID6 R677 BOARD_ID7 R422 S&C@10K_4 *10K_4 CEC@10K_4 R703 10K_4 BOARD_ID10 R423 *10K_4 B ID11 [7] BOARD_ID8 [7] BOARD_ID9 [7,35] BOARD_ID10 H L BOARD_ID8 BOARD_ID9 BOARD_ID10 H L H L H L H L H L A H L H L H L H L Quanta Computer Inc. FCH-M3 FCH-M2 H L PROJECT :BY6/BY6D Size Document Number FCH 3/5(SATA/VGA/GND/SPI) Date: 5 4 3 2 Tuesday, February 14, 2012 1 Sheet 9 of Rev 1A 47 4 3 2 PLACE ALL THE DECOUPLING CAPS ON THIS SHEET CLOSE TO SB AS POSSIBLE. TRACE WIDTH >=15mil HCB1608KF-221T20_2A C383 2.2U/6.3V_4X C393 *0.1U/10V_4X D3A +VDDPL_3.3V L32 +FCH_VDDPL_33_MLDAC +FCH_VDDAN_33_DAC_R +FCH_VDDPL_33_SSUSB_S +FCH_VDDPL_33_SUSB_S TRACE WIDTH >=15mil HCB1608KF-221T20_2A C389 2.2U/6.3V_4X C399 *0.1U/10V_4X D3A R278 +FCH_VDDAN_11_MLDAC R279 HCB1608KF-221T20_2A +3V_S5 *SHORT_8 R563 C756 *0_4 LDO_CAP *2.2U/6.3V_6X M31 +FCH_VDDAN_11_DAC +FCH_VDDPL_33_SSUSB_S C463 0.1U/10V_4X C419 1U/10V_4X V21 7mA 226mA +FCH_VDDAN_11_ML 0_8 Y22 V23 V24 V25 C441 0.1U/10V_4X C418 4.7U/6.3V_6X AB10 L44 U3@HCB1608KF-221T20_2A C508 [email protected]/6.3V_6X C496 [email protected]/10V_4X VDDPL_33_SYS VDDPL_33_DAC VDDPL_33_ML VDDAN_33_DAC VDDPL_33_SSUSB_S VDDPL_33_USB_S VDDPL_33_PCIE VDDPL_33_SATA AB11 AA11 U2@0_4 D3A +FCH_VDDPL_33_SUSB_S +3V_AVDD_USB R298 *SHORT_8 C382 2.2U/6.3V_6X C384 0.1U/10V_4X AA9 AA10 VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8 LDO_CAP VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8 VDDPL_11_DAC VDDAN_11_ML_1 VDDAN_11_ML_2 VDDAN_11_ML_3 VDDAN_11_ML_4 VDDIO_33_GBE_S +FCH_VDDPL_33_MLDAC R412 C H24 V22 U22 T22 L18 D7 AH29 AG28 +FCH_VDDPL_33_PCIE +FCH_VDDPL_33_SATA +1.5VSUS L24 47mA 20mA 12mA 200mA 11mA 14mA 11mA 12mA 0_8 0_8 VDDAN_11_SATA_1 VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7 VDDAN_11_SATA_8 VDDAN_11_SATA_9 VDDAN_11_SATA_10 GBE LAN +3V R169 R171 VDDCR_11_GBE_S_1 VDDCR_11_GBE_S_2 VDDIO_GBE_S_1 VDDIO_GBE_S_2 R300 C478 C477 C490 0.1U/10V_4X 0.1U/10V_4X 1U/10V_4X C489 1U/10V_4X C498 C497 10U/6.3V_8X 1U/10V_4X TRACE WIDTH >=30mil C460 1U/10V_4X C459 1U/10V_4X C514 2.2U/6.3V_4X L42 HCB1608KF-181T15_1.5A +1.1V L29 HCB1608KF-181T15_1.5A +1.1V L30 HCB1608KF-181T15_1.5A +1.1V C442 C404 C484 C474 0.1U/10V_4X 0.1U/10V_4X 22U/6.3V_8X 1U/10V_4X +1.1V_PCIE_VDDR AB24 Y21 AE25 AD24 AB23 AA22 AF26 AG27 TRACE WIDTH >=100mil 1088mA PCIE_VDDR--PCIE I/O power C407 C445 C430 0.1U/10V_4X 0.1U/10V_4X 1U/10V_4X C415 1U/10V_4X C391 C398 22U/6.3V_8X 1U/10V_4X +1.1V_AVDD_SATA AA21 Y20 AB21 AB22 AC22 AC21 AA20 AA18 AB20 AC19 TRACE WIDTH >=50mil 1337mA C467 1U/10V_4X +FCH_VDDAN_33_DAC_R C451 1U/10V_4X AVDD_SATA--SATA phy power C472 C466 C412 C387 0.1U/10V_4X 0.1U/10V_4X 22U/6.3V_8X 1U/10V_4X HCB1608KF-221T20_2A C520 C552 C540 C545 C519 0.1U/10V_4X 22U/6.3V_8X10U/6.3V_8X 10U/6.3V_8X 1U/10V_4X EMI +FCH_VDDAN_11_USB_S C566 2.2U/6.3V_6X C504 0.1U/10V_4X C548 0.1U/10V_4X L49 +1.1V_DUAL HCB1608KF-221T20_2A TRACE WIDTH >=20mil U12 U13 140mA HCB1608KF-221T20_2A +1.1V_DUAL +FCH_VDD_11_SSUSB_S L46 U3@HCB1608KF-221T20_2A C505 0.1U/10V_4X C518 C587 0.1U/10V_4X 10U/6.3V_8X R302 *SHORT_8 +FCH_VDDAN_11_SSUSB_S_R R304 *SHORT_8 +FCH_VDDCR_11_SSUSB_S C515 U3@10U/6.3V_8X C510 U3@1U/10V_4X C507 [email protected]/10V_4X 42mA P16 M14 N14 P13 P14 D3A R413 U2@0_4 T12 T13 +FCH_VDDCR_11_USB_S TRACE WIDTH >=15mil L52 +1.1V_DUAL C525 1U/10V_4X C495 [email protected]/10V_4X C506 U3@1U/10V_4X 282mA C485 [email protected]/10V_4X C493 U3@1U/10V_4X N16 N17 P17 M17 424mA VDDAN_33_USB_S_1 VDDAN_33_USB_S_2 VDDAN_33_USB_S_3 VDDAN_33_USB_S_4 VDDAN_33_USB_S_5 VDDAN_33_USB_S_6 VDDAN_33_USB_S_7 VDDAN_33_USB_S_8 VDDAN_33_USB_S_9 VDDAN_33_USB_S_10 VDDAN_33_USB_S_11 VDDAN_33_USB_S_12 VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8 VDDXL_33_S VDDAN_11_USB_S_1 VDDAN_11_USB_S_2 VDDCR_11_S_1 VDDCR_11_S_2 VDDCR_11_USB_S_1 VDDCR_11_USB_S_2 VDDPL_11_SYS_S VDDAN_33_HWM_S VDDAN_11_SSUSB_S_1 VDDAN_11_SSUSB_S_2 VDDAN_11_SSUSB_S_3 VDDAN_11_SSUSB_S_4 VDDAN_11_SSUSB_S_5 VDDCR_11_SSUSB_S_1 VDDCR_11_SSUSB_S_2 VDDCR_11_SSUSB_S_3 VDDCR_11_SSUSB_S_4 N18 L19 M18 V12 V13 Y12 Y13 W11 G24 TRACE WIDTH >=20mil +VDDIO_33_S 59mA R314 C503 C455 C521 C538 *0.1U/10V_4X 2.2U/6.3V_6X 2.2U/6.3V_6X 1U/10V_4X 5mA S5 plus mode D3A C530 1U/10V_4X +VDDXL_3.3V 113mA +VDDCR_1.1V TRACE WIDTH >=15mil R353 0_6 +3V_S5 L33 HCB1608KF-221T20_2A S5_1.1V--1.1V standby power N20 M20 *SHORT_6 C527 C523 1U/10V_4X 1U/10V_4X +1.1V_DUAL C420 *0.1U/10V_4X C386 2.2U/6.3V_6X +3V_S5 C385 1U/10V_4X VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 N8 J24 M8 70mA 12mA C473 1U/10V_4X +VDDPL_1.1V C461 C456 1U/10V_4X 2.2U/6.3V_4X Part 5 of 5 VSSAN_HWM K25 VSSPL_SYS EFUSE VDDIO_AZ_S AA4 26mA R414 +15V L67 *HCB1608KF-221T20_2A C448 *0.1U/10V_4X 1 L62 HCB1608KF-221T20_2A Q84 HCB1608KF-221T20_2A C427 2.2U/6.3V_6X C443 0.1U/10V_4X C570 2.2U/6.3V_6X C532 0.1U/10V_4X +1.1V R294 100K/F_4 3 L40 HCB1608KF-221T20_2A L51 C437 2.2U/6.3V_6X C433 0.1U/10V_4X [7] VGA_PD VGA_PD C759 *1U/10V_4X 2 2 R566 2.2K_4 Q75 PMV45EN_4A FDV301N_200MA C755 *1U/10V_4X C784 0.1U/10V_4X L68 *HCB1608KF-221T20_2A Q75&Q76 1st BAM34040001, Rdson=22.5m 2nd BAM2306006, Rdson=38m 1 C593 2.2U/6.3V_6X +VDDPL_3.3V +VDDAN_3.3V_HWM C777 2.2U/6.3V_6X Q77 PMV45EN_4A 1 *SHORT_8 B 32mA Max 3 +3V R301 R6 +FCH_VDDAN_33_DAC +VDDPL_1.1V +3V_S5 T21 L28 K33 N28 +FCH_VDDAN_33_DAC_R POWER +VDDIO_AZ L36 U2@HCB1608KF-221T20_2A L35 U3@HCB1608KF-221T20_2A C +3V U2@0_4 C482 [email protected]/10V_4X 2 D3A D Trace width >=20 mil R558 1M_4 +3V_S5 T25 T27 U6 U14 U17 U20 U21 U30 U32 V11 V16 V18 W4 W6 W25 W28 Y14 Y16 Y18 AA6 AA12 AA13 AA14 AA16 AA17 AA25 AA28 AA30 AA32 AB25 AC6 AC18 AC28 AD27 AE6 AE15 AE21 AE28 AF8 AF12 AF16 AF33 AG30 AG32 AH5 AH11 AH18 AH19 AH21 AH23 AH25 AH27 AJ18 AJ28 AJ29 AK21 AK25 AL18 AM21 AM25 AN1 AN18 AN28 AN33 Hudson-M3 +VDDIO_AZ Hudson-M3 +1.1V_DUAL +1.1V VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSSPL_DAC VSSAN_DAC VSSANQ_DAC VSSIO_DAC VSSXL H25 +VDDAN_3.3V_HWM HUDSON-M3 USB SS L47 +3V_S5 G7 H8 J8 K8 K9 M9 M10 N9 N10 M12 N12 M11 470mA USB +3V_AVDD_USB TRACE WIDTH >=50mil 3.3V_S5 I/O S5_3.3--3.3v standby power C829 1U/10V_4X +1.1V CKVDD_1.1V-Internal clock Generator I/O power +1.1V_CKVDD 340mA H26 J25 K24 L22 M22 N21 N22 P22 C513 2.2U/6.3V_4X *SHORT_8 L73 HCB1608KF-221T20_2A C832 2.2U/6.3V_6X B TRACE WIDTH >=100mil 1007mA T14 T17 T20 U16 U18 V14 V17 V20 Y17 3 L31 CORE S0 +3V PCI/GPIO I/O C512 C543 C491 C501 C494 C524 1U/10V_4X 1U/10V_4X 22U/6.3V_8X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X D Part 3 of 5 VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8 VDDCR_11_9 A3 A33 B7 B13 D9 D13 E5 E12 E16 E29 F7 F9 F11 F13 F16 F17 F19 F23 F25 F29 G6 G16 G32 H12 H15 H29 J6 J9 J10 J13 J28 J32 K7 K16 K27 K28 L6 L12 L13 L15 L16 L21 M13 M16 M21 M25 N6 N11 N13 N23 N24 P12 P18 P20 P21 P31 P33 R4 R11 R25 R28 T11 T16 T18 D3A +1.1V_VCC_FCH_R HUDSON-M3 VDDIO_33_PCIGP_1 VDDIO_33_PCIGP_2 VDDIO_33_PCIGP_3 VDDIO_33_PCIGP_4 VDDIO_33_PCIGP_5 VDDIO_33_PCIGP_6 VDDIO_33_PCIGP_7 VDDIO_33_PCIGP_8 VDDIO_33_PCIGP_9 VDDIO_33_PCIGP_10 CLKGEN I/O C541 1U/10V_4X AB17 AB18 AE9 AD10 AG7 AC13 AB12 AB13 AB14 AB16 SERIAL ATA C539 1U/10V_4X U3C 102mA *SHORT_8 MAIN LINK PCI EXPRESS VDDQ--3.3V I/O power R299 10 U3D VDD-- S/B CORE power +3.3V_FCH_R D3A +3V 1 GROUND 5 +FCH_VDDAN_11_MLDAC A A Quanta Computer Inc. PROJECT :BY6/BY6D Size Document Number Rev 1A FCH 4/5(POWER) Date: 5 4 3 2 Tuesday, February 14, 2012 1 Sheet 10 of 47 5 4 3 2 1 11 OVERLAP COMMON PADS WHERE POSSIBLE FOR DUAL-OP RESISTORS. +3V +3V +3V +3V_S5 +3V_S5 +3V_S5 +3V_S5 STRAPS PINS D D R700 10K_4 PCI_CLK1 [8] PCI_CLK3 PCI_CLK3 [8] PCI_CLK4 PCI_CLK4 [8] LPC_CLK0 LPC_CLK0 [8] LPC_CLK1 LPC_CLK1 [7] EC_PWM2 EC_PWM2 R701 *10K_4 R617 *10K_4 R625 10K_4 R305 *10K_4 R663 10K_4 +3V_S5 +3V_S5 R435 10K_4 5 [8] PCI_CLK1 R702 *10K_4 C610 *0.1U/10V_4X U20 RTC_CLK D42 [41,42] VRM_PWRGD 2 1SS355_100MA C604 *2.2U/6.3V_6X R686 *10K_4 R690 10K_4 R688 10K_4 R612 10K_4 R620 *10K_4 R306 2.2K_4 R672 *2.2K_4 4 R439 *0_4 *SN74LVC1G17DCKR FCH_PWRGD [5,7] 3 [8,36] RTC_CLK D3A EC_PWM2--> SPI ROM: 2.2-Kȍ 5% pull-down LPC ROM: Pull-up to 3.3V_S5. External pull-up resistor is not required as FCH has integrated 10-Kȍ pull-up to 3.3V_S5. R440 [36] MPWROK D49 *SHORT_4 1SS355_100MA C C Remove PCI_CLK2 function -------- REQUIRED STRAPS PULL HIGH PULL LOW -------- -------- PCI_CLK1 ALLOW PCIE Gen2 DEFAULT FORCE PCIE Gen1 PCI_CLK2 -------- -------- PCI_CLK3 PCI_CLK4 LPC_CLK0 EC ENABLED USE DEBUG STRAP non_Fusion CLOCK MODE IGNORE DEBUG STRAP FUSION CLOCK MODE EC DISABLED DEFAULT DEFAULT LPC_CLK1 EC_PWM2 CLKGEN ENABLED LPC ROM DEFAULT CLKGEN DISABLED RTC_CLK S5 PLUS MODE DISABLED FCH PWRGD CKT DEFAULT SPI ROM S5 PLUS MODE ENABLED DEFAULT DEFAULT B B DEBUG STRAPS FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23] [8] PCI_AD27 [8] PCI_AD26 [8] PCI_AD25 [8] PCI_AD24 [8] PCI_AD23 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PULL HIGH PCI_AD23 R345 *2.2K_4 R401 *2.2K_4 R402 *2.2K_4 R351 *2.2K_4 R350 *2.2K_4 PULL LOW PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 USE PCI PLL DISABLE ILA AUTORUN USE FC PLL USE DEFAULT PCIE STRAPS DISABLE PCI MEM BOOT DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT BYPASS PCI PLL ENABLE ILA AUTORUN BYPASS FC PLL USE EEPROM PCIE STRAPS ENABLE PCI MEM BOOT A A Quanta Computer Inc. PROJECT :BY6/BY6D Size Document Number Rev 1A FCH 5/5(STRAP & PWRGD) Date: 5 4 3 2 Tuesday, February 14, 2012 1 Sheet 11 of 47 5 4 3 2 1 12 DDR_STD(DDR) [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] 10K_4 10K_4 R19 R18 M_A_BS#0 M_A_BS#1 M_A_BS#2 M_A_CS#0 M_A_CS#1 M_A_CLKP0 M_A_CLKN0 M_A_CLKP1 M_A_CLKN1 M_A_CKE0 M_A_CKE1 M_A_CAS# M_A_RAS# M_A_WE# [7,13,35] SMB_RUN_CLK [7,13,35] SMB_RUN_DAT C Reserve ICT test point 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 DIMM0_SA0 DIMM0_SA1 SMB_RUN_CLK SMB_RUN_DAT 109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200 116 120 [4] M_A_ODT0 [4] M_A_ODT1 11 28 46 63 136 153 170 187 [4] M_A_DM0 [4] M_A_DM1 [4] M_A_DM2 [4] M_A_DM3 [4] M_A_DM4 [4] M_A_DM5 [4] M_A_DM6 [4] M_A_DM7 [4] M_A_DQSP[7:0] M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7 [4] M_A_DQSN[7:0] 12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15 BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 PC2100 DDR3 SDRAM SO-DIMM (204P) D M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 [4] +1.5VSUS JDIM6B 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2.48A 199 +3V 77 122 125 198 30 [4] M_A_EVENT# [4] M_A_RST# 1 126 +0.75V_VREF_DQ +0.75V_VREF_CA 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 +1.5VSUS +0.75V_VREF_CA +SMDDR_VREF R311 1K/F_4 R321 0_6 R323 R319 1K/F_4 *0_6 C401 470P/50V_4X VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDDSPD NC1 NC2 NCTEST EVENT# RESET# VREF_DQ VREF_CA VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 PC2100 DDR3 SDRAM SO-DIMM (204P) M_A_DQ[0..63] JDIM6A [4] M_A_A[15:0] VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VTT1 VTT2 GND GND 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 D C 203 204 +SMDDR_VTERM 205 206 DDRSK-20401-TP8D +1.5VSUS DDRSK-20401-TP8D R355 +SMDDR_VREF R316 1K/F_4 +0.75V_VREF_DQ 0_6 R324 *0_6 B B R313 1K/F_4 C408 470P/50V_4X D3A Place these Caps near So-Dimm0. +1.5VSUS +1.5VSUS C542 C517 C529 C546 C522 C526 C536 C535 C500 C502 C509 C528 C516 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X *10U/6.3V_6X 1U/10V_4X 1U/10V_4X 1U/10V_4X 1U/10V_4X 10U/6.3V_8X 10U/6.3V_8X +3V +SMDDR_VTERM +0.75V_VREF_DQ EMI Suggestion C396 C388 C390 C392 C394 C395 C400 ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N +0.75V_VREF_CA A A C499 C492 C547 C511 C647 C645 C646 C544 2.2U/6.3V_6X 0.1U/10V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 10U/6.3V_6X *10U/6.3V_6X C435 C409 C403 C438 0.1U/10V_4X 1000P/50V_4X 0.1U/10V_4X 1000P/50V_4X Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev 1A DDR3 DIMM-1 Date: 5 4 3 2 Tuesday, February 14, 2012 Sheet 1 12 of 47 5 4 3 2 1 13 DDR_RVS(DDR) D +3V [7,12,35] SMB_RUN_CLK [7,12,35] SMB_RUN_DAT 109 108 79 114 121 101 103 102 104 73 74 115 110 113 197 201 202 200 [4] M_B_ODT0 [4] M_B_ODT1 116 120 [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] 10K_4 10K_4 R462 R464 Reserve ICT test point C 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 M_B_BS#0 M_B_BS#1 M_B_BS#2 M_B_CS#0 M_B_CS#1 M_B_CLKP0 M_B_CLKN0 M_B_CLKP1 M_B_CLKN1 M_B_CKE0 M_B_CKE1 M_B_CAS# M_B_RAS# M_B_WE# DIMM1_SA0 DIMM1_SA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15 BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA ODT0 ODT1 11 28 46 63 136 153 170 187 [4] M_B_DM0 [4] M_B_DM1 [4] M_B_DM2 [4] M_B_DM3 [4] M_B_DM4 [4] M_B_DM5 [4] M_B_DM6 [4] M_B_DM7 [4] M_B_DQSP[7:0] M_B_DQSP0 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7 M_B_DQSN0 M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7 [4] M_B_DQSN[7:0] DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 12 29 47 64 137 154 171 188 10 27 45 62 135 152 169 186 PC2100 DDR3 SDRAM SO-DIMM (204P) M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 [4] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 +1.5VSUS JDIM7B 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2.48A 199 +3V 77 122 125 198 30 [4] M_B_EVENT# [4] M_B_RST# 1 126 +0.75V_VREF_DQ +0.75V_VREF_CA 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDDSPD NC1 NC2 NCTEST EVENT# RESET# VREF_DQ VREF_CA VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 PC2100 DDR3 SDRAM SO-DIMM (204P) M_B_DQ[0..63] JDIM7A [4] M_B_A[15:0] VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VTT1 VTT2 GND GND 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 D C 203 204 +SMDDR_VTERM 205 206 DDRSK-20401-TP4B DDRSK-20401-TP4B B B D3A Place these Caps near So-Dimm1. +1.5VSUS +1.5VSUS C483 EMI Suggestion +0.75V_VREF_CA C465 C476 C487 C470 C471 C481 C480 C454 C458 C457 C475 C468 C449 0.1U/10V_4X 1000P/50V_4X C464 C447 C450 C439 C440 C444 C446 ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X 10U/6.3V_6X *10U/6.3V_6X 1U/10V_4X 1U/10V_4X 1U/10V_4X 1U/10V_4X 10U/6.3V_8X 10U/6.3V_8X +0.75V_VREF_DQ A C453 A +SMDDR_VTERM +3V C452 C488 2.2U/6.3V_6X 0.1U/10V_4X C462 C644 C643 C642 C469 C479 0.1U/10V_4X 1000P/50V_4X C486 Quanta Computer Inc. 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 1U/6.3V_4X 10U/6.3V_6X *10U/6.3V_6X PROJECT : BY6/BY6D Size Document Number Rev 1A DDR3 DIMM-2 Date: 5 4 3 2 Tuesday, February 14, 2012 Sheet 1 13 of 47 [3] PEG_TXP[0..15] [3] PEG_TXN[0..15] PEG_TXP[0..15] <VGA> 14 U5000A PEG_TXN[0..15] PART 1 0F 9 [3] PEG_RXN[0..15] PEG_RXP[0..15] PEG_RXN[0..15] [3] PEG_TXP0 [3] PEG_TXN0 [3] PEG_TXP1 [3] PEG_TXN1 [3] PEG_TXP2 [3] PEG_TXN2 [3] PEG_TXP3 [3] PEG_TXN3 [3] PEG_TXP4 [3] PEG_TXN4 [3] PEG_TXP5 [3] PEG_TXN5 [3] PEG_TXP6 [3] PEG_TXN6 [3] PEG_TXP7 [3] PEG_TXN7 [3] PEG_TXP8 [3] PEG_TXN8 [3] PEG_TXP9 [3] PEG_TXN9 [3] PEG_TXP10 [3] PEG_TXN10 [3] PEG_TXP11 [3] PEG_TXN11 [3] PEG_TXP12 [3] PEG_TXN12 [3] PEG_TXP13 [3] PEG_TXN13 [3] PEG_TXP14 [3] PEG_TXN14 [3] PEG_TXP15 [3] PEG_TXN15 PEG_TXP0 PEG_TXN0 AA38 Y37 PCIE_RX0P PCIE_TX0P PCIE_RX0N PCIE_TX0N PEG_TXP1 PEG_TXN1 Y35 W36 PCIE_RX1P PCIE_TX1P PCIE_RX1N PCIE_TX1N PEG_TXP2 PEG_TXN2 W38 V37 PCIE_RX2P PCIE_TX2P PCIE_RX2N PCIE_TX2N PEG_TXP3 PEG_TXN3 V35 U36 PCIE_RX3P PCIE_TX3P PCIE_RX3N PCIE_TX3N PEG_TXP4 PEG_TXN4 U38 T37 PCIE_RX4P PCIE_TX4P PCIE_RX4N PCIE_TX4N PEG_TXP5 PEG_TXN5 T35 R36 PCIE_RX5P PCIE_TX5P PCIE_RX5N PCIE_TX5N PEG_TXP6 PEG_TXN6 R38 P37 PCIE_RX6P PCIE_TX6P PCIE_RX6N PCIE_TX6N PEG_TXP7 PEG_TXN7 P35 N36 PCIE_RX7P PCIE_TX7P PCIE_RX7N PCIE_TX7N PEG_TXP8 PEG_TXN8 N38 M37 PCIE_RX8P PCIE_TX8P PCIE_RX8N PCIE_TX8N PEG_TXP9 PEG_TXN9 M35 L36 PCIE_RX9P PEG_TXP10 PEG_TXN10 L38 K37 PCIE_RX10P PEG_TXP11 PEG_TXN11 K35 J36 PCIE_RX11P PCIE_TX11P PCIE_RX11N PCIE_TX11N PEG_TXP12 PEG_TXN12 J38 H37 PCIE_RX12P PCIE_TX12P PCIE_RX12N PCIE_TX12N PEG_TXP13 PEG_TXN13 H35 G36 PCIE_RX13P PCIE_TX13P PCIE_RX13N PCIE_TX13N PEG_TXP14 PEG_TXN14 G38 F37 PCIE_RX14P PCIE_TX14P PCIE_RX14N PCIE_TX14N PEG_TXP15 PEG_TXN15 F35 E37 PCIE_RX15P PCIE_TX15P PCIE_RX15N PCIE_TX15N PCIE_RX9N PCIE_RX10N PCI EXPRESS INTERFACE [3] PEG_RXP[0..15] PCIE_TX9P PCIE_TX9N PCIE_TX10P PCIE_TX10N Y33 CPEG_RXP0 Y32 CPEG_RXN0 C5001 C5002 [email protected]/10V_4X [email protected]/10V_4X W33 CPEG_RXP1 W32 CPEG_RXN1 C5003 C5004 [email protected]/10V_4X [email protected]/10V_4X U33 CPEG_RXP2 U32 CPEG_RXN2 C5005 C5006 [email protected]/10V_4X [email protected]/10V_4X U30 CPEG_RXP3 U29 CPEG_RXN3 C5007 C5008 [email protected]/10V_4X [email protected]/10V_4X T33 T32 CPEG_RXP4 CPEG_RXN4 C5009 C5010 [email protected]/10V_4X [email protected]/10V_4X T30 T29 CPEG_RXP5 CPEG_RXN5 C5011 C5012 [email protected]/10V_4X [email protected]/10V_4X P33 CPEG_RXP6 P32 CPEG_RXN6 C5013 C5014 [email protected]/10V_4X [email protected]/10V_4X P30 CPEG_RXP7 P29 CPEG_RXN7 C5015 C5016 [email protected]/10V_4X [email protected]/10V_4X N33 CPEG_RXP8 N32 CPEG_RXN8 C5000 C5017 [email protected]/10V_4X [email protected]/10V_4X N30 CPEG_RXP9 N29 CPEG_RXN9 C5018 C5019 [email protected]/10V_4X [email protected]/10V_4X L33 L32 CPEG_RXP10 CPEG_RXN10 C5020 C5021 [email protected]/10V_4X [email protected]/10V_4X L30 L29 CPEG_RXP11 CPEG_RXN11 C5022 C5023 [email protected]/10V_4X [email protected]/10V_4X K33 CPEG_RXP12 K32 CPEG_RXN12 C5024 C5025 [email protected]/10V_4X [email protected]/10V_4X J33 J32 CPEG_RXP13 CPEG_RXN13 C5026 C5027 [email protected]/10V_4X [email protected]/10V_4X K30 CPEG_RXP14 K29 CPEG_RXN14 C5028 C5029 [email protected]/10V_4X [email protected]/10V_4X H33 CPEG_RXP15 H32 CPEG_RXN15 C5030 C5031 [email protected]/10V_4X [email protected]/10V_4X PEG_RXP0 [3] PEG_RXN0 [3] PEG_RXP1 [3] PEG_RXN1 [3] PEG_RXP2 [3] PEG_RXN2 [3] PEG_RXP3 [3] PEG_RXN3 [3] PEG_RXP4 [3] PEG_RXN4 [3] PEG_RXP5 [3] PEG_RXN5 [3] PEG_RXP6 [3] PEG_RXN6 [3] Thames and Seymour Power-on sequence 1 => +1V_GPU 2 => +3V_GPU 3 => +VGPU_CORE,+1.5V_GPU 4 => +1.8V_GPU PEG Intel platform: Lane0 ~ Lane15 Brazos platform: Lane12 ~ Lane15 Comal and Sabine platform: Lane8 ~Lane15 PEG_RXP7 [3] PEG_RXN7 [3] PEG_RXP8 [3] PEG_RXN8 [3] PEG_RXP9 [3] PEG_RXN9 [3] PEG_RXP10 [3] PEG_RXN10 [3] PEG_RXP11 [3] PEG_RXN11 [3] PEG_RXP12 [3] PEG_RXN12 [3] PEG_RXP13 [3] PEG_RXN13 [3] PEG_RXP14 [3] PEG_RXN14 [3] PEG_RXP15 [3] PEG_RXN15 [3] CLOCK AB35 AA36 [8] CLK_PCIE_VGAP [8] CLK_PCIE_VGAN PCIE_REFCLKP PCIE_REFCLKN CALIBRATION R5000 [24] PERST#_BUF EV@10K_4 AH16 TEST_PG PERST#_BUF AA30 PERSTB PCIE_CALR_TX Y30 R5001 [email protected]/F_4 PCIE_CALR_RX Y29 R5002 EV@2K/F_4 +1V_GPU Quanta Computer Inc. PROJECT : BY6/BY6D EV@HEATHROW M2 Size Document Number Rev A1A Thames_M2/ PEG*16 Date: Monday, February 13, 2012 Sheet 14 of 47 15 <VGA> U5000B PART 2 0F 9 MUTI GFX [17] GENIL_CLK [17] GENIL_VSYNC AD29 AC29 GENLK_CLK TXCAP_DPA3P GENLK_VSYNC TXCAM_DPA3N AJ21 AK21 SWAPLOCKA TX0P_DPA2P TX0M_DPA2N DPA SWAPLOCKB TX1P_DPA1P TX1M_DPA1N [17] [17] [17] [17] [17] AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12 RAM_STRAP0 RAM_STRAP1 RAM_STRAP2 RAM_STRAP3 RAM_STRAP4 1.8V GPIO +3V_GPU R5005 R5004 EV@10K/F_4 EV@10K/F_4 DVPCNTL_MVP_0 TX2P_DPA0P DVPCNTL_MVP_1 TX2M_DPA0N DVPCNTL_1 TXCBP_DPB3P DVPCNTL_2 TXCBM_DPB3N TX3P_DPB2P DVPDATA_1 TX3M_DPB2N DPB DVPDATA_2 DVPDATA_3 TX4P_DPB1P DVPDATA_4 TX4M_DPB1N DVPDATA_6 TX5P_DPB0P DVPDATA_7 TX5M_DPB0N DVPDATA_9 TXCCP_DPC3P DVPDATA_10 EV@10K/F_4 GPU_SCL EV@10K/F_4 GPU_SDA AK26 AJ26 TXCCM_DPC3N DVPDATA_12 TX0P_DPC2P DVPDATA_13 TX0M_DPC2N DVPDATA_14 DPC DVPDATA_15 TX1P_DPC1P DVPDATA_16 TX1M_DPC1N DVPDATA_18 TX2P_DPC0P DVPDATA_19 TX2M_DPC0N DVPDATA_21 TXCDP_DPD3P DVPDATA_22 EV@10K_4 [17] GPU_GPIO8 [17] GPU_GPIO9 [17] GPU_GPIO10 [17] GPU_GPIO11 [17] GPU_GPIO12 [17] GPU_GPIO13 [5,38] SYS_SHDN# 3 [44] GFX_CORE_CNTRL0 T5003 Q24 2 GPIO_19_CTF [44] GFX_CORE_CNTRL1 [17] GPU_GPIO21 [17] GPU_GPIO22 *ME2N7002E_200MA 1 R226 *EV@100K_4 TXCDM_DPD3N DPD SMBCLK TX4P_DPD1P SMBus SMBDATA TX4M_DPD1N SCL [17] GPU_GENERICC Place close to Chip GPIO_2 GPIO_6 GPIO_7_BLON T5047 T5048 VSYNC AC36 AC38 T5049 T5050 RSET AB34 R5011 AVDD AD34 AE34 AVDD AC33 AC34 VDD1DI HSYNC GPIO_10_ROMSCK GPIO_11 GPIO_13 GPIO_14_HPD2 AVSSQ +1.8V_GPU DAC1 Analog Power GPIO_15_PWRCNTL_0 GPIO_16 VDD1DI GPIO_17_THERMAL_INT VSS1DI 1.8V@18mA AVDD GPIO_18_HPD3 L5000 EV@BLM15BD121SN1D_300MA GPIO_19_CTF GPIO_20_PWRCNTL_1 NC#1 GPIO_21 NC#2 GPIO_22_ROMCSB NC#3 CLKREQB NC#4 GPIO_29 NC#7 GPIO_30 NC#8 V13 U13 AC31 AD30 AC32 AD32 AF32 AA29 AG21 T5006 T5007 T5008 T5010 T5011 T5012 T5014 T5016 T5017 C5032 [email protected]/10V_4X C5033 EV@1U/6.3V_4X C5034 [email protected]/6.3V_6X DAC1 Digital Power 1.8V@117mA GENERICA VDD1DI GENERICB L5001 EV@BLM15BD121SN1D_300MA GENERICC GENERICD GENERICE_HPD4 AF33 R5012 EV@0_4 NC_TSVSSQ should be tied to GND on Thames/Whistler/Seymour PS_0 AM34 R5013 EV@0_4 PS_0 should be tied to GND on Thames/Whistler/Seymour PS_1 AD31 PS_2 AG31 PS_3 AD33 NC_TSVSSQ GENERICF_HPD5 C5035 [email protected]/10V_4X C5036 EV@1U/6.3V_4X C5037 [email protected]/6.3V_6X GENERICG_HPD6 AC30 T5025 AK24 HPD1 AH13 VREFG CEC_1 MLPS PS_1,PS_2, PS_3 are NC on Thames/Whistler/Seymour BACO [email protected]/10V_4X [24] PX_EN R5016 PX4@0_4 R5017 *EV@0_4 AL21 PX_EN AD28 TESTEN DDC/AUX DDC1CLK DDC1DATA EV@1K_4 AUX1P R5019 +3V_GPU *[email protected]/F_4 AUX1N AM23 AN23 AK23 AL24 AM24 JTAG_TRSTB DDC2CLK JTAG_TDI DDC2DATA JTAG_TMS AUX2P JTAG_TDO AUX2N DDCCLK_AUX3P DDCDATA_AUX3N T5037 T5039 AF29 AG29 DPLUS R5020 EV@10K/F_4 AK32 GPIO_28_FDO R5021 *EV@10K/F_4 AL31 TS_A DDCCLK_AUX4P DDCDATA_AUX4N DDCCLK_AUX5P DDCCLK_AUX6P DDCDATA_AUX6N 1.8V@8mA DDCVGACLK TSVDD EV@BLM15BD121SN1D_300MA C5039 C5040 C5041 [email protected]/6.3V_6X EV@1U/6.3V_4X [email protected]/10V_4X AJ32 AJ33 T5026 T5027 AM27 AL27 AM19 AL19 T5042 T5045 CRT AN20 AM20 AL30 AM30 T5000 T5035 AL29 AM29 DMINUS DDCDATA_AUX5N +3V_GPU PU:Disable MLPS PD:Enable MLPS AM26 AN26 JTAG_TCK THERMAL on-die thermal sensor power EV@499/F_4 GPIO_12 DEBUG +1.8V_GPU AT23 AR22 GPIO_9_ROMSI C5038 R5018 L5002 AU22 AV21 AF37 AE38 AVSSN#3 DAC1 GPIO_8_ROMSO R5014 EV@499/F_4 R5015 EV@249/F_4 AT21 AR20 T5046 AVSSN#2 GPIO_5_AC_BATT T5024 GPU_VREFG AU20 AT19 AE36 AD35 G B2A Del INT_HDMI_HPD +1.8V_GPU AT17 AR16 AD39 AD37 AVSSN#1 GPIO_1 NC#9 AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24 AU16 AV15 GPIO_0 NC#6 AG32 AG33 AT15 AR14 I2C SDA NC#5 T5013 T5015 AU14 AV13 DVPDATA_23 B R5133 AT33 AU32 DVPDATA_20 R AH17 AJ17 AK17 AJ13 AH15 AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17 AL13 AJ14 AK13 AN13 AR32 AT31 DVPDATA_17 GENERAL PURPOSE I/O AH20 AH18 AN16 [17] GPU_GPIO0 [17] GPU_GPIO1 [17] GPU_GPIO2 AV31 AU30 DVPDATA_11 TX5M_DPD0N R5006 R5007 AR30 AT29 DVPDATA_8 TX5P_DPD0P +3V_GPU AT27 AR26 DVPDATA_5 TX3M_DPD2N AJ23 AH23 AU26 AV25 DVPCLK DVPDATA_0 TX3P_DPD2P Tempeature function: Connect to EC GPU_SMBCLK GPU_SMBDAT AT25 AR24 DVPCNTL_0 GPU_SMBCLK GPU_SMBDAT [34] GPU_SMBCLK [34] GPU_SMBDAT AU24 AV23 TSVDD DDCVGADATA AN21 AM21 AK30 AK29 DDCxx_AUX6x is NC on Seymour AJ30 AJ31 Quanta Computer Inc. TSVSS PROJECT : BY6/BY6D EV@HEATHROW M2 Size Document Number Rev A1A 02_Thames_M2/ GPIO_DP_CRT_I2C Date: Monday, February 13, 2012 Sheet 15 of 47 <VGA> 16 Display phase-locked loop power. 1.8V@75mA Dedicated analog power pin for the display and DISPCLK PLLs. +1.8V_GPU L5003 EV@PBY160808T-501Y-N_1.2A C5042 C5043 [email protected]/6.3V_6X DPE/DPF/LVDS DPLL_PVDD U5000G C5044 EV@1U/6.3V_4X U5000I [email protected]/10V_4X PART 7 0F 9 VARY_BL PART 9 0F 9 LVDS CONTROL DIGON AK27 AJ27 R5022 R5023 EV@10K/F_4 EV@10K/F_4 Display phase-locked loop power. L5004 EV@PBY160808T-501Y-N_1.2A C5046 DPLL_VDDC C5047 [email protected]/6.3V_6X AM32 DPLL_PVDD AN31 DPLL_VDDC AN32 DPLL_PVSS XTALIN AV33 C5045 GPU_XTALIN R5024 EV@1M/F_4 C5048 EV@1U/6.3V_4X EV@27P/50V_4N TXCLK_UP_DPF3P TXCLK_UN_DPF3N Y5000 EV@27MHZ_20 TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N 1 +1V_GPU 2 1V@140mA Dedicated digital power pin for the display PLLs. [email protected]/10V_4X TXOUT_U1P_DPF1P XTALOUT AU34 GPU_XTALOUT R5025 EV@0_4 C5049 EV@27P/50V_4N TXOUT_U1N_DPF1N TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N L5005 EV@PBY160808T-501Y-N_1.2A MPLL_PVDD TXOUT_U3P MPLL_PVDD C5050 C5051 C5052 [email protected]/6.3V_6X EV@1U/6.3V_4X [email protected]/10V_4X AM10 SPLL_PVDD AN9 SPLL_VDDC PLLS/XTAL +1.8V_GPU XO_IN AW34 T5040 XO_IN2 AW35 T5041 TXOUT_U3N TXCLK_LP_DPE3P TXCLK_LN_DPE3N TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N AN10 Engine phase-locked loop power. SPLL_PVSS TXOUT_L1P_DPE1P 1.8V@75mA Dedicated analog power pin for the engine and UVD PLLs. +1.8V_GPU L5006 EV@BLM15BD121SN1D_300MA TXOUT_L1N_DPE1N SPLL_PVDD TXOUT_L2P_DPE0P CLKTESTA AF30 AF31 C5053 C5054 C5055 [email protected]/6.3V_6X EV@1U/6.3V_4X [email protected]/10V_4X NC_XTAL_PVDD CLKTESTB AK10 AL10 CLKTESTA CLKTESTB TXOUT_L2N_DPE0N NC_XTAL_PVSS TXOUT_L3P TXOUT_L3N C5056 *[email protected]/10V_4X L5007 EV@PBY160808T-501Y-N_1.2A AG38 AH37 AF35 AG36 AP34 AR34 AW37 AU35 AR37 AU39 AP35 AR35 AN36 AP37 EV@HEATHROW M2 EV@HEATHROW M2 R5026 *[email protected]/F_4 SPLL_VDDC C5058 C5059 C5060 [email protected]/6.3V_6X EV@1U/6.3V_4X [email protected]/10V_4X DPLL_PVDD Brazos use DPF interface to LVDS display AH35 AJ36 C5057 *[email protected]/10V_4X Engine phase-locked loop power. 1V@150mADedicated digital power pin for the engine and UVD PLLs. +1V_GPU AJ38 AK37 MPLL_PVDD LVTMDP H7 H8 Memory phase-locked loop power. 1.8V@150mA Dedicated analog power pin for the memory PLLs. AK35 AL36 R5028 *EV@0_4 R5029 *EV@0_4 R5027 *[email protected]/F_4 Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev A1A Thames_M2/ XTAL_LVDS Date: Monday, February 13, 2012 Sheet 16 of 47 <VGA> [15] RAM_STRAP0 +3V_GPU [15] GPU_GPIO0 [15] GPU_GPIO1 [15] GPU_GPIO2 [15] GPU_GPIO9 [15] GPU_GPIO11 [15] GPU_GPIO12 [15] GPU_GPIO13 [15] GPU_GPIO22 [15] GENIL_VSYNC [15] GENIL_CLK [15] GPU_GPIO8 [15] GPU_GPIO21 [15] GPU_GENERICC [15] GPU_GPIO10 R5030 EV@10K/F_4 R5031 EV@10K/F_4 R5032 *EV@10K/F_4 R5033 *EV@10K/F_4 R5034 EV@10K/F_4 R5035 *EV@10K/F_4 R5036 *EV@10K/F_4 R5038 *EV@10K/F_4 R5039 *EV@10K/F_4 [15] RAM_STRAP1 [15] RAM_STRAP2 R5047 Sam@10K/F_4 R5048 Hyn@10K/F_4 R5137 AMD@10K/F_4 R5049 AMD@10K/F_4 R5050 Sam@10K/F_4 R5139 Hyn@10K/F_4 R5051 2G@10K/F_4 +1.8V_GPU R5134 1G8@10K/F_4 +1.8V_GPU R5052 512M@10K/F_4 R5135 1G4@10K/F_4 R5151 4G@10K/F_4 CONFIGURATION STRAPS -- SEE EACH DATABOOK FOR STRAP DETAILS ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET +1.8V_GPU R5043 *EV@10K/F_4 R5044 *EV@10K/F_4 R5053 1G4@10K/F_4 +1.8V_GPU R5045 *EV@10K/F_4 R5138 2G@10K/F_4 +1.8V_GPU R5046 *EV@10K/F_4 R5054 512M@10K/F_4 R5145 *EV@10K/F_4 R5152 1G8@10K/F_4 R5153 4G@10K/F_4 R5055 4G@10K/F_4 R5056 512M@10K/F_4 R5154 1G4@10K/F_4 R5155 1G8@10K/F_4 R5156 2G@10K/F_4 [15] RAM_STRAP3 [15] RAM_STRAP4 17 +1.8V_GPU MLPS GPIO PIN DESCRIPTION OF DEFAULT SETTINGS MLPS_DISABLE NA GPIO_28_FDO Enable MLPS, NA for Thames/Whistler/Seymour 0: Enable MLPS, disable GPIO PINSTRAP 1: Disable MLPS, enable GPIO PINSTRAP TX_PWRS_ENB PS_1[4] GPIO0 Transmitter Power Savings Enable 0: 50% Tx output swing 1: Full Tx output swing TX_DEEMPH_EN PS_1[5] GPIO1 PCIE Transmitter De-emphasis Enable 0: Tx de-emphasis disabled 1: Tx de-emphasis enabled X BIF_GEN3_EN_A PS_1[1] GPIO2 PCIE Gen3 Enable (NOTE: RESERVED for Thames/Whistler/Seymour) 0: GEN3 not supported at power-on 1: GEN3 supported at power-on 1 BIF_VGA DIS PS_2[4] GPIO9 VGA Control 0: VGA controller capacity enabled 1: VGA controller capacity disabled (for multi-GPU) 0 ROMIDCFG[2:0] PS_0[3..1] GPIO[13:11] BIOS_ROM_EN PS_2[3] NA NA H5TQ1G63DFR-11C (64M*16) STN B/S P/N AKD5LZWTW02 AKD5LZWTW02 Hynix H5TQ2G63BFR-11C (128M*16) H5TQ4G****** (256M*16) K4W1G1646G-BC11 (64M*16) Samsung AMD Size *4 512MB 0 0 0 DVPDATA_1 DVPDATA_0 0 0 *8 1GB 0 0 1 0 0 AKD5MGWTW00 * 4 1GB 0 1 0 0 0 AKD5MGWTW00 * 8 2GB 0 1 1 0 0 AK************* *8 4GB 1 0 0 0 0 AKD5EGGT500 *4 512MB 0 0 0 0 1 AKD5EGGT500 *8 1GB 0 0 1 0 1 AKD5MGWT500 * 4 1GB 0 1 0 0 1 Enable external BIOS ROM device 0: Disabled 1: Enabled X HSYNC VSYNC 00 - No audio function 01 - Audio for DP only 10 - Audio for DP and HDMI if dongle is detected 11 - Audio for both DP and HDMI HDMI must only be enabled on systems that are legally entitled. It is the responsibility of the system designer to ensure that the system is entitled to support this feature. XX Enable CEC function. Reserved for Thames/Whistler/Seymour 0: Disabled 1: Enabled 2GB 0 1 1 0 1 K4W4G****** (256M*16) AK************* *8 4GB 1 0 0 0 1 23EY2387MC11 (64M*16) AKD5EZWT700 *4 512MB 0 0 0 1 0 AKD5EZWT700 *8 1GB 0 0 1 1 0 *4 1GB 0 1 0 1 0 AKD5DZWT700 * 8 2GB 0 1 1 1 0 AK************* 4GB 1 0 0 1 0 23EY********** (256M*16) *4 PS_0[4] GENLK_VSYNC RESERVED RESERVED RESERVED RESERVED PS_1[3] PS_1[2] NA NA GENLK_CLK GPIO8 GPIO21 GENERICC X NOTE: ALLOW FOR PULLUP PADS FOR THE RESERVED STRAPS BUT DO NOT INSTALL RESISTOR IF THESE GPIOS ARE USEED, THEY MUST KEEP LOW AND NOT CONFLICT DURING RESET AUD_PORT_CONN_PINSTRAP[2] PS_3[5] AUD_PORT_CONN_PINSTRAP[1] PS_3[4] AUD_PORT_CONN_PINSTRAP[0] PS_0[5] GPIO9 AKD5MGWT500 * 8 AKD5DZWT700 CEC_DIS NA NA NA 0 0 0 0 Reserved Reserved Reserved Reserved (for Thames/Whistler/Seymour only) XXX STRAPS TO INDICATE THE NUMBER OF AUDIO CAPABLE DISPLAY OUTPUTS 111 = 0 usable endpoints 110 = 1 usable endpoints 101 = 2 usable endpoints 100 = 3 usable endpoints 011 = 4 usable endpoints 010 = 5 usable endpoints 001 = 6 usable endpoints 000 = all endpoints are usable System Memory Aperture size K4W2G1646C-HC11 (128M*16) 23EY4187MC11 (128M*16) Serial ROM type or Memory Aperture Size Select GPIO22 RAM_STRAP4 RAM_STRAP3 RAM_STRAP2 RAM_STRAP1 RAM_STRAP0 DVPDATA_4 DVPDATA_3 DVPDATA_2 X XXX DDR3 Memory TYPE Vendor P/N X If GPIO22 = 0, defines memory aperture size If GPIO22 = 1, defines ROM type 100 - 512Kbit M25P05A (ST) 101 - 1Mbit M25P10A (ST) 101 - 2Mbit M25P20 (ST) 101 - 4Mbit M25P40 (ST) 101 - 8Mbit M25P80 (ST) 100 - 512Kbit Pm25LV512 (Chingis) 101 - 1Mbit Pm25LV010 (Chingis) +1.8V_GPU AUD[1] AUD[0] Vendor Default Setting STRAPS BIOSROM 0 0 0 0 EEPROM GPIO13 GPIO12 GPIO11 ROMIDCFG2 ROMIDCFG1 ROMIDCFG0 128M 256M 64M 32M 0 0 0 0 0 0 1 1 0 1 0 1 Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev A1A Thames_M2/ STRAPS_Thermal Date: Monday, February 13, 2012 Sheet 17 of 47 <VGA> 18 U5000E +1.8V_GPU PCIe IO power. PART 5 0F 9 C5062 C5063 C5064 [email protected]/6.3V_6X [email protected]/6.3V_6X [email protected]/6.3V_6X C5065 [email protected]/6.3V_6X (1.8V@440mA) D3A ([email protected] / DDR3 128bits 900MHz) C5271 *EV@10U/6.3V_6X MEM I/O AC7 AD11 AF7 AG10 AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10 J7 J9 K11 K13 K8 L12 L16 L21 L23 L26 L7 M11 N11 P7 R11 U11 U7 Y11 Y7 C5272 *EV@10U/6.3V_6X Close to C5209 C5080 [email protected]/10V_4X C5084 EV@1U/6.3V_4X C5072 EV@1U/6.3V_4X C5081 [email protected]/10V_4X C5073 EV@1U/6.3V_4X C5082 [email protected]/10V_4X C5074 EV@1U/6.3V_4X C5085 EV@1U/6.3V_4X C5075 EV@1U/6.3V_4X C5083 [email protected]/10V_4X C3A + C5088 [email protected]/10V_4X C5089 [email protected]/10V_4X C5090 [email protected]/10V_4X C5091 [email protected]/10V_4X C5061 EV@100U/6.3V_3528P_E45b NC_PCIE_VDDR VDDR1 NC_PCIE_VDDR VDDR1 NC_PCIE_VDDR VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 PCIE_VDDC VDDR1 PCIE_VDDC VDDR1 PCIE_VDDC VDDR1 PCIE_VDDC VDDR1 PCIE_VDDC VDDR1 PCIE_VDDC VDDR1 PCIE_VDDC VDDR1 PCIE_VDDC VDDR1 PCIE_VDDC VDDR1 PCIE_VDDC VDDR1 PCIE_VDDC VDDR1 PCIE_VDDC VDDR1 VDDR1 BACO BIF_VDDC BIF_VDDC VDDR1 VDDR1 CORE VDDC VDDC VDDR1 VDDC VDDR1 VDDC VDDR1 VDDC VDDR1 VDDC VDDC VDDC EV@BLM15BD121SN1D_300MA VDDC_CT C5099 [email protected]/6.3V_6X I/O power for 3.3-V pins, such as GPIOs. C5100 EV@1U/6.3V_4X C5101 [email protected]/10V_4X AF26 AF27 AG26 AG27 LEVEL TRANSLATION VDDC VDD_CT VDDC VDD_CT VDDC VDD_CT VDDC VDD_CT VDDC VDDC VDDC VDDC +3V_GPU (3.3V@60mA) L5010 C3A I/O EV@FCM1005KF-221T03_300MA C5112 [email protected]/6.3V_6X AF23 AF24 AG23 AG24 VDDR3 C5113 EV@1U/6.3V_4X C5114 EV@1U/6.3V_4X VDDC VDDR3 VDDC VDDR3 VDDC VDDR3 VDDC VDDR3 VDDC VDDC DVP AD12 AF11 AF12 AF13 Power for all DVP pins; DVPDATA_[23:0]—DVO or GPIO. (1.8V@170mA) VDDC VDDR4 L5011 C3A EV@FCM1005KF-221T03_300MA C5125 [email protected]/6.3V_6X VDDC VDDR4 VDDC VDDR4 VDDC VDDR4 C5126 EV@1U/6.3V_4X VDDC AF15 AG11 AG13 AG15 C5127 [email protected]/10V_4X VDDR4 VDDC VDDR4 VDDC VDDR4 VDDC VDDR4 VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI B2A VDDCI VDDCI VOLTAGE SENESE [44] VCORE_VCCSSENSE R9532 *EV@0_4 VCORE_SEN/RTN route a differtial pair. AF28 FB_VDDC AG28 FB_VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI VDDCI [44] VCORE_VSSSENSE R9533 *EV@0_4 AH29 +1V_GPU C5076 EV@1U/6.3V_4X C5077 EV@1U/6.3V_4X C5078 EV@1U/6.3V_4X C5079 EV@1U/6.3V_4X C5086 EV@1U/6.3V_4X C5087 [email protected]/6.3V_6X +BIF_VDDC Separate core power for the PCIe bus logic. In non-BACO designs, connect to VDDC. In BACO designs, must be the same voltage as VDDC when the GPU is operating, N27 T27 C5092 EV@1U/6.3V_4X AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 C5093 [email protected]/6.3V_6X Dedicated core power, provides power to the internal logic. +VGPU_CORE (0.9~1V@30A) C5094 EV@1U/6.3V_4X C5095 EV@1U/6.3V_4X C5096 EV@1U/6.3V_4X C5097 EV@1U/6.3V_4X C5098 EV@1U/6.3V_4X C5102 EV@1U/6.3V_4X C5103 EV@1U/6.3V_4X C5104 EV@1U/6.3V_4X C5105 EV@1U/6.3V_4X C5106 EV@1U/6.3V_4X C5107 EV@1U/6.3V_4X C5108 EV@1U/6.3V_4X C5109 EV@1U/6.3V_4X C5110 EV@1U/6.3V_4X C5111 EV@1U/6.3V_4X C5115 [email protected]/6.3V_6X C5116 [email protected]/6.3V_6X C5117 [email protected]/6.3V_6X C5118 [email protected]/6.3V_6X C5119 [email protected]/6.3V_6X C5120 [email protected]/6.3V_6X C5121 [email protected]/6.3V_6X C5122 [email protected]/6.3V_6X C5123 [email protected]/6.3V_6X C5124 [email protected]/6.3V_6X VDDR4 VDDC +1.8V_GPU C5070 [email protected]/6.3V_6X PCIe digital power supply. VDDR1 VDDC (1.8V@17mA) G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28 C5069 EV@1U/6.3V_4X EV@HCB1608KF-181T15_1.5A VDDR1 VDDC L5009 L5008 C5066 C5067 C5068 [email protected]/10V_4X [email protected]/10V_4X EV@1U/6.3V_4X VDDR1 Level translation between core and I/O, excluding memory receivers. +1.8V_GPU PCIE_VDDR VDDR1 ISOLATED CORE I/O C5071 EV@1U/6.3V_4X AA31 AA32 AA33 NC_PCIE_VDDR AA34 NC_PCIE_VDDR W30 NC_PCIE_VDDR Y31 NC_BIF_VDDC V28 NC_BIF_VDDC W29 PCIE_PVDD AB37 VDDR1 PCIE +1.5V_GPU FB_GND VDDCI VDDCI VDDCI VDDCI VDDCI AH22 AH27 AH28 M26 N24 R18 R21 R23 R26 T17 T20 T22 T24 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28 AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13 Isolated (clean) core power for the l/O logic. ([email protected] / DDR3 128bits 900MHz) VDDCI +VGPU_CORE L5012 EV@HCB1608KF-121T30_3A L5013 EV@HCB1608KF-121T30_3A C5128 EV@1U/6.3V_4X C5129 EV@1U/6.3V_4X C5130 EV@1U/6.3V_4X C5131 EV@1U/6.3V_4X C5132 [email protected]/6.3V_6X C5133 [email protected]/6.3V_6X C5134 [email protected]/6.3V_6X C5135 EV@1U/6.3V_4X C5136 EV@1U/6.3V_4X B2A C5137 EV@1U/6.3V_4X Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev A1A Thames_M2/ MainPower EV@HEATHROW M2 Date: Monday, February 13, 2012 Sheet 18 of 47 19 <VGA> For Thames/Whistler/Seymour For Thames/Whistler/Seymour a dedicated BEAD is required a dedicated BEAD is required for each DPAB_VDD10, DPCD_VDD10, DPEF_VDD10 for each DPAB_VDD18, DPCD_VDD18, DPEF_VDD18 DP/TMDS/LVDS Transmitter Power 0.935V@222mA per port U5000H (1V@222mA) PART 8 0F 9 DP_VDDR DPAB_VDD10 DP_VDDC DP/TMDS/LVDS Transmitter Power DP_VDDC DP_VDDC DP mode: 1.8V@188mA per port HDMI mode: 1.8V@237mA per port DP_VDDC DP_VDDC AN24 AP24 AP25 AP26 AU28 AV29 (1.8V@237mA) +1.8V_GPU L5015 EV@PBY160808T-501Y-N_1.2A C5138 [email protected]/6.3V_6X DPAB_VDD18 C5139 EV@1U/6.3V_4X (1.8V@237mA) +1.8V_GPU L5018 EV@PBY160808T-501Y-N_1.2A C5150 [email protected]/6.3V_6X DPCD_VDD18 C5151 EV@1U/6.3V_4X C5152 [email protected]/10V_4X (1.8V@237mA) +1.8V_GPU L5019 EV@PBY160808T-501Y-N_1.2A DP_VDDR DP_VDDC DP_VDDR DP_VDDC DP_VDDR DP_VDDC DP_VDDR DP_VDDC DPEF_VDD18 DP_VDDC DP_VDDR DP_VDDC DP_VDDR DP_VDDC DP_VDDR DP_VDDR DP GND DP_VDDR DP_VSSR DP_VDDR DP_VSSR DP_VDDR DP_VSSR DP_VDDR DP_VSSR DP_VDDR DP_VSSR DP_VDDR DP_VSSR C5155 [email protected]/10V_4X DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DP_VSSR CALIBRATION DP_VSSR DP_VSSR DP_VSSR EV@150/F_4 AW28 R5058 EV@150/F_4 AW18 DPAB_CALR DP_VSSR DP_VSSR DP_VSSR DP_VSSR DPCD_CALR DP_VSSR DP_VSSR DP_VSSR DP_VSSR R5059 EV@150/F_4 AM39 EV@1U/6.3V_4X [email protected]/10V_4X +1V_GPU (1V@222mA) L5016 EV@PBY160808T-501Y-N_1.2A C5144 C5145 C5146 [email protected]/6.3V_6X EV@1U/6.3V_4X [email protected]/10V_4X +1V_GPU (1V@222mA) L5017 EV@PBY160808T-501Y-N_1.2A +1V_GPU DP_VDDR DP_VSSR R5057 [email protected]/6.3V_6X DPEF_VDD10 DP_VSSR C5154 EV@1U/6.3V_4X C5143 DPCD_VDD10 AL33 AM33 AK33 AK34 DP_VDDR DP_VSSR C5153 [email protected]/6.3V_6X C5142 DP_VDDR DP_VDDC AH34 AJ34 AF34 AG34 AM37 AL38 AP13 AT13 AP14 AP15 EV@PBY160808T-501Y-N_1.2A C5141 DP_VDDR C5140 [email protected]/10V_4X AP20 AP21 AP22 AP23 AU18 AV19 AP31 AP32 AN33 AP33 L5014 DPEF_CALR DP_VSSR DP_VSSR DP_VSSR DP_VSSR AN27 AP27 AP28 AW24 AW26 AN29 AP29 AP30 AW30 AW32 AN17 AP16 AP17 AW14 AW16 AN19 AP18 AP19 AW20 AW22 AN34 AP39 AR39 AU37 AF39 AH39 AK39 AL34 AV27 AR28 AV17 AR18 AN38 AM35 C5147 C5148 C5149 [email protected]/6.3V_6X EV@1U/6.3V_4X [email protected]/10V_4X D3A +1V_GPU C5584 EV@39P/50V_4N C5585 EV@39P/50V_4N EV@HEATHROW M2 Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev A1A Thames_M2/ DP_Powers Date: Monday, February 13, 2012 Sheet 19 of 47 20 <VGA> U5000F PART 6 0F 9 AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39 PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND PCIE_VSS GND GND GND GND GND GND GND GND F15 F17 F19 F21 F23 F25 F27 F29 F31 F33 F7 F9 G2 G6 H9 J2 J27 J6 J8 K14 K7 L11 L17 L2 L22 L24 L6 M17 M22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VSS_MECH GND VSS_MECH GND VSS_MECH A39 AW1 AW39 EV@HEATHROW M2 Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev A1A Thames_M2/ GND Date: Monday, February 13, 2012 Sheet 20 of 47 21 <VGA> [23] VMB_DM[7..0] U5000C [23] VMB_RDQS[7..0] PART 3 0F 9 VMA_DQ[63..0] VMA_DM[7..0] [22] VMA_DM[7..0] VMA_RDQS[7..0] [22] VMA_RDQS[7..0] VMA_WDQS[7..0] [22] VMA_WDQS[7..0] VMA_MA[14..0] [22] VMA_MA[14..0] VMA_BA0 VMA_BA1 VMA_BA2 [22] VMA_BA0 [22] VMA_BA1 [22] VMA_BA2 Place MVREF dividers and Caps close to ASIC +1.5V_GPU (0.7*VDDR1) Ra [23] VMB_WDQS[7..0] GDDR5/DDR3 R5060 [email protected]/F_4 VMA_DQ0 VMA_DQ1 VMA_DQ2 VMA_DQ3 VMA_DQ4 VMA_DQ5 VMA_DQ6 VMA_DQ7 VMA_DQ8 VMA_DQ9 VMA_DQ10 VMA_DQ11 VMA_DQ12 VMA_DQ13 VMA_DQ14 VMA_DQ15 VMA_DQ16 VMA_DQ17 VMA_DQ18 VMA_DQ19 VMA_DQ20 VMA_DQ21 VMA_DQ22 VMA_DQ23 VMA_DQ24 VMA_DQ25 VMA_DQ26 VMA_DQ27 VMA_DQ28 VMA_DQ29 VMA_DQ30 VMA_DQ31 VMA_DQ32 VMA_DQ33 VMA_DQ34 VMA_DQ35 VMA_DQ36 VMA_DQ37 VMA_DQ38 VMA_DQ39 VMA_DQ40 VMA_DQ41 VMA_DQ42 VMA_DQ43 VMA_DQ44 VMA_DQ45 VMA_DQ46 VMA_DQ47 VMA_DQ48 VMA_DQ49 VMA_DQ50 VMA_DQ51 VMA_DQ52 VMA_DQ53 VMA_DQ54 VMA_DQ55 VMA_DQ56 VMA_DQ57 VMA_DQ58 VMA_DQ59 VMA_DQ60 VMA_DQ61 VMA_DQ62 VMA_DQ63 C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10 G8 K9 K10 G9 A8 C8 E8 A6 C6 E6 A5 MVREFDA MVREFSA L18 L20 DQA0_0 MAA0_0/MAA_0 DQA0_1 MAA0_1/MAA_1 DQA0_2 MAA0_2/MAA_2 DQA0_3 MAA0_3/MAA_3 DQA0_4 MAA0_4/MAA_4 DQA0_5 MAA0_5/MAA_5 DQA0_6 MAA0_6/MAA_6 DQA0_7 MAA0_7/MAA_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 MEMORY INTERFACE A [22] VMA_DQ[63..0] MAA1_0/MAA_8 MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12 MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1 G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17 VMA_MA0 VMA_MA1 VMA_MA2 VMA_MA3 VMA_MA4 VMA_MA5 VMA_MA6 VMA_MA7 VMA_MA8 VMA_MA9 VMA_MA10 VMA_MA11 VMA_MA12 VMA_BA2 VMA_BA0 VMA_BA1 A32 C32 D23 E22 C14 A14 E10 D9 VMA_DM0 VMA_DM1 VMA_DM2 VMA_DM3 VMA_DM4 VMA_DM5 VMA_DM6 VMA_DM7 [23] VMB_MA[14..0] [23] VMB_BA0 [23] VMB_BA1 [23] VMB_BA2 DQA0_16 DQA0_17 WCKA0_0/DQMA_0 DQA0_18 WCKA0B_0/DQMA_1 DQA0_19 WCKA0_1/DQMA_2 DQA0_20 WCKA0B_1/DQMA_3 DQA0_21 WCKA1_0/DQMA_4 DQA0_22 WCKA1B_0/DQMA_5 DQA0_23 WCKA1_1/DQMA_6 DQA0_24 WCKA1B_1/DQMA_7 DQA0_25 DQA0_26 EDCA0_0/QSA_0 DQA0_27 EDCA0_1/QSA_1 DQA0_28 EDCA0_2/QSA_2 DQA0_29 EDCA0_3/QSA_3 DQA0_30 EDCA1_0/QSA_4 DQA0_31 EDCA1_1/QSA_5 DQA1_0 EDCA1_2/QSA_6 DQA1_1 EDCA1_3/QSA_7 C34 D29 D25 E20 E16 E12 J10 D7 VMA_RDQS0 VMA_RDQS1 VMA_RDQS2 VMA_RDQS3 VMA_RDQS4 VMA_RDQS5 VMA_RDQS6 VMA_RDQS7 A34 E30 E26 C20 C16 C12 J11 F8 VMA_WDQS0 VMA_WDQS1 VMA_WDQS2 VMA_WDQS3 VMA_WDQS4 VMA_WDQS5 VMA_WDQS6 VMA_WDQS7 DQA1_2 DQA1_3 DDBIA0_0/QSA_0B DQA1_4 DDBIA0_1/QSA_1B DQA1_5 DDBIA0_2/QSA_2B DQA1_6 DDBIA0_3/QSA_3B DQA1_7 DDBIA1_0/QSA_4B DQA1_8 DDBIA1_1/QSA_5B DQA1_9 DDBIA1_2/QSA_6B DQA1_10 DDBIA1_3/QSA_7B DQA1_11 DQA1_12 ADBIA0/ODTA0 DQA1_13 ADBIA1/ODTA1 J21 G19 DQA1_14 DQA1_15 CLKA0 DQA1_16 CLKA0B H27 VMA_CLK0 G27 VMA_CLK0# DQA1_17 DQA1_18 CLKA1 DQA1_19 CLKA1B J14 VMA_CLK1 H14 VMA_CLK1# VMA_ODT0 [22] VMA_ODT1 [22] VMA_CLK0 [22] VMA_CLK0# [22] VMA_CLK1 [22] VMA_CLK1# [22] DQA1_20 DQA1_21 RASA0B DQA1_22 RASA1B K23 VMA_RAS0# K19 VMA_RAS1# DQA1_23 DQA1_24 CASA0B DQA1_25 CASA1B K20 VMA_CAS0# K17 VMA_CAS1# VMA_RAS0# [22] VMA_RAS1# [22] VMA_CAS0# [22] VMA_CAS1# [22] Place MVREF dividers and Caps close to ASIC +1.5V_GPU DQA1_26 DQA1_27 CSA0B_0 DQA1_28 CSA0B_1 K24 VMA_CS0# K27 (0.7*VDDR1) VMA_CS0# [22] DQA1_29 DQA1_30 CSA1B_0 DQA1_31 CSA1B_1 M13 VMA_CS1# K16 VMA_CS1# [22] Ra R5061 [email protected]/F_4 VMB_DQ[63..0] VMB_DM[7..0] U5000D VMB_RDQS[7..0] PART 4 0F 9 VMB_WDQS[7..0] VMB_MA[14..0] VMB_BA0 VMB_BA1 VMB_BA2 VMB_DQ0 VMB_DQ1 VMB_DQ2 VMB_DQ3 VMB_DQ4 VMB_DQ5 VMB_DQ6 VMB_DQ7 VMB_DQ8 VMB_DQ9 VMB_DQ10 VMB_DQ11 VMB_DQ12 VMB_DQ13 VMB_DQ14 VMB_DQ15 VMB_DQ16 VMB_DQ17 VMB_DQ18 VMB_DQ19 VMB_DQ20 VMB_DQ21 VMB_DQ22 VMB_DQ23 VMB_DQ24 VMB_DQ25 VMB_DQ26 VMB_DQ27 VMB_DQ28 VMB_DQ29 VMB_DQ30 VMB_DQ31 VMB_DQ32 VMB_DQ33 VMB_DQ34 VMB_DQ35 VMB_DQ36 VMB_DQ37 VMB_DQ38 VMB_DQ39 VMB_DQ40 VMB_DQ41 VMB_DQ42 VMB_DQ43 VMB_DQ44 VMB_DQ45 VMB_DQ46 VMB_DQ47 VMB_DQ48 VMB_DQ49 VMB_DQ50 VMB_DQ51 VMB_DQ52 VMB_DQ53 VMB_DQ54 VMB_DQ55 VMB_DQ56 VMB_DQ57 VMB_DQ58 VMB_DQ59 VMB_DQ60 VMB_DQ61 VMB_DQ62 VMB_DQ63 C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5 DQB0_0 GDDR5/DDR3 MAB0_0/MAB_0 DQB0_1 MAB0_1/MAB_1 DQB0_2 MAB0_2/MAB_2 DQB0_3 MAB0_3/MAB_3 DQB0_4 MAB0_4/MAB_4 DQB0_5 MAB0_5/MAB_5 DQB0_6 MAB0_6/MAB_6 DQB0_7 MAB0_7/MAB_7 DQB0_8 MAB1_0/MAB_8 DQB0_9 MAB1_1/MAB_9 DQB0_10 MAB1_2/MAB_10 DQB0_11 MAB1_3/MAB_11 DQB0_12 MAB1_4/MAB_12 DQB0_13 MAB1_5/BA2 DQB0_14 MAB1_6/BA0 DQB0_15 MAB1_7/BA1 DQB0_16 MEMORY INTERFACE B [23] VMB_DQ[63..0] DQB0_17 DQB0_18 DQB0_19 DQB0_20 DQB0_21 DQB0_22 DQB0_23 DQB0_24 WCKB0_0/DQMB_0 WCKB0B_0/DQMB_1 WCKB0_1/DQMB_2 WCKB0B_1/DQMB_3 WCKB1_0/DQMB_4 WCKB1B_0/DQMB_5 WCKB1_1/DQMB_6 WCKB1B_1/DQMB_7 CKEA0 MVREFSA CKEA1 K21 VMA_CKE0 J20 VMA_CKE1 MVREFDB MVREFSB VMA_CKE0 [22] VMA_CKE1 [22] Y12 AA12 DQB0_26 EDCB0_0/QSB_0 DQB0_27 EDCB0_1/QSB_1 DQB0_28 EDCB0_2/QSB_2 DQB0_29 EDCB0_3/QSB_3 DQB0_30 EDCB1_0/QSB_4 DQB0_31 EDCB1_1/QSB_5 DQB1_0 EDCB1_2/QSB_6 DQB1_1 Rb R5062 EV@100/F_4 C5156 EV@1U/6.3V_4X R5063 R5065 R5066 L27 Thames@243/F_4 Seymour@243/F_4 N12 Thames@243/F_4 AG12 R5067 R5068 R5069 Seymour@243/F_4 M12 Thames@243/F_4 M27 Thames@243/F_4 AH12 NC_MEM_CALRN0 WEA0B NC_MEM_CALRN1 WEA1B K26 VMA_WE0# L15 VMA_WE1# NC_MEM_CALRN2 VMA_WE0# [22] VMA_WE1# [22] EDCB1_3/QSB_7 DQB1_3 DDBIB0_0/QSB_0B DQB1_4 DDBIB0_1/QSB_1B DQB1_5 DDBIB0_2/QSB_2B DQB1_6 DDBIB0_3/QSB_3B DQB1_7 DDBIB1_0/QSB_4B DQB1_8 DDBIB1_1/QSB_5B DQB1_9 DDBIB1_2/QSB_6B DQB1_10 MAA0_8/MAA_13 DDBIB1_3/QSB_7B DQB1_12 ADBIB0/ODTB0 DQB1_13 R5064 EV@100/F_4 MEM_CALRP0 MAA1_8/MAA_14 MEM_CALRP2 MAA0_9/MAA_15 MAA1_9/RSVD +1.5V_GPU ADBIB1/ODTB1 DQB1_15 CLKB0 DQB1_16 VMB_RDQS0 VMB_RDQS1 VMB_RDQS2 VMB_RDQS3 VMB_RDQS4 VMB_RDQS5 VMB_RDQS6 VMB_RDQS7 QSB[7..0] G7 K1 P1 W4 AC4 AH3 AJ8 AM3 VMB_WDQS0 VMB_WDQS1 VMB_WDQS2 VMB_WDQS3 VMB_WDQS4 VMB_WDQS5 VMB_WDQS6 VMB_WDQS7 QSB#[7..0] T7 W7 CLKB0B L9 L8 VMB_ODT0 [23] VMB_ODT1 [23] VMB_CLK0 VMB_CLK0# VMB_CLK0 [23] VMB_CLK0# [23] DQB1_17 DQB1_18 CLKB1 DQB1_19 CLKB1B AD8 VMB_CLK1 AD7 VMB_CLK1# VMB_CLK1 [23] VMB_CLK1# [23] DQB1_20 DQB1_21 RASB0B DQB1_22 RASB1B T10 VMB_RAS0# Y10 VMB_RAS1# VMB_RAS0# [23] VMB_RAS1# [23] DQB1_23 DQB1_24 CASB0B DQB1_25 CASB1B W10 VMB_CAS0# AA10 VMB_CAS1# VMB_CAS0# [23] VMB_CAS1# [23] DQB1_26 DQB1_27 CSB0B_0 DQB1_28 CSB0B_1 P10 VMB_CS0# L10 VMB_CS0# [23] AD10 VMB_CS1# AC10 VMB_CS1# [23] DQB1_29 DQB1_30 CSB1B_0 DQB1_31 CSB1B_1 MVREFDB CKEB1 U10 VMB_CKE0 AA11 VMB_CKE1 VMB_CKE0 [23] VMB_CKE1 [23] MVREFSB N10 VMB_WE0# AB11 VMB_WE1# VMB_WE0# [23] VMB_WE1# [23] C5157 EV@1U/6.3V_4X H23 VMA_MA13 J19 VMA_MA14 M21 M20 MAB1_8/MAB_14 MAB0_9/MAB_15 MAB1_9/RSVD +1.5V_GPU (0.7*VDDR1) F6 K3 P3 V5 AB5 AH1 AJ9 AM5 DQB1_14 WEB1B Rb VMB_DM0 VMB_DM1 VMB_DM2 VMB_DM3 VMB_DM4 VMB_DM5 VMB_DM6 VMB_DM7 DQB1_11 MAB0_8/MAB_13 NC_MEM_CALRP1 H3 H1 T3 T5 AE4 AF5 AK6 AK5 DQB1_2 WEB0B +1.5V_GPU VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_BA2 VMB_BA0 VMB_BA1 DQB0_25 CKEB0 MVREFDA P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9 DRAM_RST T8 VMB_MA13 W8 VMB_MA14 U12 V12 AH11 GPU_DRAM_RST (0.7*VDDR1) EV@HEATHROW M2 Ra Rb R5070 [email protected]/F_4 R5072 EV@100/F_4 Ra R5071 [email protected]/F_4 Rb R5073 EV@100/F_4 EV@HEATHROW M2 C5158 EV@1U/6.3V_4X Ball Name Thames MEM_CALRN0 243R MEM_CALRN1 X Seymour X 243R MEM_CALRN2 243R X MEM_CALRP0 243R X MEM_CALRP1 X 243R MEM_CALRP2 243R X C5159 EV@1U/6.3V_4X 25mm (max) 5mm (max) 25mm (max) D3A GPU_DRAM_RST R5074 EV@10/F_4 R5075 EV@51/F_4 MEM_RST# [22,23] C5160 R5076 [email protected]/F_4 EV@120P/50V_4N Place all these componets very close to GPU (within 25mm) and keep all components close to each other ** This basic topology should be used for DRAM_RAT for DDR3/GDDR5 These Capacitors and Resistor values arre an example only The series R and || cap values will depend on the DRAM loads and will have to be calculated for differrent Memory, DRAM loads and board to pass Reset Signal Spec Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev A1A Thames_M2/ MEM Interface Date: Tuesday, February 14, 2012 Sheet 21 of 47 5 4 3 VMA_DM[7..0] [21] VMA_DM[7..0] [21] VMA_RDQS[7..0] [21] VMA_WDQS[7..0] VMA_RDQS[7..0] QSA[7..0] VMA_WDQS[7..0] QSA#[7..0] U5002 VREFC_VMA1 M8 VREFD_VMA1 H1 [21] VMA_MA0 [21] VMA_MA1 [21] VMA_MA2 [21] VMA_MA3 [21] VMA_MA4 [21] VMA_MA5 [21] VMA_MA6 [21] VMA_MA7 [21] VMA_MA8 [21] VMA_MA9 [21] VMA_MA10 [21] VMA_MA11 [21] VMA_MA12 [21] VMA_MA13 [21] VMA_MA14 D [21] VMA_BA0 [21] VMA_BA1 [21] VMA_BA2 [21] VMA_CLK0 [21] VMA_CLK0# [21] VMA_CKE0 [21] VMA_ODT0 [21] VMA_CS0# [21] VMA_RAS0# [21] VMA_CAS0# [21] VMA_WE0# C [21,23] MEM_RST# 1 22 <VGA> U5004 VMA_MA[14..0] [21] VMA_MA[14..0] 2 CHANNEL A: 512MB DDR3 (64M*16*4pcs) VMA_DQ[63..0] [21] VMA_DQ[63..0] VMA_MA0 VMA_MA1 VMA_MA2 VMA_MA3 VMA_MA4 VMA_MA5 VMA_MA6 VMA_MA7 VMA_MA8 VMA_MA9 VMA_MA10 VMA_MA11 VMA_MA12 VMA_MA13 VMA_MA14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 VMA_BA0 VMA_BA1 VMA_BA2 M2 N8 M3 VMA_CLK0 VMA_CLK0# VMA_CKE0 J7 K7 K9 VMA_ODT0 VMA_CS0# VMA_RAS0# VMA_CAS0# VMA_WE0# K1 L2 J3 K3 L3 VMA_RDQS0 VMA_RDQS3 F3 C7 VMA_DM0 VMA_DM3 E7 D3 VMA_WDQS0 VMA_WDQS3 G3 B7 MEM_RST# T2 VMA_ZQ1 L8 VREFCA VREFDQ DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 CK CK CKE DQSL DQSU VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 DML DMU VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 DQSL DQSU RESET ZQ NC#J1 NC#L1 NC#J9 NC#L9 E3 F7 F2 F8 H3 H8 G2 H7 VMA_DQ5 VMA_DQ0 VMA_DQ6 VMA_DQ1 VMA_DQ4 VMA_DQ3 VMA_DQ7 VMA_DQ2 D7 C3 C8 C2 A7 A2 B8 A3 VMA_DQ24 VMA_DQ31 VMA_DQ27 VMA_DQ28 VMA_DQ25 VMA_DQ29 VMA_DQ26 VMA_DQ30 VREFC_VMA2 VREFD_VMA2 M8 H1 VMA_MA0 VMA_MA1 VMA_MA2 VMA_MA3 VMA_MA4 VMA_MA5 VMA_MA6 VMA_MA7 VMA_MA8 VMA_MA9 VMA_MA10 VMA_MA11 VMA_MA12 VMA_MA13 VMA_MA14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 VMA_BA0 VMA_BA1 VMA_BA2 M2 N8 M3 VMA_CLK0 VMA_CLK0# VMA_CKE0 J7 K7 K9 +1.5V_GPU BA0 BA1 BA2 R5077 Thames@243/F_4 J1 L1 J9 L9 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 ODT CS RAS CAS WE U5005 U5003 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VMA_ODT0 VMA_CS0# VMA_RAS0# VMA_CAS0# VMA_WE0# K1 L2 J3 K3 L3 VMA_RDQS1 VMA_RDQS2 F3 C7 VMA_DM1 VMA_DM2 E7 D3 VMA_WDQS1 VMA_WDQS2 G3 B7 MEM_RST# T2 VMA_ZQ2 B1 B9 D1 D8 E2 E8 F9 G1 G9 L8 VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 100-BALL SDRAM DDR3 EV@VRAM _DDR3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 CK CK CKE ODT CS RAS CAS WE DQSL DQSU VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 DML DMU VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 DQSL DQSU RESET ZQ NC#J1 NC#L1 NC#J9 NC#L9 E3 F7 F2 F8 H3 H8 G2 H7 D7 C3 C8 C2 A7 A2 B8 A3 VMA_DQ12 VMA_DQ14 VMA_DQ8 VMA_DQ11 VMA_DQ10 VMA_DQ15 VMA_DQ9 VMA_DQ13 VMA_DQ20 VMA_DQ19 VMA_DQ23 VMA_DQ17 VMA_DQ22 VMA_DQ16 VMA_DQ21 VMA_DQ18 VREFC_VMA3 VREFD_VMA3 M8 H1 VMA_MA0 VMA_MA1 VMA_MA2 VMA_MA3 VMA_MA4 VMA_MA5 VMA_MA6 VMA_MA7 VMA_MA8 VMA_MA9 VMA_MA10 VMA_MA11 VMA_MA12 VMA_MA13 VMA_MA14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 VMA_BA0 VMA_BA1 VMA_BA2 M2 N8 M3 VMA_CLK1 VMA_CLK1# VMA_CKE1 J7 K7 K9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B2 D9 G7 K2 K8 N1 N9 R1 R9 [21] VMA_CLK1 [21] VMA_CLK1# [21] VMA_CKE1 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 VMA_DQ54 VMA_DQ50 VMA_DQ53 VMA_DQ49 VMA_DQ52 VMA_DQ51 VMA_DQ55 VMA_DQ48 VREFC_VMA4 VREFD_VMA4 M8 H1 VMA_MA0 VMA_MA1 VMA_MA2 VMA_MA3 VMA_MA4 VMA_MA5 VMA_MA6 VMA_MA7 VMA_MA8 VMA_MA9 VMA_MA10 VMA_MA11 VMA_MA12 VMA_MA13 VMA_MA14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 D7 C3 C8 C2 A7 A2 B8 A3 VMA_DQ32 VMA_DQ36 VMA_DQ33 VMA_DQ37 VMA_DQ34 VMA_DQ39 VMA_DQ35 VMA_DQ38 VMA_BA0 VMA_BA1 VMA_BA2 M2 N8 M3 VMA_CLK1 VMA_CLK1# VMA_CKE1 J7 K7 K9 A1 A8 C1 C9 D2 E9 F1 H2 H9 VMA_ODT1 VMA_CS1# VMA_RAS1# VMA_CAS1# VMA_WE1# K1 L2 J3 K3 L3 VMA_RDQS5 VMA_RDQS7 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VMA_DM5 VMA_DM7 E7 D3 VMA_WDQS5 VMA_WDQS7 G3 B7 MEM_RST# T2 +1.5V_GPU VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 VMA_DQ46 VMA_DQ45 VMA_DQ44 VMA_DQ40 VMA_DQ41 VMA_DQ42 VMA_DQ43 VMA_DQ47 D7 C3 C8 C2 A7 A2 B8 A3 VMA_DQ61 VMA_DQ58 VMA_DQ63 VMA_DQ56 VMA_DQ60 VMA_DQ59 VMA_DQ62 VMA_DQ57 D BA0 BA1 BA2 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 CK CK CKE B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU +1.5V_GPU BA0 BA1 BA2 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 CK CK CKE B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU +1.5V_GPU [21] VMA_ODT1 [21] VMA_CS1# [21] VMA_RAS1# [21] VMA_CAS1# [21] VMA_WE1# A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VMA_ODT1 VMA_CS1# VMA_RAS1# VMA_CAS1# VMA_WE1# K1 L2 J3 K3 L3 VMA_RDQS6 VMA_RDQS4 F3 C7 VMA_DM6 VMA_DM4 E7 D3 VMA_WDQS6 VMA_WDQS4 G3 B7 MEM_RST# T2 VMA_ZQ3 B1 B9 D1 D8 E2 E8 F9 G1 G9 L8 ODT CS RAS CAS WE VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 DQSL DQSU DML DMU VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 DQSL DQSU RESET ZQ VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 R5079 Thames@243/F_4 J1 L1 J9 L9 100-BALL SDRAM DDR3 EV@VRAM _DDR3 TOP Left VREFCA VREFDQ +1.5V_GPU BA0 BA1 BA2 R5078 Thames@243/F_4 J1 L1 J9 L9 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 BOT Left Group-A0 VREF NC#J1 NC#L1 NC#J9 NC#L9 VMA_ZQ4 B1 B9 D1 D8 E2 E8 F9 G1 G9 L8 ODT CS RAS CAS WE DQSL DQSU DML DMU VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 DQSL DQSU RESET ZQ R5080 Thames@243/F_4 J1 L1 J9 L9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 NC#J1 NC#L1 NC#J9 NC#L9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 C B1 B9 D1 D8 E2 E8 F9 G1 G9 100-BALL SDRAM DDR3 EV@VRAM _DDR3 100-BALL SDRAM DDR3 EV@VRAM _DDR3 BOT Right TOP Right Group-A1 VREF +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU +1.5V_GPU B B R5081 [email protected]/F_4 R5082 [email protected]/F_4 VREFC_VMA1 R5083 [email protected]/F_4 VREFD_VMA1 R5084 [email protected]/F_4 VREFC_VMA2 R5085 [email protected]/F_4 R5086 [email protected]/F_4 R5088 [email protected]/F_4 VREFD_VMA2 VREFC_VMA3 R5089 C5161 R5090 C5162 R5091 C5163 R5092 C5164 [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X Group-A0 decoupling CAP MEM_A0 CLK R5087 [email protected]/F_4 VREFD_VMA3 VREFC_VMA4 VREFD_VMA4 R5093 C5165 R5094 C5166 R5095 C5167 R5096 C5168 [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X Group-A1 decoupling CAP MEM_A1 CLK +1.5V_GPU +1.5V_GPU VMA_CLK0 VMA_CLK1 VMA_CLK0# C3A R5097 [email protected]/F_4 C5169 EV@1U/6.3V_4X C5170 EV@1U/6.3V_4X C5171 EV@1U/6.3V_4X C5178 EV@1U/6.3V_4X C5179 EV@1U/6.3V_4X C5180 EV@1U/6.3V_4X C5181 EV@1U/6.3V_4X C5172 EV@1U/6.3V_4X C5182 EV@1U/6.3V_4X C5173 EV@1U/6.3V_4X C5174 EV@1U/6.3V_4X C5175 EV@1U/6.3V_4X C5176 EV@1U/6.3V_4X C5177 EV@1U/6.3V_4X C5183 EV@1U/6.3V_4X VMA_CLK1# C5184 EV@1U/6.3V_4X C3A R5098 [email protected]/F_4 R5099 [email protected]/F_4 +1.5V_GPU R5100 [email protected]/F_4 +1.5V_GPU C5189 [email protected]/25V_4X C5186 EV@1U/6.3V_4X A C5187 EV@1U/6.3V_4X C5188 EV@1U/6.3V_4X C5196 EV@1U/6.3V_4X C5197 EV@1U/6.3V_4X C5198 EV@1U/6.3V_4X C5199 EV@1U/6.3V_4X C5190 EV@1U/6.3V_4X C5200 EV@1U/6.3V_4X C5191 EV@1U/6.3V_4X C5192 EV@1U/6.3V_4X C5193 EV@1U/6.3V_4X C5194 EV@1U/6.3V_4X C5195 EV@1U/6.3V_4X C5201 EV@1U/6.3V_4X C5202 EV@1U/6.3V_4X C5185 [email protected]/25V_4X A +1.5V_GPU +1.5V_GPU C5203 [email protected]/6.3V_6X C5204 [email protected]/6.3V_6X C5205 [email protected]/6.3V_6X C5206 [email protected]/6.3V_6X C5208 [email protected]/6.3V_6X C5207 [email protected]/6.3V_6X C5209 [email protected]/6.3V_6X C5210 [email protected]/6.3V_6X C5211 [email protected]/6.3V_6X C5212 [email protected]/6.3V_6X Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Date: Monday, February 13, 2012 Rev A1A VRAM_A: DDR3*4PCS 5 4 3 2 1 Sheet 22 of 47 5 3 2 CHANNEL B: 512MB DDR3 (64M*16*4pcs) VMB_DQ[63..0] [21] VMB_DQ[63..0] 1 23 <VGA> VMB_DM[7..0] [21] VMB_DM[7..0] [21] VMB_RDQS[7..0] [21] VMB_WDQS[7..0] VMB_RDQS[7..0] QSA[7..0] VMB_WDQS[7..0] QSA#[7..0] U5006 U5007 U5008 U5009 VMB_MA[14..0] [21] VMB_MA[14..0] [21] VMB_MA0 [21] VMB_MA1 [21] VMB_MA2 [21] VMB_MA3 [21] VMB_MA4 [21] VMB_MA5 [21] VMB_MA6 [21] VMB_MA7 [21] VMB_MA8 [21] VMB_MA9 [21] VMB_MA10 [21] VMB_MA11 [21] VMB_MA12 [21] VMB_MA13 [21] VMB_MA14 D 4 [21] VMB_BA0 [21] VMB_BA1 [21] VMB_BA2 [21] VMB_CLK0 [21] VMB_CLK0# [21] VMB_CKE0 [21] VMB_ODT0 [21] VMB_CS0# [21] VMB_RAS0# [21] VMB_CAS0# [21] VMB_WE0# C [21,22] MEM_RST# VREFC_VMB1 VREFD_VMB1 M8 H1 VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13 VMB_MA14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 VMB_BA0 VMB_BA1 VMB_BA2 M2 N8 M3 VMB_CLK0 VMB_CLK0# VMB_CKE0 J7 K7 K9 VMB_ODT0 VMB_CS0# VMB_RAS0# VMB_CAS0# VMB_WE0# K1 L2 J3 K3 L3 VMB_RDQS2 VMB_RDQS3 F3 C7 VMB_DM2 VMB_DM3 E7 D3 VMB_WDQS2 VMB_WDQS3 G3 B7 MEM_RST# T2 VMB_ZQ1 VREFCA VREFDQ DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 CK CK CKE ODT CS RAS CAS WE VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 DQSL DQSU DML DMU VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 DQSL DQSU RESET ZQ VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 R5101 Thames@243/F_4 J1 L1 J9 L9 VMB_DQ23 VMB_DQ16 VMB_DQ21 VMB_DQ17 VMB_DQ22 VMB_DQ19 VMB_DQ20 VMB_DQ18 D7 C3 C8 C2 A7 A2 B8 A3 VMB_DQ26 VMB_DQ30 VMB_DQ28 VMB_DQ31 VMB_DQ24 VMB_DQ27 VMB_DQ25 VMB_DQ29 VREFC_VMB2 VREFD_VMB2 M8 H1 VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13 VMB_MA14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 VMB_BA0 VMB_BA1 VMB_BA2 M2 N8 M3 VMB_CLK0 VMB_CLK0# VMB_CKE0 J7 K7 K9 +1.5V_GPU BA0 BA1 BA2 L8 E3 F7 F2 F8 H3 H8 G2 H7 NC#J1 NC#L1 NC#J9 NC#L9 B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU A1 A8 C1 C9 D2 E9 F1 H2 H9 VMB_ODT0 VMB_CS0# VMB_RAS0# VMB_CAS0# VMB_WE0# K1 L2 J3 K3 L3 VMB_RDQS0 VMB_RDQS1 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VMB_DM0 VMB_DM1 E7 D3 VMB_WDQS0 VMB_WDQS1 G3 B7 MEM_RST# T2 VMB_ZQ2 B1 B9 D1 D8 E2 E8 F9 G1 G9 L8 VREFCA VREFDQ A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2 CK CK CKE ODT CS RAS CAS WE DQSL DQSU DML DMU DQSL DQSU RESET ZQ R5102 Thames@243/F_4 J1 L1 J9 L9 100-BALL SDRAM DDR3 EV@VRAM _DDR3 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 NC#J1 NC#L1 NC#J9 NC#L9 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 VMB_DQ1 VMB_DQ4 VMB_DQ2 VMB_DQ5 VMB_DQ0 VMB_DQ7 VMB_DQ3 VMB_DQ6 D7 C3 C8 C2 A7 A2 B8 A3 VMB_DQ15 VMB_DQ10 VMB_DQ14 VMB_DQ8 VMB_DQ12 VMB_DQ9 VMB_DQ13 VMB_DQ11 M8 H1 VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13 VMB_MA14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 VMB_BA0 VMB_BA1 VMB_BA2 M2 N8 M3 VMB_CLK1 VMB_CLK1# VMB_CKE1 J7 K7 K9 +1.5V_GPU VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B2 D9 G7 K2 K8 N1 N9 R1 R9 [21] VMB_CLK1 [21] VMB_CLK1# [21] VMB_CKE1 +1.5V_GPU A1 A8 C1 C9 D2 E9 F1 H2 H9 [21] VMB_ODT1 [21] VMB_CS1# [21] VMB_RAS1# [21] VMB_CAS1# [21] VMB_WE1# A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VMB_ODT1 VMB_CS1# VMB_RAS1# VMB_CAS1# VMB_WE1# K1 L2 J3 K3 L3 VMB_RDQS6 VMB_RDQS5 F3 C7 VMB_DM6 VMB_DM5 E7 D3 VMB_WDQS6 VMB_WDQS5 G3 B7 MEM_RST# T2 VMB_ZQ3 B1 B9 D1 D8 E2 E8 F9 G1 G9 L8 VREFCA VREFDQ J1 L1 J9 L9 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 CK CK CKE DQSL DQSU VREFC_VMB4 VREFD_VMB4 M8 H1 VMB_MA0 VMB_MA1 VMB_MA2 VMB_MA3 VMB_MA4 VMB_MA5 VMB_MA6 VMB_MA7 VMB_MA8 VMB_MA9 VMB_MA10 VMB_MA11 VMB_MA12 VMB_MA13 VMB_MA14 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 D7 C3 C8 C2 A7 A2 B8 A3 VMB_DQ41 VMB_DQ47 VMB_DQ40 VMB_DQ46 VMB_DQ44 VMB_DQ45 VMB_DQ43 VMB_DQ42 VMB_BA0 VMB_BA1 VMB_BA2 M2 N8 M3 VMB_CLK1 VMB_CLK1# VMB_CKE1 J7 K7 K9 A1 A8 C1 C9 D2 E9 F1 H2 H9 VMB_ODT1 VMB_CS1# VMB_RAS1# VMB_CAS1# VMB_WE1# K1 L2 J3 K3 L3 VMB_RDQS7 VMB_RDQS4 F3 C7 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VMB_DM7 VMB_DM4 E7 D3 VMB_WDQS7 VMB_WDQS4 G3 B7 MEM_RST# T2 +1.5V_GPU VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 DML DMU VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 DQSL DQSU RESET ZQ NC#J1 NC#L1 NC#J9 NC#L9 VMB_DQ55 VMB_DQ51 VMB_DQ54 VMB_DQ50 VMB_DQ52 VMB_DQ49 VMB_DQ53 VMB_DQ48 B2 D9 G7 K2 K8 N1 N9 R1 R9 VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 ODT CS RAS CAS WE E3 F7 F2 F8 H3 H8 G2 H7 +1.5V_GPU BA0 BA1 BA2 R5103 Thames@243/F_4 100-BALL SDRAM DDR3 EV@VRAM _DDR3 BOT Down VMB_ZQ4 B1 B9 D1 D8 E2 E8 F9 G1 G9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 L8 TOP Down VREFCA VREFDQ J1 L1 J9 L9 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 BA0 BA1 BA2 CK CK CKE ODT CS RAS CAS WE DQSL DQSU DML DMU DQSL DQSU RESET ZQ R5104 Thames@243/F_4 100-BALL SDRAM DDR3 EV@VRAM _DDR3 NC#J1 NC#L1 NC#J9 NC#L9 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 VMB_DQ62 VMB_DQ61 VMB_DQ63 VMB_DQ60 VMB_DQ59 VMB_DQ58 VMB_DQ57 VMB_DQ56 D7 C3 C8 C2 A7 A2 B8 A3 VMB_DQ38 VMB_DQ32 VMB_DQ36 VMB_DQ33 VMB_DQ37 VMB_DQ35 VMB_DQ39 VMB_DQ34 D +1.5V_GPU VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9 VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9 VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9 VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9 B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.5V_GPU A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 C B1 B9 D1 D8 E2 E8 F9 G1 G9 100-BALL SDRAM DDR3 EV@VRAM _DDR3 TOP Up Group-B0 VREF BOT Up Group-B1 VREF +1.5V_GPU B VREFC_VMB3 VREFD_VMB3 +1.5V_GPU R5105 [email protected]/F_4 +1.5V_GPU R5106 [email protected]/F_4 VREFC_VMB1 +1.5V_GPU R5107 [email protected]/F_4 VREFD_VMB1 +1.5V_GPU R5108 [email protected]/F_4 VREFC_VMB2 +1.5V_GPU R5109 [email protected]/F_4 VREFD_VMB2 +1.5V_GPU R5110 [email protected]/F_4 VREFC_VMB3 +1.5V_GPU R5111 [email protected]/F_4 VREFD_VMB3 B R5112 [email protected]/F_4 VREFC_VMB4 B2A VREFD_VMB4 R5113 C5213 R5114 C5214 R5115 C5215 R5116 C5216 R5117 C5217 R5118 C5218 R5119 C5219 R5120 C5220 [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X [email protected]/F_4 [email protected]/10V_4X Group-B0 decoupling CAP MEM_B0 CLK Group-B1 decoupling CAP +1.5V_GPU MEM_B1 CLK +1.5V_GPU VMB_CLK1 VMB_CLK0 VMB_CLK0# C3A R5123 R5124 [email protected]/F_4 [email protected]/F_4 C5222 C5223 C5224 C5225 C5226 C5227 C5228 C5229 C5230 C5231 C5232 C5233 C5234 C5235 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X +1.5V_GPU A C5237 [email protected]/25V_4X VMB_CLK1# C5221 C3A R5121 R5122 [email protected]/F_4 [email protected]/F_4 +1.5V_GPU C5238 C5239 C5240 C5241 C5242 C5243 C5244 C5245 C5246 C5247 C5248 C5249 C5250 C5251 C5252 EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X EV@1U/6.3V_4X +1.5V_GPU A C5236 [email protected]/25V_4X +1.5V_GPU C5253 C5254 C5255 C5256 C5257 C5258 C5259 C5260 C5261 C5262 [email protected]/6.3V_6X [email protected]/6.3V_6X [email protected]/6.3V_6X [email protected]/6.3V_6X [email protected]/6.3V_6X [email protected]/6.3V_6X [email protected]/6.3V_6X [email protected]/6.3V_6X [email protected]/6.3V_6X [email protected]/6.3V_6X Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev A1A VRAM_B: DDR3*4PCS Date: 5 4 3 2 Monday, February 13, 2012 Sheet 1 23 of 47 5 4 3 2 1 24 <VGA> +5V_S5 +3V R5125 EV@100K_4 +3V C5263 5 R5126 PX4@10K_4 C5264 EV@4700P/25V_4X U5010 Enable Power IC of +VGPU_CORE 2 PX_MODE PX_MODE [44] 3 Q5046 PX4@ME2N7002E_200MA R5128 R5136 0.5A C5265 *EV@200K_4 PX5@0_4 2 EV@0_4 Q5002 1 3 3 R5127 [7,44] PE_GPIO1 2 GPU +3V power EV@ME1303_3A PX4@TC7SH08FU(F) 3 4 1 [15] PX_EN D There is no restriction on VDDR3 relative to other rails Q5001 2 [7,44] PE_GPIO1 PX_EN needs to be isolated during a scan dump +3V [email protected]/10V_4X 1 D +3V_GPU C5266 C5267 C5268 EV@10U/6.3V_8X EV@1U/6.3V_4X [email protected]/10V_4X EV@ME2N7002E_200MA [email protected]/10V_4X 1 R5129 PX4@100K_4 PX4.0 fixed mode with BACO D3A PX_EN =0, for Normal operation PX_EN =1, for BACO MODE B2A C C SLP_S3# [7,36] SLP_S3# 1 D50 2 EV@RB500V-40_100MA Designs that do not support the BACO option must connect the BIF_VDDC to VDDC +VGPU_CORE R5130 +5V PX5@0_4 Q5003 PX4@PMV45EN_4A 1 +5V 3 Q5004 PX4@PMV45EN_4A 3 1 2 2 R5131 PX4@1K/F_4 +BIF_VDDC +BIF_CORE_EN +3V +BIF_+1V_EN B +1V_GPU Q5000 PX4@PMV45EN_4A 2 4 PX_PWRGOOD_Q 2 Q5047A PX4@2N7002KDW_115MA 1 3 2 3 PX4@TC7SH08FU(F) Q5007 PX4@PMV45EN_4A 3 1 1 1 [8,36,44] PE_PWRGD PX4@22U/6.3V_8X 2 PX_MODE U5011 C5269 Q5047B PX4@2N7002KDW_115MA 4 5 B 5 [email protected]/10V_4X 6 C5270 3 R5132 PX4@1K/F_4 +3V 5 C5559 [email protected]/10V_4X U5034 2 [7] PE_GPIO0 4 A PERST#_BUF 1 3 [8,26,28,30] APU_PCIE_RST# A PERST#_BUF [14] EV@TC7SH08FU(F) Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Date: Monday, February 13, 2012 Rev A1A Thames_M2/ Baco 5 4 3 2 Sheet 1 24 of 47 5 4 USB 3.0 Power switch +3V_S5 3 2 1 25 <USB> <U3B> +5V_S5 B2A R262 UR@10K_4 U4 2 3 4 1 9 USB_SC_EN# [36] USB_SC_EN# B2A C132 IN1 IN2 8 7 6 OUT3 OUT2 OUT1 EN# GND GND-C D3A +5VSUS_USBP1 5 OC# D3A C127 C128 *UR@470P/50V_4X *[email protected]/10V_4X USB w S&C MAXIM solution <SLC> + C130 *UR@100U/6.3V_3528P_E45b C131 C575 R144 *UR@10U/6.3V_8X UR@100U/6.3V_1206 *UR@470/F_4 C3A R69 +5V_S5 14566 UR@UP7534BRA8-15 UR@1U/16V_6X USB_SC_OC# Q14 USB_SC_OC# [7,36] 14617(with CB2) S&[email protected]/10V_4X 14617(no CB2) U5 S&C@MAX14600ETA+T B2A *UR@ME2N7002E_200MA USB 3.0 CONN R69 R62 [36] USB_BUS_SW4 [36] USB_BUS_SW3 [36] USB_BUS_SW2 <U3B> <USB> <EMI> *S&C@0_4 *S&C@0_4 VCC 1 8 DP DM 9 C309 USB_S&C#_R USB_S&C_R 2 3 2 3 1 4 1 4 *UR-3@10P/50V_4C R397 *UR-3@300_4 USB_S&C#_R1 USB_S&C_R1 USB3_RXN0 R30 USB3_RXP0 R31 [7] USB3_RXN0 [7] USB3_RXP0 USB3_TXN0 R32 USB3_TXP0 R33 1 2 3 4 5 6 7 8 9 +5VSUS_USBP1 USB_S&C#_R1 USB_S&C_R1 *UR@0X2/S 1 3 USB30_RX0USB30_RX0+ UR-3@0_4 UR-3@0_4 UR-3@0_4 USB30_TX0-_R1 C134 UR-3@0_4 USB30_TX0+_R1 C135 USB30_TX0-_C USB30_TX0+_C [email protected]/10V_4X [email protected]/10V_4X 1 2 3 4 5 6 7 8 9 VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ UR-3@TARAH-9V1391 13 12 11 10 13 12 11 10 [7] USB3_TXN0 [7] USB3_TXP0 B2A B2A 7 USB3.0 USB2.0 C308 3 2 3 2 4 1 4 1 R393 [7] USBP11[7] USBP11+ 1 2 3 4 5 6 7 8 9 *ULU@0X2/S +5VSUS_USBP0 3 USBP11-_R 1 USBP11+_R USB3_RXN1_RE R34 USB3_RXP1_RE R35 ULU-3@0_4 USB30_RX1ULU-3@0_4 USB30_RX1+ USB3_TXN1_RE USB3_TXP1_RE ULU-3@0_4 USB30_TX1-_R1 ULU-3@0_4USB30_TX1+_R1 R36 R37 V NS&C@0_4 NS&C@0_4 3 2 USB_S&C_R USB_S&C#_R 4 R59 S&C@0_4 R53 *S&C@0_4 USB_BUS_SW3 [36] CB1 CB0 CB1 CB2 0 0 Auto mode X X 1 Force Apple 2A Charger Mode 0 1 Force dedicated charger mode 0 0 0 Autodetection charger mode 1 X Pass-Through(USB) mode: Connect DP/DM to TDP/TDM 0 1 0 Force-Dedicated Charger Mode 1 0 0 1 1 0 USB Pass-Through Mode Connect DP/DM to TDP/TDM USB Pass-Through Mode with CDP Emulation.Auto connect DP/DM to TDP/TDM depending on CDP status Status Status C +5V_S5 CN2 RP2 4 2 1 2 3 4 5 6 7 8 9 VBUS DD+ GND SSRXSSRX+ GND SSTXSSTX+ R269 10K_4 B2A U6 2 3 IN1 IN2 USB_NORMAL_EN# 4 1 9 [36] USB_NORMAL_EN# B2A EN# GND GND-C C143 8 7 6 OUT3 OUT2 OUT1 5 OC# D3A +5VSUS_USBP0 C138 C139 *470P/50V_4X *0.1U/10V_4X + C140 100U/6.3V_3528P_E45b C142 C576 R145 *10U/6.3V_8X *100U/6.3V_1206 *470/F_4 UP7534BRA8-15 1U/16V_6X ULU-3@TARA9-9V1391 3 13 12 11 10 13 12 11 10 *ULU@MCM2012B900GBE V UR-3@TARAH-9V1391 UR-2@UARCF-4K1986 *ULU-3@300_4 USBP11USBP11+ D V CB0 +3V_S5 *ULU-3@10P/50V_4C USBP11-_R USBP11+_R V UR-2@UARCF-4K1986 B2A L3 USBP11USBP11+ R72 R78 1 2 3 4 D24 *UR@AZ5125-01J USBP10+ USBP10- USBP10+ USBP10- 6 8 +5VSUS_USBP1 USB_S&C#_R1 USB_S&C_R1 [7] USBP10+ [7] USBP10- GND 6 7 CN22 5 <U3B> <U2B> C GND CN1 RP1 2 4 USB_S&C#_R USB_S&C_R *UR@MCM2012B900GBE TDP TDM CB1(CEN#) CB B2A L2 R71 V *S&C@10K_4 5 1 B2A R71 R53 V C133 2 R59 V 14600 3 D R62 USB_NORMAL_OC# B B2A [email protected]_4 1 B2A C3A 1 2 3 4 OSA DE_A EQ_A +USB_RE_PWR +5VSUS_USBP0 USBP11-_R USBP11+_R D25 *ULU@AZ5125-01J D3A for ramp1 *ME2N7002E_200MA 6 8 *[email protected]_4 R39 ESD2 USB30_TX1+_R1 +5VSUS_USBP0 5 R41 B 2 CN5 7 +USB_RE_PWR Q15 USB_NORMAL_OC# [7,36] B2A ULU-2@UARC6-4K1926 USBP11-_R USB30_RX1+ 1 2 3 4 5 1 VDD NC 4 5 10 GND NC1 7 6 10 9 8 7 6 USB30_TX1-_R1 USBP11+_R USB30_RX1- *ULU-3@AZ1065-06F 6 5 4 3 2 1 NC RXARXA+ EN_A# TXBTXB+ HGND NC TXATXA+ EN_B# RXBRXB+ USB3_TXN1_RE_C C757 USB3_TXP1_RE_C C758 [email protected]/10V_4X [email protected]/10V_4X 13 14 15 16 17 18 R43 *[email protected]_4 R45 [email protected]_4 USBP0USBP0+ USB3_RXN1_RE USB3_RXP1_RE 3 2 3 2 4 1 4 1 USBP0-_R USBP0+_R *MCM2012B900GBE +USB_RE_PWR ULU-3@PI3EQX7502ZDE B2A R550 *[email protected]_4 EQ_A R559 *[email protected]_4 EQ_B R561 *[email protected]_4 DE_A R565 *[email protected]_4 DE_B R569 *[email protected]_4 OSA R570 *[email protected]_4 CN3 C3A C307 OSB DE_B EQ_B +USB_RE_PWR L4 USB 2.0 CONN USB3_TXN1_RE USB3_TXP1_RE *10P/50V_4C R395 *300_4 RP3 4 2 [7] USBP0[7] USBP0+ *E@0X2/S 3 1 +5VSUS_USBP0 USBP0-_R USBP0+_R 1 2 3 4 OSB 7 A D3A R557 [email protected]_4 R560 [email protected]_4 R564 *[email protected]_4 R567 *[email protected]_4 R568 *[email protected]_4 6 [email protected]/10V_4X USB3_RXN1_C [email protected]/10V_4X USB3_RXP1_C ULU-3@TARA9-9V1391 ULU-2@UARC6-4K1926 8 [email protected]/10V_4X USB3_TXN1_C [email protected]/10V_4X USB3_TXP1_C C753 C754 DFHS09FR085 DFHS04FR487 5 C760 C762 USB3.0 USB2.0 25 24 23 22 21 20 19 VDD NC NC DE_B EQ_B NC [7] USB3_TXN1 [7] USB3_TXP1 [7] USB3_RXN1 [7] USB3_RXP1 NC RXD_EN NC DE_A EQ_A VDD U22 7 8 9 10 11 12 A UARC6-4K1926 R571 *[email protected]_4 B2A 30 mils +USB_RE_PWR U5037 USBP0-_R +3V_S5 +3V R10 1 ULU-3@0_6 2 R13 *ULU-3@0_6 C723 C763 C751 C45 C46 ULU-3@10U/6.3V_6X [email protected]/10V_4X [email protected]/10V_4X [email protected]/10V_6X ULU-3@470P/50V_4X USBP0+_R 3 CH1 CH4 GND VDD CH2 CH3 6 USBP11-_R 5 +5VSUS_USBP0 4 USBP11+_R Quanta Computer Inc. PROJECT :BY6/BY6D *AZC099-04S Size Document Number Rev 1A USB2.0/USB3.0 Date: 5 4 3 2 Tuesday, February 14, 2012 Sheet 1 25 of 47 5 4 3 2 1 26 DVDD12 +3V 20mils L5 L6 HCB1608KF-221T20_2A C149 20mils C150 1U/6.3V_4X AVDD33 13 53 C151 C152 C153 C154 C155 1U/6.3V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 8 25 33 39 63 [5] INT_LVDS_TXP1 [5] INT_LVDS_TXN1 6 7 [5] INT_LVDS_TXP0 [5] INT_LVDS_TXN0 3 4 [5] INT_LVDS_AUXP [5] INT_LVDS_AUXN 61 60 58 INT_LVDS_HPD [5] INT_LVDS_HPD C R42 C159 APU_VARY_BL_Q 48 ANX_POR 34 TRAVIS_RST# 12 ANX_CLKSEL 10 64 12.1K/F_4 100P/50V_4N 30 31 [8] CLK_PCIE_TRAVISP [8] CLK_PCIE_TRAVISN REV.B Del RP25_20111005 +3V INT_LVDS_AUXP R48 1M_4 R51 1M_4 B2A INT_LVDS_AUXN R52 +3V +3V +3V *10K_4 TP52 TP53 REV.B add TP_20111003 B2A R55 *100K_4 R56 10K_4 INT_LVDS_HPD R57 1M_4 ANX_CLKSEL C145 C146 C147 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X HCB1608KF-221T20_2A C148 1U/6.3V_4X U7 0.1U/10V_4X L8 HCB1608KF-221T20_2A C144 54 55 56 57 11 51 52 2 5 62 65 DVDD12 DVDD12 DVDD12 DVDD12 DVDD33 DVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD33 AVDD12 LVDS_L3_P LVDS_L3_N LVDS_L2_P LVDS_L2_N LVDS_L1_P LVDS_L1_N LVDS_L0_P LVDS_L0_N DPRX_LN1_P DPRX_LN1_N DPRX_LN0_P DPRX_LN0_N DPRX_AUX_P DPRX_AUX_N LVDS_CLKL_P LVDS_CLKL_N DPPX_HPD CLKSEL LVDS_U3_P LVDS_U3_N LVDS_U2_P LVDS_U2_N LVDS_U1_P LVDS_U1_N LVDS_U0_P LVDS_U0_N R_BIAS LVDS_CLKU_P LVDS_CLKU_N CPU_VARY_BL POR RESET_L OSC_IN OSC_OUT DDC_CLK DDC_DATA TDO TDI TCK TMS BL_EN DIGON VARY_BL 20mils 9 32 46 59 +1.2V_TRAVIS D AVDD12 1 C156 C157 L7 C158 0.01U/25V_4X 0.1U/10V_4X 1U/6.3V_4X 29 28 24 23 22 21 20 19 INT_LCD_TXLOUT2+ INT_LCD_TXLOUT2INT_LCD_TXLOUT1+ INT_LCD_TXLOUT1INT_LCD_TXLOUT0+ INT_LCD_TXLOUT0- 27 26 INT_LCD_TXLCLKOUT+ [32] INT_LCD_TXLCLKOUT- [32] HCB1608KF-221T20_2A [32] [32] [32] [32] [32] [32] 45 44 41 40 38 37 36 35 43 42 49 50 C TRAVIS_LVDS_EDIDCLK TRAVIS_LVDS_EDIDDAT 15 14 47 R47 R49 R50 R44 R46 *SHORT_4 *SHORT_4 *SHORT_4 *SHORT_4 *SHORT_4 INT_LCD_EDIDCLK [32] INT_LCD_EDIDDATA [32] TRAVIS_BL_EN [32] TRAVIS_DIGON [32] TRAVIS_VARY_BL [32] Care sequenc, S5 - S0, S0 - S3, S3 - S0 NC1 NC2 NC3 AVSS AVSS AVSS PAD GPIO2 GPIO1 GPIO0 +5V_S5 18 17 16 +1.2V_VDDPR R54 Q2 PMV45EN_4A 10K_4 3 R58 100K_4 +5V_S5 ANX_POR ANX3111 C160 0.1U/10V_4X B2A 4.7K_4 +3V C161 0.1U/16V_4Y 5 B R65 [36] RUN_1.2V B Q3B 2N7002KDW_115MA 4 6 R63 120K/F_4 Q2 1st BAM34040001, Rdson=22.5m 2nd BAM2306006, Rdson=38m 3 R61 R60 *10K_4 +1.2V_TRAVIS 1 2 +3V D +1.2V_TRAVIS 20mils DVDD33 2 *0_4 1 Q3A 2N7002KDW_115MA C162 1U/6.3V_4X +3V +1.5VSUS DVDD33 +1.5VSUS R66 2.2K_4 R70 4.7K_4 [8] PCIE_RST#_TRAVIS R67 10K_4 D9 *1SS355_100MA 1 D10 2 RB500V-40_100MA TRAVIS_RST# 2 C163 *0.1U/10V_4X A *0_4 Care TRAVIS_EN# active Hi not active Lo R68 *2.2K_4 [5] APU_VARY_BL R64 [7] TRAVIS_EN# 1 3 Q5 APU_VARY_BL_Q [8,24,28,30] FDV301N_200MA APU_PCIE_RST# C164 0.1U/16V_4Y A D3A Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev 1A TRAVIS ANX3110 Date: 5 4 3 2 Tuesday, February 14, 2012 Sheet 1 26 of 47 5 4 HDMI 3 2 1 27 B2A INT_HDMI_TXDN0 INT_HDMI_TXDP0 INT_HDMI_TXDN0 INT_HDMI_TXCP INT_HDMI_TXDN2 R73 *HM@100_4 INT_HDMI_TXDP2 INT_HDMI_TXDN1 R74 *HM@100_4 INT_HDMI_TXDP1 INT_HDMI_TXDN0 R75 *HM@100_4 INT_HDMI_TXCN R76 *HM@100_4 INT_HDMI_TXCP INT_HDMI_TXCN HDMI_CON_CEC B2A HDMI_SCL HDMI_SDA INT_HDMI_TXDP0 +5V R90 NCEC@0_6F1 +5VPCU R88 CEC@0_6 2 1 2 +5V_HDM *HM@SMD1206P110TFT D11 1 DDC5V *HM@B130LAW-7-F_1A HDMI_HPD_L C168 +3V +5V R77 HM@1K_4 23 22 R79 HM@10K_4 [5] INT_HDMI_HPD Q6B 21 2 IN DDC5V OUT GND HM@AP2331SA-7 C166 *HM@56P/50V_4N D30 *HM@AZ5125-01J C167 *HM@56P/50V_4N 1 C3A B2A DDC5V DDC5V 2 B2A D12 +5V +3V 1 R546 [email protected]_4 D13 HMO@RB500V-40_100MA HMO@RB500V-40_100MA R81 [email protected]_4 R82 [email protected]_4 2 R547 [email protected]_4 C3A 1 +3V B2A +3V DDC5V HDMI_SDA U8 4 +3V +5V C3A C +3V 3 2 R576 [email protected]_4 C171 B2A [email protected]/10V_4X 1 INT_HDMI_AUXP 3 Q9 1 +3V 2 R577 [email protected]_4 [5] INT_HDMI_AUXN [5] INT_HDMI_AUXP HDMI_SCL R316,R311,R335,R330,R343,R339,R327 and R321 need to close to HDMI connector B2A GND EN SDA1 SDA2 SCL1 SCL2 VREF1 VREF2 5 HDMI_EN C169 *HMO@10P/50V_4C R83 HM@0_4 6 7 8 R85 *HM@0_4 HDMI_SCL 3 3 HDMI_SDA HM@FDV301N_200MA Q8 R86 HM@604/F_4 INT_HDMI_TXDP0 R87 HM@604/F_4 INT_HDMI_TXDN0 R89 HM@604/F_4 INT_HDMI_TXDP1 R91 HM@604/F_4 INT_HDMI_TXDN1 R93 HM@604/F_4 R96 HM@604/F_4 INT_HDMI_TXDN2 R98 HM@604/F_4 INT_HDMI_TXCP R99 HM@604/F_4 C Q7 2 HDMI_VREF2 C170 *HMO@10P/50V_4C HMO@PCA9509DP HM@FDV301N_200MA PCA9306DCUR-->200K/F PCA9509DP-->0ohm B2A 1 1 INT_HDMI_AUXN R134 HM@100K_4 1 2 C165 *[email protected]/10V_4X HDMI_HPD_L Q6A 2 3 HM@2N7002KDW_115MA HM@2N7002KDW_115MA Q10 HDMI_SDA D 5 HM@HMR2N-AK120N [email protected]/10V_4X HDMI_SCL HDMI Hot-plug 6 INT_HDMI_TXDN1 INT_HDMI_TXDP0 20 SHELL1 D2+ D2 Shield D2D1+ D1 Shield D1D0+ D0 Shield D0GND CK+ CK Shield GND CKCE Remote NC DDC CLK DDC DATA GND +5V HP DET SHELL2 3 INT_HDMI_TXDN2 INT_HDMI_TXDP1 INT_HDMI_TXCN INT_HDMI_TXCP [5] INT_HDMI_TXCN [5] INT_HDMI_TXCP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 INT_HDMI_TXDP2 INT_HDMI_TXDN2 INT_HDMI_TXDP2 [5] INT_HDMI_TXDN2 [5] INT_HDMI_TXDP2 D CN4 INT_HDMI_TXDN1 INT_HDMI_TXDP1 [5] INT_HDMI_TXDN1 [5] INT_HDMI_TXDP1 4 [5] INT_HDMI_TXDN0 [5] INT_HDMI_TXDP0 R97 HM@FDV301N_200MA DDC5V C172 INT_HDMI_TXDP2 HM@100K_4 [email protected]/10V_4X INT_HDMI_TXCN C173 [email protected]/10V_4X CEC Output <CEC> (To Connect) HDMI CEC <CEC> +3VPCU 0.013A(20mils) C5279 C5280 *CEC@1U/6.3V_4X *[email protected]/10V_4X C5286 RP14 3 1 4 *[email protected] 2 XIN_CEC XOUT_CEC CEC-RESET# CEC-MODE 4 6 3 8 5 15 14 11 3 XOUT XIN TEST1 TEST0 RESET MODE CEC OUT CEC IN VSS NC NC NC HPDET NC 1 20 18 17 3ND_MBCLK 3ND_MBDATA HDMI_CEC_DDCDATA HDMI_CEC_DDCCLK 13 12 CEC-TEST1 CEC-TEST2 RP13 4 2 +3VPCU 3ND_MBCLK [34,36] 3ND_MBDATA [34,36] 3 *[email protected] 1 B CEC_OUT R9556 1 *CEC@22K_4 R9557 +3VPCU Q5018 *CEC@100K_4 10 9 CEC_OUT CEC_IN 19 2 HPDET R9561 *CEC@2SK3541T2L_100MA HDMI_SDA CEC-RESET# 6 1 *CEC@R5F211B4D61SP#W4 R9537 B2A **CEC@47K_4 HDMI_CEC_DDCDATA CEC-TEST1 Q5022A R9538 **CEC@0_4 CEC-MODE *CEC@2N7002KDW_115MA R9539 **CEC@0_4 CEC Input <CEC> (To CECC) CEC-TEST2 +3VPCU +3VPCU CEC HotPlug <CEC> U5017 1 2 3 +3VPCU 5 C5285 *[email protected]/10V_4X R9569 4 HDMI_SCL *CEC@SN74LVC1G14DCKR 3 CEC_EC_HP *[email protected]/10V_4X R9542 5 *CEC@33_4 4 1 2 3 *[email protected]_4 4 Q5022B U5015 C5283 [36] CEC_EC_HP *[email protected]_4 2 4 *[email protected] 2 SCL SDA DDCSDA DDCSCL 5 RP21 3 1 VCC VCC 2 +3VPCU <CEC> **CEC@47P/50V_4N U5014 7 16 B CEC SMBus Level Shift (To CECC) HDMI_CON_CEC HDMI_CEC_DDCCLK *CEC@2N7002KDW_115MA B2A R9541 *CEC@1K/F_4 HDMI_HPD_L +3VPCU +3VPCU *CEC@SN74LVC1G17DCKR HPDET +3VPCU R9544 C3A A D2008 R9555 *CEC@470K_4 *CEC@RB500V-40_100MA **CEC@10K_4 U5016 1 HDMI_CON_CEC CEC_IN 3 R9558 *CEC@27K_4 **[email protected]/10V_4X 5 C5284 1 4 INT_HDMI_HPD 2 **CEC@TC7SH08FU(F) Q5019 **CEC@2SK3541T2L_100MA +3V Quanta Computer Inc. 2 3 A PROJECT :BY6/BY6D Size B2A Del RP24 Rev 1A HDMI/CEC Date: 5 Document Number 4 3 2 Tuesday, February 14, 2012 1 Sheet 27 of 47 5 Atheros Lan 4 3 2 1 <LAN> <LNG> <LN1> <LAN> <LNG> 28 LAN_VDD33 0.163A(20mils) R548 LAN_VDD33 LAN_VDD33 LAN@10K_4 R549 LAN@0_4 CKREQ# U9 D C174 C175 C176 [email protected]/6.3V_6X LAN@1U/10V_6Y 1 [email protected]/16V_4Y VDD33 39 38 23 LED1/LED_LINK10/100n LED0/LED_ACTn LED2/CLKREQn 20110719 del 10U/6.3_8X for saving spacing C3A C276 APU_PCIE_RST# PCIE_WAKE# [8,24,26,30] APU_PCIE_RST# CKREQ# B2A C184 62@30K/F_4 6 AVDDL 7 LAN_XTLI 8 AR8151/AR8152 XTLO XTLI 2 C126 LAN@ME1303_3A C270 [email protected]/25V_4X R328 *[email protected]/25V_4X R164 [email protected]_4 [email protected]/F_4 3 C186 C187 [email protected]/10V_4X [email protected]/10V_4X D CLK_PCIE_LANP [8] CLK_PCIE_LANN [8] PCIE_TXN_LAN [3] PCIE_TXP_LAN [3] PCIE_RXP_LAN [3] PCIE_RXN_LAN [3] LAN-Wake up function <LAN> SB_SMBDATA1_LAN SB_SMBCLK1_LAN GND9 GND8 C194 62@0_6 LAN_VDD33 [email protected]/16V_4Y AVDDL [email protected]/16V_4Y C275 C3A C3A For EMI close to U9 GIGA:AR8151-BL1A-R AL008151005 Q26 C564 [email protected]/50V_4N TX0P C565 [email protected]/50V_4N TX0N C567 [email protected]/50V_4N TX1P C568 [email protected]/50V_4N TX1N LAN-SM-Bus <LAN> TRANSFORMER CONN C B2A SB_SMBDATA1_LAN R104 *LAN@0_4 SMB_LAN_DAT [7,30] SB_SMBCLK1_LAN R105 *LAN@0_4 SMB_LAN_CLK [7,30] 10/100:AR8152-BL1A-R AL008152009 LAN@LTC044EUBFS8TL_30MA 1 PCIE_WAKE# [7,30] [email protected]/16V_4Y R578 AVDDH_C C268 GND10 50 GND7 AVDDH B2A 2 Q25 AR8152-BL1A-R LAN_P [36] 49 3 48 TRXP3 TRXN3 +3V_S5 1 16 19 13 AVDDH AVDDL AVDDL TRXP2 TRXN2 GND6 20 21 *LAN@0_6 22 AVDDH TRXP1 TRXN1 GND5 17 18 [email protected]/16V_4Y [email protected]/16V_4Y [email protected]/16V_4Y [email protected]/16V_4Y FCH_PCIE_LAN_CLKREQ# [7] FCH_PCIE_LAN_CLKREQ# 41 TRXP0 TRXN0 47 LAN_VDD33 C C180 C181 C182 C183 PCIE_RXP_LAN_C PCIE_RXN_LAN_C 26 25 GND1 GND4 14 15 C3A LAN@1U/10V_6Y PCIE_WAKE# RBIAS 46 TX1P TX1N LAN@1U/10V_6Y [email protected]/16V_4Y C179 AVDDH_REG GND3 11 12 45 10 TX0P TX0N *LAN@470P/50V_4X *LAN@470P/50V_4X 40 LX GND2 AVDDH [email protected]/F_4 RBIAS C193 C177 C178 CKREQ# 28 27 SMDATA SMCLK LAN@25MHZ_30 9 33 32 36 35 30 29 TEST_RST TESTMODE Y1 R103 R102 AVDDL_REG DVDDL DVDDL AVDDL AVDDL 24 31 34 REFCLKP REFCLKN RX_N RX_P TX_P TX_N VDDCT LAN@33P/50V_4N C192 +3V_S5 LAN_XTLO Atheros PERSTn WAKEn VDDCT_REG/CKRn 44 C191 5 43 LAN@1U/10V_6Y R575 2 3 4 52@0_4 42 [email protected]/16V_4Y +3V LAN@33P/50V_4N 2 C190 R552 AVDD_CEN 52@1U/10V_6Y 1 C189 62@0_4 [email protected]/16V_4Y C185 C188 R562 LAN_LINKLED# LAN_ACTLED 52@0_4 B2A 37 DVDD_REG DVDDL AVDDL AVDDL *150P/50V_4N R551 20110801 add SMbus for LAN RJ45 <LAN> <LNG> 1 0 LED0 = LAN_ACTLED <LAN> <LNG> <LN1> PLACE NEAR LAN IC SIDE <LAN> <LNG> 2 4 RN5 RN6 8 7 6 5 4 3 2 1 TX0N TX0P L15 AVDD_CEN 52@HCB1608KF-601T10_1A TX1P TX1N TX0P TX0N 1 SWR switch-mode regulator select Giga LAN pull High (default = 1) 0 LDO linear regulator select 10/100M LAN pull Low U21 B2A 2 4 Over-clocking disable LED1 = LAN_LINKLED# B B2A Over-clocking enable (default = 1) AVDD_CEN_R TX1N TX1P C423 C424 C273 [email protected]/16V_4Y [email protected]/16V_4Y LAN@1U/10V_6Y TDTD+ CT NC NC CT RDRD+ TXTX+ CT NC NC CT RXRX+ 9 10 11 12 13 14 15 16 X-TX0N X-TX0P TERM0 B TERM1 X-TX1N X-TX1P C422 C421 1 Normal function 0 ATE test mode CKREQ# or CKREQ_G# [email protected]/100V_6X [email protected]/100V_6X [email protected] 1 3 1 3 LAN@NS681610 [email protected] TERM2 C197 C199 52@1000P/50V_4X C200 C201 [email protected]/16V_4Y 52@1000P/50V_4X C202 [email protected]/16V_4Y 10/100:DB0EF7LAN01 GIGA: DB0Z06LAN00 TERM3 R108 *[email protected]/10V_4X R109 C198 *[email protected]/10V_4X LAN@75/F_8 CN20 LAN@75/F_8 Power on Strapping pin LAN_ACTLED C425 LAN@220P/3KV_1808X TERM5 D3A del C195 and C196 TERM5 8 TERM5 7 6 X-TX1N B2A A U13 TX0P 1 2 TX0N 3 CH1 CH4 GND VDD CH2 CH3 6 5 TERM5 4 X-TX1P 3 X-TX0N 2 X-TX0P 1 TX1P 5 4 TERM5 LAN_VDD33 NC4/3- [email protected]/F_6 [email protected]/F_6 NC/3+ RX-/1NC2/2NC1/2+ A RX+/1+ B2A TX-/0TX+/0+ GND GND TX1N R110 LAN_LINKLED# R111 9 10 R348 *SHORT_6 Quanta Computer Inc. *[email protected] LAN@130456-031 PROJECT : BY6/BY6D Size Document Number Rev 1A ATHEROS LAN (AR8152B) Date: 5 4 3 2 Tuesday, February 14, 2012 1 Sheet 28 of 47 5 4 3 2 1 29 Codec (CX20671-21Z) <ADO> <EMI> Output HP <ADO> <EMC> Output FILT_1.65V C203 C204 C205 C206 1U/10V_6Y 0.1U/16V_4Y 4.7U/6.3V_6X 0.1U/16V_4Y CN6 D3A 1.2mA(20mils) R114 +3V *SHORT_6 D ADOGND +3AVDD R112 5.1/F_6 HPOUT-L2 L10 HCB1608KF-121T20_2A HPOUT-L3 HPOUT-R R113 5.1/F_6 HPOUT-R2 L11 HCB1608KF-121T20_2A HPOUT-R3 1 2 6 3 4 C211 C212 4.7U/6.3V_6X 0.1U/16V_4Y 0.1U/16V_4Y 5 Port_A# Layout Note: Path from +5V_IC to LPWR_5.0 and RPWR_5.0 must be very low resistance ( <0.01 ohms). C208 C209 C210 *100P/50V_4N *100P/50V_4N *0.1U/25V_6X Shield_GND GND D Normal Open Jack Place bypass caps very close to device. GND GND 0.061mA(15mils) R115 7 8 9 10 ADOGND Near chip +3V_S5 HPOUT-L 2SJ3013-009311F C207 D3A C3A AVDD_3.3 +3AVDD_S5 *SHORT_6 C213 C214 C215 C216 *10U/6.3V_8X 0.1U/16V_4Y Determining HDA use +1.5V/+3V *10U/6.3V_8X 0.1U/16V_4Y ADOGND Port_A# 1A(100mils) +5AVDD L12 TI160808U300_1A +5V D15 *VPORT 0603 220K-V05 HPOUT-L3 D16 *VPORT 0603 220K-V05 HPOUT-R3 D14 *VPORT 0603 220K-V05 GND GND GND 48.7mA(20mils) Modify Power from +3V to +3V_S5 for fixing W/L and MODS issue C217 C218 *10U/6.3V_8X 0.1U/16V_4Y GND +3AVDD CLASSD_5V Output GND (40mils) External MIC <ADO> <EMC> FILT_1.8V C219 C220 C221 C222 C223 C224 C225 4.7U/6.3V_6X 0.1U/16V_4Y 0.1U/16V_4Y 0.1U/16V_4Y 0.1U/16V_4Y 10U/6.3V_8X 10U/6.3V_8X D3A *SHORT_4 +3AVDD R116 R124 R121 33_4 *SHORT_4 ACZ_BITCLK_R5 8 6 SDATA_IN 4 15 17 RPWR_5.0 28 27 BIT_CLK SYNC SDATA_IN SDATA_OUT 12 29 3 REV-00 for EMI GND CLASSDREF D3A [7] ACZ_BITCLK [7] ACZ_SYNC [7] ACZ_SDIN0 [7] ACZ_SDOUT RESET# AVDD_5V [7] ACZ_RST# C LPWR_5.0 9 FILT_1.65 0.1U/16V_4Y AVDD_3.3 C226 FILT_1.8 GND VAUX_3.3 VDD_IO DVDD_3.3 AVDD_HP U10 2 7 18 26 SENSE_A_R GND R117 5.11K/F_4 MIC1-VREFO C227 SENSE PIN A R118 3.3K/F_4 R119 3.3K/F_4 *4.7U/6.3V_6X C3A1 ADOGND SENSE_A 36 R120 R122 SENSE_A Port_A# Port_B# 39.2K/F_4 20K/F_4 R123 MIC1_L2 100/F_6 L13 HCB1608KF-121T20_2A MIC1_R3 MIC1_R1 R125 100/F_6 MIC1_R2 L14 CN7 2 6 3 4 MIC1_L3 MIC1_L1 HCB1608KF-121T20_2A 7 8 9 10 C 5 Port_B# PORTB_R PORTB_L B_BIAS [7] PCBEEP GND R127 33_4 R128 *10K_4 PCBEEP_R C233 0.1U/16V_4Y PCBEEP_C 39 TP4 AMP_MUTE# [36] AMP_MUTE# 10 Low Active 38 37 PC_BEEP C_BIAS PORTC_R PORTC_L SPDIF GPIO0/EAPD# GPIO1/SPK_MUTE# R129 DMIC 100_4 DMIC_DATA PORTA_R PORTA_L DMIC_CLK DMIC_1/2 2.2U/6.3V_6X 2.2U/6.3V_6X *SHORT_4 MIC1_R1 MIC1_L1 MIC1-VREFO 2SJ3013-009311F C230 TP1 TP2 TP3 C232 DMIC_DATA C237 Port_B# ADOGND 25 24 23 22 21 20 19 HPOUT-R HPOUT-L AVEE FLY_N FLY_P C234 0.1U/16V_4Y GND Normal Open Jack *0.1U/25V_6X D3A D18 *VPORT 0603 220K-V05 D17 2 1 *VPORT 0603 220K-V05 MIC1_L3 D19 2 1 *VPORT 0603 220K-V05 MIC1_R3 GND GND 1U/10V_6Y REV-00 Del short pad,Add C590 DMIC Shield_GND C231 100P/50V_4N 100P/50V_4N 32 31 30 EP_GND 41 RIGHT- LEFT- RIGHT+ 16 14 13 LEFT+ AVEE FLY_N FLY_P 11 C228 C229 R126 GND NC_DR NC_DL 40 1 MIC1-RR MIC1-LL MIC1-VREFO_B CX20671-21Z Place close to audio codec. [32] DMIC_CLK [32] DMIC_DATA 35 34 33 C235 C236 0.1U/16V_4Y 4.7U/6.3V_6X Internal Speaker <ADO> <EMC> CN8 SPK_R+ SPK_RSPK_LSPK_L+ GND MIC1-LL R130 R131 R132 R133 INSPKR+N INSPKR-N INSPKL-N INSPKL+N PBY160808T-501Y-N_1.2A PBY160808T-501Y-N_1.2A PBY160808T-501Y-N_1.2A PBY160808T-501Y-N_1.2A 1 2 3 4 MIC1-RR 1 2 3 4 88266-040L C239 B GND C238 0.1U/16V_4Y C241 *0.1U/16V_4Y C244 *0.1U/16V_4Y C240 *0.47U/6.3V_4X C242 *0.47U/6.3V_4X GND GND GND Close to CN2 C243 *0.47U/6.3V_4X B INSPKL-N INSPKL+N INSPKR-N INSPKR+N *0.47U/6.3V_4X B2A GND C245 E@2200P/50V_4X ADOGND C246 C247 C248 E@2200P/50V_4X E@2200P/50V_4X E@2200P/50V_4X SPK_R+ For EMI GND GND GND GND SPK_RACZ_BITCLK ACZ_SDOUT ACZ_RST# D3A SPK_LC249 C250 C251 *10P/50V_4C *10P/50V_4C *10P/50V_4C SPK_L+ INSPKR+N INSPKR-N D20 VPORT 0603 220K-V05 INSPKL+N INSPKL-N D21 D22 D23 VPORT 0603 220K-V05 VPORT 0603 220K-V05 VPORT 0603 220K-V05 GND A A Quanta Computer Inc. PROJECT :BY6/BY6D Size Document Number AUDIO CODEC (CX20671-21Z) Date: 5 4 3 2 Tuesday, February 14, 2012 1 Sheet 29 of Rev 1A 47 5 MINI Card Slot#1 (WiFi) 4 3 2 1 30 B2A <MNW> +1.5V Before RAMP must to remove debug card component D WIMAX_P C3A C414 C410 C416 C413 C271 C411 C417 C272 [email protected]/25V_4X [email protected]/16V_4Y *10U/6.3V_8X [email protected]/16V_4Y 0.1U/16V_4Y *[email protected]/16V_4Y *[email protected]/16V_4Y *C@10U/6.3V_8X D CN19 PLTRST#_debug PCLK__debug_R NMP@0_4 NMP@0_4 [3] PCIE_TXP_WLAN [3] PCIE_TXN_WLAN [3] PCIE_RXP_WLAN [3] PCIE_RXN_WLAN WIMAX_P 2 R582 [8] CLK_PCIE_WLANP [8] CLK_PCIE_WLANN 10K_4 C [7] FCH_PCIE_WLAN_CLKREQ# 6 1 Q76A CLKREQ# BT_RFCTRL_BT 2N7002KDW_115MA R361 D3A *0_4 WLAN_WAKE# 15 13 11 9 7 5 3 1 NC C-Link_RST C-Link_DAT C-Link_CLK GND NC NC GND GND PETp0 PETn0 GND GND PERp0 PERn0 GND NC NC +3.3V GND +1.5V LED_WPAN# LED_WLAN# NC NC USB_D+ USB_DGND SMB_DATA SMB_CLK +1.5V GND +3.3Vaux PERST# W_DISABLE# GND GND REFCLK+ REFCLKGND CLKREQ# BT_CHCLK BT_DATA WAKE# NC NC NC NC NC +1.5V GND +3.3V SMBus(DDR3/WLAN/3G) 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 R356 USBP7+ USBP7- USBP7+ [7] USBP7- [7] WLCGDAT_SMB WLCGCLK_SMB R400 *300_4 C556 [7,28] SMB_LAN_CLK *10P/50V_4C 0_4 Q79B 3 *2N7002KDW_115MA 4 B2A C572 C3A *150P/50V_4N APU_PCIE_RST# RF_EN 16 14 12 10 8 6 4 2 LFRAME#_PCIE LAD3_PCIE LAD2_PCIE LAD1_PCIE LAD0_PCIE WIMAX_P APU_PCIE_RST# [8,24,26,28] RF_EN [36] RN8 RN7 R330 2 4 2 4 WLCGCLK_SMB R335 *4.7K_4 5 R420 R339 1 NMP@0X2 3 1 NMP@0X2 3 NMP@0_4 R381 *4.7K_4 2 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 BT_RFCTRL_BT B2A PLTRST# [8,31,36] PLTRST# [8] PCLK_DEBUG LFRAME# [8,36] LAD3 [8,36] LAD2 [8,36] LAD1 [8,36] LAD0 [8,36] 6 [7,28] SMB_LAN_DAT 1 WLCGDAT_SMB C Q79A R360 *2N7002KDW_115MA 0_4 AAA-PCI-052-P01 Q76B 3 B2A 5 [7,28] PCIE_WAKE# 2N7002KDW_115MA 4 R580 WIMAX_P 10K_4 WIMAX_P R165 BT_RFCTRL_BT 10K_4 2 [36] BT_RFCTRL Q13 1 3 LTC044EUBFS8TL_30MA B B +3V_S5 WIMAX_P R162 R163 *0_6 *0_6 +3V R168 R186 0_6 0_6 B2A A A Quanta Computer Inc. PROJECT :BY6/BY6D Size Document Number Rev 1A MINI CARD Date: 5 4 3 2 Tuesday, February 14, 2012 1 Sheet 30 of 47 5 3 2 1 őŐŘņœ D3A : LED ŃłŕņœœŚ luminance to light,1K-ohm change 2.2K-ohm. +5VPCU D3A : LED œŇġōņŅ luminance to light,1K-ohm change 2.2K-ohm. +5VPCU 1 LED4 31 C3A 3 LED 4 2 12-21/S2C-AQ2R2B/2C +5V B2A 2 2 D -PWRLED R135 1.5K/F_4 PWRLED# PWRLED# [36] -BATLED0 R139 2.2K_4 BAT_SAT0# [36] RF_LED_R R140 1.2K/F_4 D RF_LED# [36] 1 1 3 3 C3A SUSLED R137 1.2K/F_4 LED1 12-11Z/T3D-CP2Q2B12Y/2C(QN) -PWRLED SUSLED_EC# SUSLED_EC# [36] 1.2K/F_4 B2A 1 B2A 1 3 3 -BATLED1 2 BAT_SAT1# [36] RF_LED_R -BATLED0 3 SUSLED B2A LED3 12-12Z/S2ST3D-C31/2C(QN) C3A B2A 1 -BATLED1 R141 D2033 *PJMBZ5V6 3 IN 1 CARD READER (Type: MS/MMC/SD) 2 2 D2035 *PJMBZ5V6 D2034 *PJMBZ5V6 <MMC> Card Reader (AU6437B53-GDL-GR) VCC_XD C C252 4.7U/6.3V_6X B2A Clock input selection 1 : 48MHz input (default) 0 : 12MHz input *SHORT_4 48M_CARD_R R151 +3V_Card C259 *1U/6.3V_4X B 330_4 USBP5+ USBP5- C260 4.7U/6.3V_6X C261 4.7U/6.3V_6X 1 2 3 4 5 6 7 8 9 10 11 12 +1.8V_Card GPON7 EXT48IN RSTN REXT VD33P DP DM VS33P XI XO VDD1 V18 C310 *10P/50V_4C R398 13 14 15 16 17 18 19 20 21 22 23 24 USBP5+ USBP5- [7] USBP5+ [7] USBP5- *300_4 36 35 34 33 32 31 30 29 28 27 26 25 NC3 DATA6 CTRL0 DATA5 CTRL2 AU6437B53-GDL-GR DATA4 DATA3 DATA2 XDWPN XDCEN EEPDATA EEPCLK CTRL0 CTRL2 CN9 VCC_XD R9772 BLM15BD121SN1D_300MA DATA2 DATA1 DATA0 DATA3 DATA2 SD AU6437B53-GDL-GR SDWP R157 CTRL1 CTRL0 trace surround with GND XD MS CTRL0 SDCLK XDALE MSBS CTRL1 SDWP XDCLE MSCLK CTRL2 SDCMD XDRBD CTRL3 CTRL4 B2A 33_4 SD_CD# SDCDN CTRL0 R9775 R9781 R9774 R9776 33_4 33_4 33_4 BLM15BD121SN1D_300MA SD_WP SD_D2 SD_D1 SD_D0 SD_CLK CTRL2 DATA3 R9777 R9779 33_4 33_4 SD_CMD SD_D3 W/P DATA2 DATA1 DATA0 VSS2 CLK VSS1 CMD DATA3 SDR009-11-F B GND3 15 D3A XDWRN XDRDN 10 9 8 7 6 5 3 2 1 GND2 R146 R9773 VCC_XD 14 [8] CLK_48M_CARD NBMD Power saving mode enable 1 : enable (default) 0 : disable 4 *SHORT_4 D3A CF_V33 NC1 AVDD5V AGND5V V33 VDDHM1 NC2 GND1 VDD2 CTRL4 XDCDN SDWPEN D3A R148 [8,30,36] PLTRST# CTRL3 VDDHM2 GND2 VDD3 XTALSEL NC5 NBMD CTRL1 CTRL3 DATA1 DATA0 DATA7 NC4 C258 *33P/50V_4N R147 *10K_4 REV.B 20111023 change connector pin define 11 12 U11 48 47 46 45 44 43 42 41 40 39 38 37 0.1U/10V_4X +3V C/D CD COM C257 C255 *0.1U/16V_4Y VDD *0_4 +3V_Card C254 *0.1U/16V_4Y WP COM R143 +1.8V_Card C253 0.1U/16V_4Y 13 *0_4 NBMD CTRL1 CTRL3 DATA1 DATA0 0.1U/10V_4X R142 XTALSEL C256 C 30mils MSINS *0_4 CTRL4 +3V D3A R158 0.5A(30mils) +1.8V_Card +3V_Card +3V_Card *SHORT_8 C265 4.7U/6.3V_6X +3V_Card C262 0.1U/10V_4X C263 0.1U/10V_4X SD write protect enable 1 : decided by SDWP(default) 0 : SD always write-able CTRL4 SD_CLK C266 0.1U/10V_4X C267 *270P/50V_4X C264 *33P/50V_4N C14 close to CN2 A A Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev 1A CARD READER/LED Date: 5 4 3 2 Sheet Tuesday, February 14, 2012 1 31 of 47 5 4 CCD [CCD] 3 LCD POWER SWITCH 2 1 HALL SENSOR&BACK LIGHT SWITCH <LDS> R159 +3VPCU 32 <HSR> 100K_4 +3V R399 C428 2 LID591# LID591# [36] MR1 USBP6-_LCD [7] *300_4 1 D3A USBP6+_LCD [7] USBP6-_LCD C405 1U/10V_6X *10P/50V_4C R325 *SHORT_1206 C269 LCDVCC 3 USBP6+_LCD APX9132H AI-TRG 0.1U/10V_4X U19 D B2A 6 4 1 *SMD1206P110TFT CCD_POWER C274 + F2 2 +3V 3 [26] TRAVIS_DIGON D IN OUT IN GND ON/OFF GND 1 2 C406 5 0.1U/16V_4Y D3A DISPON_I [36] DISPON_I 10U/6.3V_8X R167 *SHORT_4 TRAVIS_BL_EN [26] AP2821KTR-G1 R170 0_8 R327 R173 100K_4 100K_4 B2A DISPON R172 1.2K/F_4 EC_FPBACK# [36] D39 LCP0G050M0R2R LCD Panel Module [LDS] B2A D3A CN10 LCD_BK_POWER C VIN *SHORT_8 LCD_BK_POWER R174 C279 +3V C280 INT_LCD_EDIDCLK INT_LCD_EDIDDATA C277 1000P/50V_4X 0.1U/25V_6X *47P/50V_4N LVDS Enable +3V R175 4.7K_4 INT_LCD_EDIDCLK R176 4.7K_4 INT_LCD_EDIDDATA INT_LCD_TXLOUT1INT_LCD_TXLOUT1+ INT_LCD_TXLOUT2INT_LCD_TXLOUT2+ INT_LCD_TXLCLKOUTINT_LCD_TXLCLKOUT+ D3A R177 [26] TRAVIS_VARY_BL C282 INT_LCD_TXLOUT0INT_LCD_TXLOUT0+ *SHORT_4 LVDS_VADJ LVDS_VADJ DISPON LCDVCC LCDVCC 0.1U/10V_4X 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C278 INT_LCD_TXLCLKOUTINT_LCD_TXLCLKOUT+ [26] INT_LCD_TXLCLKOUT[26] INT_LCD_TXLCLKOUT+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C INT_LCD_TXLOUT2+ INT_LCD_TXLOUT2- [26] INT_LCD_TXLOUT2+ [26] INT_LCD_TXLOUT2- INT_LCD_TXLOUT1+ INT_LCD_TXLOUT1- [26] INT_LCD_TXLOUT1+ [26] INT_LCD_TXLOUT1- INT_LCD_TXLOUT0+ INT_LCD_TXLOUT0- [26] INT_LCD_TXLOUT0+ [26] INT_LCD_TXLOUT0- INT_LCD_EDIDDATA INT_LCD_EDIDCLK [26] INT_LCD_EDIDDATA [26] INT_LCD_EDIDCLK *10U/6.3V_4X [29] DMIC_DATA [29] DMIC_CLK C286 C287 L17 L16 DMIC_DATA_R DMIC_CLK_R FCM1005KF-221T03_300MA FCM1005KF-221T03_300MA USBP6+_LCD USBP6-_LCD *4.7P/50V_4C *4.7P/50V_4C CCD_POWER USBP6-_LCD USBP6+_LCD C283 22P/50V_4N C3A 24 25 26 27 28 29 30 24 25 26 27 28 29 30 34 33 32 31 34 C3A +3VPCU 33 INT_LCD_EDIDDATA C298 E@2200P/50V_4X INT_LCD_EDIDCLK C300 E@2200P/50V_4X 31 C284 0.1U/10V_4X 50373-03001-002 C288 22P/50V_4N +3VPCU 32 C285 0.1U/10V_4X C3A B B CRT [CRT] C289 2 D26 L18 CRT@BLM18BA470SN1D_300MA CRT_RED_L FCH_CRT_GRE L19 CRT@BLM18BA470SN1D_300MA CRT_GRE_L FCH_CRT_BLU L20 CRT@BLM18BA470SN1D_300MA CRT_BLU_L 1 CRT@SS14L_1A 2 F3 1 5V_CRT2 CRT@SMD1206P110TFT 16 +5V FCH_CRT_RED [email protected]/16V_4Y +3V +5V 6 1 7 2 8 3 9 4 10 5 CRT_RED_L B2A [9] FCH_CRT_RED FCH_CRT_RED [9] FCH_CRT_GRE FCH_CRT_GRE [9] FCH_CRT_BLU FCH_CRT_BLU C291 [email protected]/16V_4Y C290 [email protected]/16V_4Y CRT_GRE_L CRT_BLU_L C295 C296 C297 [email protected]/50V_4N [email protected]/50V_4N [email protected]/50V_4N FCH_CRT_HSYNC FCH_CRT_VSYNC [9] FCH_CRT_HSYNC [9] FCH_CRT_VSYNC R185 +3V FCH_DDCDAT FCH_DDCCLK [9] FCH_DDCDAT [9] FCH_DDCCLK R187 +5V 12 CRTDDAT 13 CRTHSYNC 14 CRTVSYNC 15 CRTDCLK [email protected]_4 FCH_DDCDAT 17 C292 C293 C294 R181 R182 [email protected]/50V_4N [email protected]/50V_4N [email protected]/50V_4N CRT@150/F_4 CRT@150/F_4 CRT@150/F_4 R180 11 [email protected]_4 FCH_DDCCLK CN11 CRT@DHR48-15K1200 U12 +3V 5V_CRT2 +5V C303 C304 [email protected]/25V_6X [email protected]/25V_6X C299 1 VCC_SYNC SYNC_OUT2 SYNC_OUT1 7 8 VCC_DDC [email protected]/10V_4X BYP 2 +3V VCC_VIDEO SYNC_IN2 SYNC_IN1 16 14 VSYNC1 HSYNC1 15 13 FCH_CRT_VSYNC FCH_CRT_HSYNC 10 11 FCH_DDCCLK FCH_DDCDAT 9 12 CRTDCLK CRTDDAT R190 R191 5V_CRT2 R192 CRT_RED_L CRT_GRE_L CRT_BLU_L A 3 4 5 6 VIDEO_1 VIDEO_2 VIDEO_3 GND DDC_IN1 DDC_IN2 DDC_OUT1 DDC_OUT2 CRTVSYNC CRTHSYNC CRT@39/F_4 CRT@39/F_4 C301 CRT@10P/50V_4C C302 CRT@10P/50V_4C R193 [email protected]_4 [email protected]_4 A CRT@IP4772CZ16 C305 CRT@10P/50V_4C C306 CRT@10P/50V_4C Quanta Computer Inc. PROJECT :BY6/BY6D Size Document Number Rev 1A LVDS/CCD/DRT Date: 5 4 3 2 Tuesday, February 14, 2012 1 Sheet 32 of 47 5 4 3 2 1 33 SATA ODD [ODD] B2A +5V_ODD CN12 GND14 D GND1 RXP RXN GND2 TXN TXP GND3 DP +5V +5V RSVD GND GND GND15 14 B2A 1 2 3 4 5 6 7 +5V L23 HCB1608KF-121T30_3A D C426 8 9 10 11 12 13 SATA_TXP1_C SATA_TXN1_C C812 C808 0.01U/25V_4X 0.01U/25V_4X SATA_RXN1_C SATA_RXP1_C C311 C312 0.01U/25V_4X 0.01U/25V_4X ODD_PRSNT# R303 SATA_TXP1 [9] SATA_TXN1 [9] 0.1U/10V_4X C3A SATA_RXN1 [9] SATA_RXP1 [9] 1K/F_4 +5V_ODD +5V_ODD 15 C313 C314 C315 C316 C317 *0.1U/10V_4X *0.1U/10V_4X 0.1U/10V_4X 0.1U/10V_4X 10U/6.3V_8X + C318 *100U/6.3V_3528P_E45b B2A C18526-11305-L C C SATA HDD [HDD] CN13 GND23 B GND1 RXP RXN GND2 TXN TXP GND3 3.3V 3.3V 3.3V GND GND GND 5V 5V 5V GND RSVD GND 12V 12V 12V GND24 B2A 23 1 2 3 4 5 6 7 B2A SATA_TXP0_C SATA_TXN0_C C817 C815 0.01U/25V_4X 0.01U/25V_4X SATA_RXN0_C SATA_RXP0_C C321 C322 0.01U/25V_4X 0.01U/25V_4X SATA_TXP0 [9] SATA_TXN0 [9] SATA_RXN0 [9] SATA_RXP0 [9] B 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 B2A +5V_HDD1 24 B2A R201 C325 C326 C327 0.1U/16V_4Y 0.1U/16V_4Y 10U/6.3V_8X *SHORT_8 +5V + C328 *100U/6.3V_3528P_E45b SAT-22ESAB A A Quanta Computer Inc. PROJECT :BY6/BY6D Size Document Number Rev 1A HDD/ODD Date: 5 4 3 2 Sheet Tuesday, February 14, 2012 1 33 of 47 5 4 3 2 1 34 +3V_GPU <THC> 2 Thermal Sensor [27,36] 3ND_MBCLK D 6 1 GPU_SMBCLK [15] GPU_SMBCLK D Q19A EV@2N7002KDW_115MA B2A Del 0_4 5 +3V_GPU [27,36] 3ND_MBDATA 3 Q19B 4 GPU_SMBDAT GPU_SMBDAT [15] EV@2N7002KDW_115MA C C Thermal Ext Thermal EC(M) 3ND_SMB dGPU Int Thermal U13 dGPU int SMBUS EC(M) 3ND_SMB dGPU(M) SMB dGPU int SMBUS U13 B B +3V FAN Control <THC> +5V R217 51!NJM FANPWR = 1.6*VSET U14 C358 2 2.2U/6.3V_4X VIN VO GND /FON GND GND VSET GND 1 4 [36] VFAN1 APE8872M 8 7 6 5 3 5 6 7 8 *10K_4 51!NJM [36] FANSIG1 +5V_FAN FANSIG1 C569 C359 C360 2.2U/6.3V_6X 0.01U/25V_4X *0.01U/25V_4X CN17 1 2 3 C3A 50273-0037L-001 B2A G995 layout notice Gnd shape A D28 D29 2 1 2 *VPORT 0603 220K-V05 1 +5V_FAN FANSIG1 A 1 2 3 4 Quanta Computer Inc. *VPORT 0603 220K-V05 PROJECT :BY6/BY6D Size Document Number Rev 1A THERMAL Date: 5 4 3 2 Tuesday, February 14, 2012 Sheet 1 34 of 47 5 4 3 KEY BOARD Connector <KBC> <EMI> INT KeyBoard 2 1 35 <TPD> <EMI> TOUCH PAD BOARD CN14 36 D3A D C329 C330 C331 C333 ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N MX7 MX2 MX3 MX4 C337 C338 C339 C340 ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N MX0 MX5 MX6 MX1 C341 C342 C343 C344 ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N MY7 MY13 MY12 MY15 C345 C346 C347 C348 ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N MY3 MY5 MY14 MY6 C349 C350 C351 C352 ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N ESD@39P/50V_4N MY2 MY1 MY0 MY4 C357 C373 ESD@39P/50V_4N ESD@39P/50V_4N MY16 MY17 CN15 C [36] TPCLK [36] TPDATA MY16 [36] MY17 C332 4.7U/6.3V_6X MY17 [36] K_LED_P MY2 MY1 MY0 MY4 MY3 MY5 MY14 MY6 MY7 MY13 MY8 MY9 MY10 MY11 MY12 MY15 MX7 MX2 MX3 MX4 MX0 MX5 MX6 MX1 K_LED_P CAPSLED K_LED_P C3A C5547 [email protected]/16V_4X C3A MY2 [36] MY1 [36] MY0 [36] MY4 [36] MY3 [36] MY5 [36] MY14 [36] MY6 [36] MY7 [36] MY13 [36] MY8 [36] MY9 [36] MY10 [36] MY11 [36] MY12 [36] MY15 [36] MX7 [36] MX2 [36] MX3 [36] MX4 [36] MX0 [36] MX5 [36] MX6 [36] MX1 [36] [7,9] BOARD_ID10 +3V C335 C336 *10P/50V_4C *10P/50V_4C C5561 E@2200P/50V_4X CAPSLED default Metal/IMR H TEXTURE L D 88513-064N C5548 [email protected]/16V_4X B2A Power Board (UIF) <PSW> CN23 [36] TPCLK [36] TPDATA +3V SMB_RUN_DAT SMB_RUN_CLK [7,12,13] SMB_RUN_DAT [7,12,13] SMB_RUN_CLK 1 2 3 4 5 6 7 8 C *50503-0080N-001 88513-044N D31 C3A +3VPCU [7,9] BOARD_ID10 1 2 3 4 NBSWON# 1 2 3 4 5 6 7 8 +5V_TP TPCLK_L TPDATA_L +5V CAPSLED [36] B2A 91504-344N ID_Detect TP board <TPD> CN16 35 1 2 3 4 5 6 C3A [36] NBSWON# ESD Issue 1 2 3 4 5 6 +5V_TP +5V K_LED_P MY16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 C354 220P/50V_4X *AZ5125-01J RP25 MX7 MX2 MX3 MX4 K_LED_P <OTH> HOLE8 +5V +5V R574 R573 R572 B C319 C320 C334 C356 HOLE9 C402 C429 *0_4 *0_4 *0_4 *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X HOLE11 HOLE12 C3A *H-TC276BC217D146P2 *0.1U/10V_4X HOLE10 +5V 1 +5V 1 +5V 1 +5V *H-TC276BC217D146P2 HOLE1 HOLE2 HOLE3 C3A *H-C256D146PT *H-TC276BC217D146P2 B *H-C256D146PT *H-TC315BC276D118P2 1 <EMI> 1 HOLE EMI PAD 1 150_4 1 10KX8 2 3 4 5 1 R205 +3V 10 9 8 7 6 MX1 MX6 MX5 MX0 C355 220P/50V_4X 1 C353 220P/50V_4X *H-TC315BC276D118P2 *0.1U/10V_4X ADOGND C436 C549 C550 *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *0.1U/10V_4X *H-C276D118P2 *H-C91D91N *H-C91D91N HOLE7 *H-BC236D161PB 1 C432 *0.1U/10V_4X HOLE6 1 C431 HOLE5 1 +3V HOLE23 1 +3V HOLE22 1 +3V HOLE21 1 +3V B2A HOLE20 1 +3V *H-TC276BC236D118P2 *H-BC236D161PB *H-BC236D161PB *H-C91D91N B2A VIN C554 C555 C559 C561 C563 [email protected]/25V_4X *0.1U/25V_4X *0.1U/25V_4X E@1U/25V_6X [email protected]/25V_6X [email protected]/25V_6X 7 8 9 +1.5VSUS HOLE15 6 5 4 7 8 9 1 2 3 C553 B2A HOLE14 6 5 4 *HG-C276D118P2-A HOLE16 6 5 4 7 8 9 *HG-C276D118P2 HOLE17 6 5 4 7 8 9 *HG-C276D118P2 HOLE18 6 5 4 7 8 9 *HG-C276D118P2 HOLE19 6 5 4 7 8 9 1 2 3 VIN 1 2 3 VIN 1 2 3 VIN 1 2 3 VIN 1 2 3 VIN *HG-C276D118P2 *HG-C276D118P2 A A C558 HOLE24 HOLE25 HOLE26 HOLE27 E@680P/50V_4X *H-C236D118P2 1 1 1 1 Quanta Computer Inc. *H-TC197BC131D91P2 B2A Fan 5 4 3 PROJECT : BY6/BY6D *H-TC197BC131D91P2 *O-BY6D-1 Size Document Number Date: Tuesday, February 14, 2012 Rev 1A KBC/TP/FP CONN. B2A ODD 2 Sheet 1 35 of 47 5 4 3 2 1 36 Intel Turbo mode only <CPU> EC <KBC> 3 H_PROCHOT# [5,8] Q23 +3VPCU C3A L21 +A3VPCU HCB1608KF-601T10_1A +3V_VDD_EC R223 2 H_PROCHOT_EC +3V 2.2_6 126 127 128 1 2 8 CLKRUN# [8] CLKRUN# 121 [7] EC_A20GATE 122 [7] EC_KBRST# 29 SCI#_uR [7] EC_EXT_SCI# 124 [7] LPCPD# 7 [8,30,31] PLTRST# 123 [25] USB_NORMAL_EN# 125 SERIRQ [8] SERIRQ 9 [7,25] USB_NORMAL_OC# C MX0 MX1 MX2 MX3 MX4 MX5 MX6 MX7 [35] [35] [35] [35] [35] [35] [35] [35] [35] [35] [35] [35] [35] [35] [35] [35] [35] [35] MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16 MY17 54 55 56 57 58 59 60 61 53 52 51 50 49 48 47 43 42 41 40 39 38 37 36 35 34 33 [7,37] MBCLK [7,37] MBDATA [5] 2ND_MBCLK [5] 2ND_MBDATA [27,34] 3ND_MBCLK [27,34] 3ND_MBDATA 70 69 67 68 119 120 2ND_MBCLK 2ND_MBDATA 3ND_MBCLK 3ND_MBDATA 72 71 10 11 [35] TPCLK [35] TPDATA [8,24,44] PE_PWRGD [25] USB_SC_EN# 77 [8,11] RTC_CLK 12 13 PCLK_591 10U/6.3V_6X GPIO11/CLKRUN R257 R258 10K_4 10K_4 SERIRQ CLKRUN# 97 98 99 100 108 96 95 94 *100K/F_4 +3VPCU SM BUS PU TEMP_MBAT [37] ICMNT [37] AC SET_EC [37] USB_BUS_SW4 [25] USB_SC_OC# [7,25] TP8 ICMNT AC SET_EC USB_BUS_SW4 NBSWON#_R D/A GPIO94/DA0 GPIO95/DA1 GPIO96/DA2 KBRST/GPIO86 LPC ECSCI/GPIO54 GPIO24 GPIO01/TB2 GPIO02 GPIO06/IOX_DOUT GPIO16 GPIO30 GPIO36 GPIO41 GPIO42/TCK GPIO43/TMS GPIO44/TDI GPIO GPO47/SCL4 GPIO50/PSCLK3/TDO GPIO51 GPIO52/PSDAT3/RDY GPIO53/SDA4 GPIO70 GPIO71 GPIO72 GPIO75 GPO76/SHBM GPIO77 GPIO81 GPO82/IOX_LDSH/TEST GPO84/IOX_SCLK/XORTR GPIO97 GPIO10/LPCPD LREST GPIO67/PWUREQ SERIRQ GPIO65/SMI KBSIN0 KBSIN1 KBSIN2 KBSIN3 KBSIN4 KBSIN5 KBSIN6 KBSIN7 KBSOUT0/JENK KBSOUT1/TCK KBSOUT2/TMS KBSOUT3/TDI KB KBSOUT4/JENO KBSOUT5/TDO KBSOUT6/RDY GPIO56/TA1 TIMER GPIO20/TA2/IOX_DIN_DIO KBSOUT7 KBSOUT8 GPIO14/TB1 KBSOUT9/SDP_VIS KBSOUT10/P80_CLK KBSOUT11/P80_DAT GPIO15/A_PWM KBSOUT12/GPIO64 GPIO21/B_PWM TIMER KBSOUT13/GPIO63 GPIO13/C_PWM KBSOUT14/GPIO62 GPIO32/D_PWM KBSOUT15/GPIO61/XOR_OUT GPIO45/E_PWM GPIO60/KBSOUT16 GPIO40/F_PWM GPIO57/KBSOUT17 GPIO66/G_PWM GPIO33/H_PWM GPIO17/SCL1 GPIO22/SDA1 GPIO73/SCL2 GPIO74/SDA2 GPIO23/SCL3 GPIO31/SDA3 GPIO34 SMB GPIO87/SIN_CR GPIO46/TRST GPO83/SOUT_CR/TRIST IR GPIO37/PSCLK1 GPIO35/PSDAT1 GPIO26/PSCLK2 GPIO27PSDAT2 PS/2 FIU GPIO00/EXTCLK F_SDI/F_SDIO1 F_SDIO&F_SDIO0 F_CS0 F_SCK GPIO55/CLKOUT/IOX_DIN_DIO L22 0_6 *22_4 +3V_S5 R261 *10P/50V_4C B2A 10K_4 R202 1 1.2K/F_4 NBSWON# [35] VCC_POR VREF 6 64 79 93 114 109 15 80 17 20 21 24 25 26 27 28 73 74 75 82 83 84 91 110 112 107 TP9 VFAN1 [34] TP10 MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA 3ND_MBCLK 3ND_MBDATA B2A EC_FPBACK# [32] ACIN [37] SKU_STRAP_2 SKU_STRAP_3 H_PROCHOT_EC B2A Strap TP5 AMP_MUTE# [29] ID [37] USB_BUS_SW3 [25] D/C# [37] S5_ON [38] USB_BUS_SW3 2 <KBC> 0_4 A0H VGA Board Thermal Sensor 98H HDMI CEC 34H Light Sensor 52H R231 10K_4 DISPON_I [32] ID EEPROM <KBC> B2A +3VPCU U16 6 5 2ND_MBCLK 2ND_MBDATA Exchange GPIO36 and GPIO77 SCL SDA 7 WP Remove Zero Power ODD funciton +1.1V_EN_EC [41] 1 2 3 A0 A1 A2 0.003A(20mils) C 8 4 VCC GND C371 M24C08-WMN6TP 0.1U/10V_4X 31 117 63 SKU_STRAP_1 32 118 62 65 22 16 81 66 RF_LED# ADDRESS: A0H TP7 FANSIG1 [34] RF_LED# [31] SUSLED_EC# [31] BAT_SAT0# [31] BAT_SAT1# [31] SUSON [39] MAINON [39,43] CAPSLED [35] 14 EC_Debug 86 87 90 92 SPI_SDI_uR SPI_SDO_uR SPI_CS0#_uR SPI_SCK_uR <KBC> BY6-A1A Del SPI ROM BT_RFCTRL [30] 113 23 111 B2A TP_ON_OFF R239 LAN_P [28] R358 R242 R489 R490 R491 30 85 SPI FLASH *10K_4 +1.1V_DUAL_EN 0_4 *100K/F_4 33_4 33_4 33_4 FCH_SPI_SI +3VPCU [41] [9] FCH_SPI_SO [9] FCH_SPI_CS0# [9] FCH_SPI_CLK [9] MX25L3205DM2I-12G: AKE39FP0Z00 W25Q16BVSSIG: AKE38FP0N01 Make sure that the rise time of VCC_POR is less than 10?sec. VCC_POR# R243 4.7K_4 104 +3VPCU +A3VPCU INTERNAL KEYBOARD STRIP SET D3A +3VPCU <KBC> MY0 NPCE791LA0DX: R245 10K_4 AJ007910F00 (w/o CIR) B LED PU/PD 8769AGND <LED> RF_LED# 1 2 3 EC_Debug ICMNT HWPG circuit <KBC> +5V B2A CN18 TP_ON_OFF R247 10K_4 C3A *DEBUG@50273-0037L-001 +3VPCU +5VPCU C377 C378 *10U/6.3V_8X *10U/6.3V_8X 8769AGND SKU_STRAP_1(GPIO56) A 8769AGND SKU_STRAP_2(GPIO02) SKU_STRAP_3(GPIO41) SKU STRAPPING: Pull H SKU_STRAP_3 For Disctete Pull L SKU_STRAP_3 For UMA Pull SKU_STRAP_1=Lo&SKU_STRAP_2=Hi For 14" SKU 0 0 0 Brazos UMA 0 0 1 Brazos DIS 0 1 0 COMAL UMA 1 1 COMAL DIS 1 0 0 Deccan UMA 1 0 1 Deccan DIS TP interface PU +3V R255 R256 <KBC> *10K_4 *10K_4 PWRLED# R248 +3V 10K_4 R251 SUSLED_EC# R266 10K_4 BAT_SAT0# R259 10K_4 BAT_SAT1# R265 10K_4 10K_4 AMD TPCLK TPDATA R252 *10K_6 D3A [38] SYS_HWPG [39] HWPG_1.5V R254 *SHORT_4 R250 *SHORT_4 HWPG AMD SKU strap pin +3VPCU <KBC> Power Button <KBC> [41] +1.1V_DUAL_PG [40,42,43] VDDA_PWRGD D34 *1SS355_100MA D35 *1SS355_100MA +3VPCU A DNBSWON#_uR R264 10K_4 R263 0 58H Touch Sensor SHBM B2A TP6 32H EC EEPROM Disabled ('1') if using FWH device on LPC. Enabled ('0') if using SPI flash for both system BIOS and EC firmware 0_4 1U/10V_6X SCI#_uR 3 3D Sensor SHBM=0: Enable shared memory with host BIOS R203 SLP_S5# [7] MPWROK [11] RSMRST_GATE# [7] USB_BUS_SW2 [25] RF_EN [30] CEC_EC_HP [27] DNBSWON# [7] 20111003 MPWROK RSMRST_GATE# USB_BUS_SW2 RF_EN R233 4.7K_4 4.7K_4 4.7K_4 4.7K_4 4.7K_4 4.7K_4 RF_EN HWPG DNBSWON#_uR GPIO82 R222 R227 R101 R100 R229 R230 LID591# [32] RUN_1.2V [26] PWRLED# [31] PWRLED# Address Battery PCH SML1 SLP_S3# [7,24] 101 105 106 CloseȱtoȱU11 AC SET_EC SMBUS Devices C3A C374 C375 SMBUS Table <KBC> +3VPCU GPIO85/GA20 NPCE885LA0DX R246 R225 GPIO90/AD0 GPIO91/AD1 GPIO92/AD2 GPIO93/AD3 GPIO05/AD4 GPIO04/AD5 GPIO03/AD6 GPIO07/AD7 A/D +3V B VDD 4 D H=1.6mm LFRAME LAD0 LAD1 LAD2 LAD3 LCLK VTT PECI R224 100K_4 8769AGND VCORF Close to C369 3 [8,30] LFRAME# [8,30] LAD0 [8,30] LAD1 [8,30] LAD2 [8,30] LAD3 [8] PCLK_591 [35] [35] [35] [35] [35] [35] [35] [35] U5030 0.1U/10V_4X AGND ESD@39P/50V_4N 10U/6.3V_6X 44 C574 0.1U/10V_4X 0.1U/10V_4X VCORF_uR C369 0.1U/10V_4X C363 103 C368 0.1U/10V_4X 102 C367 0.1U/10V_4X AVCC C366 0.1U/10V_4X C362 GND1 GND2 GND3 GND4 GND5 GND6 C365 10U/6.3V_6X C361 5 18 45 78 89 116 C364 VCC1 VCC2 VCC3 VCC4 VCC5 D 19 46 76 88 115 D3A C370 1 FDV301N_200MA R221 2.2_6 C376 *0.1U/10V_4X DIS@10K_4 SKU_STRAP_2 NBSWON#_R SW2 *SHORT_ PAD SKU_STRAP_3 SKU_STRAP_1 R267 UMA@10K_4 D36 *LCP0G050M0R2R Quanta Computer Inc. R268 10K_4 PROJECT :BY6/BY6D Size Document Number Date: Tuesday, February 14, 2012 Rev 1A EC NPCE795CA0DX 5 4 3 2 1 Sheet 36 of 47 5 4 3 VA1 PCN1 4 PF1 F1206HA15V024TM 1 2 DC_JACK 0.01_3720 PR1 PD1 3 1 VA2 1 PQ1 TPCA8109 R1 1 VA0 2 2 1 2 3 VA3 2 37 PQ2 TPCA8109 VIN 1 2 3 5 5 BAT-V PC2 E@1000P/50V_4X PC3 0.1U/25V_4X PD2 PR2 220K/F_4 PC4 E@1U/25V_6X 4 PC1 E@1000P/50V_4X 2 1 SBR1045SP5-13 4 3 PR3 33K_6 50322-0044L-001 PR4 10/F_6 RB500V-40_100MA D PR5 10/F_6 ( Near by sense R side) PR7 220K/F_4 1 6 2 5 3 PR8 82.5K/F_6 PR6 10K_6 PC5 E@2200P/50V_4X CSIN 3 TVS_SMAJ20A PD3 2 1 D 4 PQ3 IMD2AT108 +3VPCU PQ4 2N7002K_300MA 2 [36] D/C# B2A [7,36] MBDATA 11 [7,36] MBCLK 9 VDDSMB C 5 21 VDDP CSSN VCC 26 27 1 33 32 31 30 28 +3VPCU PC18 0.1U/10V_4X PC15 *E@10U/25V_8X PC17 1U/6.3V_4X 1 2 B2A B2A ACIN [36] ACIN NC GND GND GND GND CSSP C PR11 4.7_6 PC16 0.1U/10V_4X PC14 *E@10U/25V_8X B2A B2A ( Near by IC side) PC13 10U/25V_8X 1U/6.3V_4X 2 PC12 10U/25V_8X 1 PC11 *2200P/50V_4X PC9 PC10 *0.1U/25V_4X PR9 10K/F_4 VIN PQ5 PR12 2.7_6 BOOT SDA UGATE SCL PHASE PC19 0.1U/25V_6X 4 AON7410 25 24 88731A_U_GATE 23 88731A_PHASE 0.01_3720 PR13 3 2 1 PC8 10U/6.3V_8X PR10 10K/F_4 1 CSIP [36] AC SET_EC PL1 TEMP_MBAT 3 CH4 VN VP CH2 CH3 6 4 MBCLK +3VPCU 3.2V 2 88731ACIN 3 DCIN 5 CSOP VREF 6 BAT-V VBF VCOMP 100/F_4 PC32 0.01U/25V_4X 1 15 PR22 29 100_4 BAT-V (Please place this R near by battery pack side) MBCLK [7,36] 100_4 B2A PC33 10U/6.3V_6X PC31 0.01U/25V_4X 1K_4 TEMP_MBAT [36] 1 PR29 2 16 ICMNT [36] MBDATA [7,36] A CSON PR28 100K_4 47P/50V_4N ( Near by IC side) 17 ( Near by sense R side) CSOP 1 2 *1U/6.3V_4X PR27 2 PC30 PR26 100/F_4 2 47P/50V_4N PC29 PR25 18 PR23 2.21K/F_6 +3VPCU 1 10 PR17 10/F_6 12 7 M-DATA M-CLOCK NC ID [36] TEMP_MBAT_C PC28 PR16 10/F_6 PC23 *1000P/50V_4X GND GND 0_4 ID PR14 *2.2/F_6 AON7410 NC 14 B2A PQ6 4 B ICOMP ICM PF2 F1206HA15V024TM 1 2 88731A_L_GATE PC24 0.1U/25V_4X 8 MBAT+ PR50 BTS1E-9K8040 PGND 20 19 ACIN NC 11 PU1 ISL88731CHRTZ-T NC PR21 0_4 PCN2 LGATE CSON 4 B2A PR20 *100K_4 B2A 22 DCIN PR19 22K/F_6 B ACOK PC20 0.1U/25V_6X PR15 49.9/F_6 +3VPCU PR18 82.5K/F_6 1 2 3 4 5 6 7 8 9 13 MBDATA 5 BAT-V 3.3UH_7X7_TOK PC22 10U/25V_8X CH1 2 PC21 10U/25V_8X 2 B2A 3 2 1 1 ID 1 5 10 PD4 TVLST2304AD0 B2A PC34 0.01U/25V_4X A B2A Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Date: Tuesday, February 14, 2012 Rev CHARGER (ISL88731C) 5 4 3 2 Sheet 1 1A 37 of 47 5 4 3 2 1 VIN VIN PC38 10U/25V_8X +5VPCU 10U/6.3V_6X PR36 [email protected]/F_6 C 5V_FB1 24 2 4 PQ9 PC46 E@1000P/50V_4X 330U/6.3V_105CS_E17f 23 AON7702A 1 PHASE2 TOP Side LGATE1 LGATE2 VOUT1 FB1 PGOOD 5 2 17 3 REF 2 8 VREG3 RT8223P 1 + DDPWRGD_R 1 2 3 PC45 PR38 *0_2/S 10 BOOT2 PHASE1 PQ8 (Peak 7.0410A, AVG 4.9287A) AON7410 OCP:10A 4 9 3V_UGATE2 PR35 PC44 1 2 11 2.2_6 0.1U/25V_6X 3V_PHASE2 12 3V_LGATE2 +3V_S5 B2A 3 2 1 19 B2A 4 TONSEL SKIPSEL GND GND 20 5V_LGATE1 5 2.2UH_7X7_TOK PR33 *0_2/S B2A UGATE2 BOOT1 PL3 +3.3V_1 2.2UH_7X7_TOK 7 OUT2 EMC +5V_1 B2A 0.1U/25V_6X 2.2_6 5V_PHASE1 B2A PC42 1U/6.3V_4X PR37 3V_FB2 Rds(on) 15m ohm AON7702A PC48 Rds(on) 15m ohm 1 2 PC49 0.1U/25V_6X 2 PD5 BAV99W-7-F_150MA PC47 PR43 330U/6.3V_105CS_E17f PR46 0_6 B2A PR111 10K/F_4 + 6.8K/F_4 *0_4/S PR44 158K/F_4 PR45 10K/F_4 PR39 *0_2/S E@1000P/50V_4X 158K/F_4 +3VPCU C PR40 [email protected]/F_6 PQ10 PR42 PR41 15.4K/F_4 B2A 4 5 FB2 14 25 15 1 2 3 B2A PL2 UGATE1 18 PC43 21 5V_UGATE1 PR34 1 25V_BST1 22 EN ENTRIP2 4 6 13 OCP:10A 16 PU2 VIN AON7410 ENTRIP1 5 PQ7 (Peak 9.6193A ,AVG 6.7335A) +5V_S5 PC41 0.1U/50V_6X VREG5 1 PC40 PR101 0_4 D +2VREF 10U/6.3V_6X +3VPCU B2A 38 2 5 D 1 PR32 2.2/F_6 3 2 1 PC37 0.1U/25V_4X PC35 0.1U/25V_4X PC39 [5,15] SYS_SHDN# PC36 10U/25V_8X VIN PR47 PR103 0_4 10K/F_4 +3VPCU [36] S5_ON 3 PC51 0.1U/25V_6X 1 PR48 *10K/F_4 2 PC50 0.1U/25V_6X 1 DDPWRGD_R PD6 BAV99W-7-F_150MA PR49 +3V_S5 0.1U/25V_6X PC52 22_8 SYS_HWPG [36] +5V_S5 +15V_ALWP +15V B 3 PQ11 5 B AON7406 MAIND TOP Side PQ12 AO6402A TOP Side 3 2 1 4 MAIND 1 2 5 6 [39,43] MAIND 3 4 MAIND +3V A A (Peak 3.3820A, AVG 2.367A) Quanta Computer Inc. +5V (Peak 5.0593A, AVG 3.5415A) PROJECT :BY6/BY6D Size Document Number Rev System 3V/5V(RT8223P) Date: 5 4 3 2 Tuesday, February 14, 2012 Sheet 1 1A 38 of 47 5 4 3 2 1 PR30 S3_1.5V S5_1.5V [36] HWPG_1.5V PR170 MAINON [36,43] VIN 0_4 S5_1.5V PR169 0_4 SUSON [36] D PC53 0.1U/25V_6X PR54 C3A PGND DRVL 4 1.5SUS_HG 1 2 3 13 PL7 1.5UH_10X10 12 1.5SUS_PHASE +1.5VSUS_SRC 11 +5V_S5 PR55 + 2 PQ14 AOL1412 B2A 1 2 3 1 B2A PC60 1U/6.3V_4X PC62 PC61 0.033U/50V_6X PC58 [email protected]/10V_4X *1000P/50V_4X OCP:20A RDSon=5.6m ohm 390U/2.5V_105CS_E10f *2.2/F_6 (Peak 0.1A, AVG 0.07A) C PC59 4 1.5SUS_LG 0_8 +1.5VSUS B2A 5 S5 S3 VDDQSNS 9 SW V5IN PC54 0.1U/25V_4X PQ13 AOL1428A 15 14 10 REFIN GND VTTGND VTTREF TRIP MODE 5 16 17 18 19 20 22 21 PwPad PGOOD DRVH 8 PR56 +SMDDR_VREF VTT 7 5 VBST TPS51216RUKR VREF PC57 4 VLDOIN 24 25 26 B2A 10U/6.3V_8X C 10U/6.3V_8X PC56 3 VTTSNS 6 +1.5VSUS_SRC PwPad-2 2 PwPad-3 PwPad-4 PwPad-5 1 +SMDDR_VTERM PwPad-1 23 2.2/F_6 PU3 B2A PC55 10U/25V_8X D PR52 100K/F_4 PR51 200K_4 S3_1.5V 39 *0_4 B2ABe careful to this two net name. (Peak 19.08A, AVG 13.356A) ESR : 9mȍ B2A B f : 400k Hz PR58 10K/F_4 PR143 R1 *100_4 Vout = (R1/R2) X 0.75 + 0.75 APU_VDDIO_RUN_FB_H [5] 3 0.1U/10V_4X B +1.5VSUS PC63 B2A PR59 57.6K/F_4 R2 [38,43] MAIND MAIND 2 PQ15 PMV45EN_4A PC65 0.01U/25V_4X 1 C3A +1.5V (Peak 0.375A, AVG 0.2625A) A A Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev +1.5VSUS (TPS51216RUKR) Date: 5 4 3 2 Tuesday, February 14, 2012 Sheet 1 39 1A of 47 5 4 3 2 1 40 D D B2A PC126 PQ20 2 1U/6.3V_4X 4 1 16 R2 PR119 R1 B 10K/F_4 SW VFB PGOOD TST DRVL GND GND 12 2 PR150 PR121 470K/F_4 DRVH EN 9 1 OCP:9A 2 2.2_6 (Peak 8.5A, AVG 5.95A) 51211_DRVH_2 0.1U/25V_6X PL18 8 51211_SW_2 2.2UH_7X7_TOK 1 6 11 +3V_S5 *10K_4 +1.2V_VDDPR B2A +1.2V_VDDPR_PG PR149 PC286 PR105 0.1U/10V_4X + 4 51211_DRVL_2 *2.2/F_6 B2A PQ19 AON7702A 7.15K/F_4 PC285 B *1000P/50V_4X RDSon=13m ohm PC287 2 C 3 2 1 10 PC282 GND 5 2 B2A 4 51211_VFB_2 1 PC283 *1U/6.3V_4X TRIP GND 3 51211_EN_2 VBST PR148 15 0_4 [36,42,43] VDDA_PWRGD V5IN GND 2 GND PR120 7 51211_V5IN_2 13 PR141 105K/F_4 1 2 TPS51211DSCR 5 PU12 14 B2A C AON7410 B2A 3 2 1 1 PC284 0.1U/25V_4X B2A 5 +5V_S5 PC129 10U/25V_8X VIN 1 PC111 *39P/50V_4N 330U/2V_7343P_E9c Vout=0.704V*(R1+R2)/R2 PR31 *100_4 PR24 *100_4 APU_VDDP_FB_H [5] APU_VDDR_FB_H [5] Quanta Computer Inc. A PROJECT : BY6/BY6D Size Document Number Rev 1A +1.2V_VDDPR (TPS51211DSCR) Date: 5 4 3 2 Sheet Tuesday, February 14, 2012 1 40 of 47 A 5 4 3 2 1 41 PC130 10U/25V_8X VIN D +5V_S5 B2A PC127 PQ22 2 B2A +1.1V_VFB 4 +1.1V_TST 5 16 PR328 1 C 100K/F_4 2 PC265 *1U/6.3V_4X 1 0_4 B2A PR123 10K/F_4 DRVH EN SW VFB R1 PGOOD TST DRVL GND GND GND R2 12 2 PR152 PR124 470K/F_4 TRIP 10 +1.1V_VBST 9 +1.1V_DRVH 8 +1.1V_SW 1 +1.1V_PGOOD 6 +1.1V_DRVL PC264 2.2_6 0.1U/25V_6X 1 F: 320k Hz 2 PL17 2.2UH_7X7_TOK 11 +3V_S5 *10K_4 C PR151 PR106 4 PC268 *2.2/F_6 0.1U/10V_4X + B2A PQ21 AON7702A 5.76K/F_4 PC269 *1000P/50V_4X RDSon=13m ohm PC270 2 +1.1V_DUAL B2A +1.1V_DUAL_PG [36] GND 3 GND 2 +1.1V_EN VBST Total capacitor : 400uF 4 PR153 15 +1.1V_TRIP PR122 [36] +1.1V_DUAL_EN V5IN GND 2 7 14 1 +1.1V_V5IN 13 PR142 75K/F_4 TPS51211DSCR 5 PU17 3 2 1 1U/6.3V_4X OCP:6A (Peak 5.15A, AVG 3.605A) AON7410 3 2 1 1 D 5 B2A PC267 0.1U/25V_4X 1 PC112 *39P/50V_4N 330U/2V_7343P_E9c Vout=0.704V*(R1+R2)/R2 +1.1V_DUAL +15V B2A B PR214 1M/F_4 1 2 5 6 B +5V_S5 3 PQ63 AO6402A 3 2 1 RB500V-40_100MA *0_4 1 PR218 A 2 [36] +1.1V_EN_EC 1 PD9 [11,42] VRM_PWRGD PQ65 2N7002K_300MA 0_4 3 2 PQ64 2N7002K_300MA PC189 *2200P/50V_4X PR215 10K/F_4 PR216 10K/F_4 PR217 4 +3V +1.1V (Peak 1.145A, AVG 0.802A) A PC190 *1U/10V_4X Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Rev +1.1V_DUAL (TPS51211DSCR) Date: 5 4 3 2 Sheet Tuesday, February 14, 2012 1 1C 41 of 47 3 2 1 VDDNB_CORE 42 PC194 0.1U/50V_6X PC196 10U/25V_8X D1 BOOT_NB PR228 1 2 1 2 1 PR232 100P/50V_4N C3A PWRGD_SVID_REG_VDDNB1 PR233 2 0_4 2 10K_4 +3V_S5 PC133 22U/6.3V_6X PC132 22U/6.3V_6X PC200 PC204 E@1000P/50V_4X *0_4 22U/6.3V_6X 5 7 8 PR229 PC207 1 2 2 VSUMG+ LG1_NB 390P/50V_4X 2 130K/F_4 2 1 2 2 2 1 PC206 PC205 0.068U/10V_4X 0.022U/16V_4X PR231 2.61K/F_4 PR230 11K/F_4 1 1 PC203 1 D + *0_2/S PR227 NTC_10K_6 1 B2A +VDDNB_CORE PR224 [email protected]/F_4 C3A PC202 330P/50V_4X 1 2 2 0.24UH_7X7 PR206 1 PL13 C3A PR205 PR226 2K/F_4 1 9 PH1_NB 10_4 1000P/50V_4X 2 B2A *0_2/S PR225 634/F_4 2 VSUMG- 0_4 PC198 1 S2 301/F_4 2 S2 PR223 1 C3A 0.22U/25V_6X S2 C3A 2.87K/F_4 2 2.2_6 +VDDNB_CORE G2 PC199 0.1U/10V_4X 1 2 PR221 1 PR220 2 1 S1/D2 D 2 6 PR219 1 560U/2V_7343P_E4.5a_3pin PC131 D1 D1 G1 PC197 PR222 330P/50V_4X 2 [5] PQ68 FDMS3606S PC193 10U/25V_8X C3A 1 APU_VDDNB_RUN_FB_H PC192 2200P/50V_6X VIN UG1_NB PC191 PC134 4 22U/6.3V_6X 5 B2A PWRGD_VDD_VDDNB PR234 VSUMG+ 1 VSUMG- 1 2 3.65K/F_6 PR235 *43.2K/F_4 PR236 PC208 1 2 +5V_S5 1 2 1/F_6 PH1_NB 0.1U/50V_6X 10K_4 UG1_NB 1 1 PC211 0.1U/50V_6X PC214 10U/25V_8X 2 PC213 10U/25V_8X 0.24UH_7X7 2 PC221 E@1000P/50V_4X +5V_S5 0_6 B2A PC137 + PR253 1 22U/6.3V_6X LGATE2 1/F_6 PC219 UGATE1 2 PR208 25 1 *0_2/S PHASE1 PR207 26 22U/6.3V_6X PR248 PC136 PR247 [email protected]/F_4 LGATE1 *0_2/S PHASEX PC210 2200P/50V_6X +VDD_CORE PL14 22U/6.3V_6X 1U/10V_4X PC212 100U/25V_105CE_f C3A 560U/2V_7343P_E4.5a_3pin PC217 2 1 9 2 5 2 6 1 PHASE2 7 38 37 28 27 BOOT1 PGOOD 1 24 FB FB2 COMP 23 22 21 20 RTN 19 C3A VSEN UGATE1 PAD B2A BOOT1 1 PR309 2 PR254 PWRGD_VDD_VDDNB +5V_S5 0_4 ISEN2 PR255 2K/F_4 1 1 2 B UGATEX 40 39 LGATEX 41 FCCM PWM2_NB 43 45 46 42 COMP_NB PGOOD_NB FB_NB VSEN_NB 47 NTC 13 PR252 PC220 133K/F_4 0.1U/50V_6X 1 49 PHASE1 18 12 IMON ISUMN NTC_CPU 27.4K/F_4 2 PR251 NTC_470K_4 1 2 2 PR250 1 LGATE1 1U/10V_4X 2 S2 9.76K/F_4 2 B2A 11 PWM_Y PWROK BOOT2 PC215 1 29 VDD ENABLE LGATE2 PQ69 FDMS3606S S2 10 IMON_CPU VDDP SVT 9 ENABLE [5] APU_PWRGD_SVID_REG PHASE2 30 PC216 0.22U/25V_6X 1 2 + D1 VDDIO 32 31 PR243 2.2_6 S2 8 LGATE2 ISL6277HRTZ-T 0.1U/50V_6X D1 SVT PHASE2 PU14 SVD UGATE2 G2 7 BOOT2 C S1/D2 [5] APU_SVT [36,40,43] VDDA_PWRGD VDDIO 34 33 C3A D1 +1.5VSUS 0_4 2 0_4 2 0_4 2 UGATE2 PC209 1 2 G1 PR244 1 PR245 1 PR246 1 BOOT_NB 35 UGATE2 VR_HOT_L 6 [5] APU_SVD 36 BOOT2 SVC 5 [5] CORE_PWM_PROCHOT# PR249 1 IMON_NB 4 VIN 0_6 VIN ISUMP 3 [5] APU_SVC VDD_CORE PR241 2 1 BOOTX NTC_NB 17 IMON_NB ISEN2_NB ISEN1 2 16 NTC_NB 15 27.4K/F_4 2 ISEN2 PR242 1 ISEN3 9.76K/F_4 2 14 PR240 1 ISUMN_NB 48 ISEN1_NB 1 C ISUMP_NB 2 PR239 NTC_470K_4 1 2 44 VIN PR238 0_4 PC135 PR237 133K/F_4 8 C3A B2A 2 LG1_NB PR286 2 ISEN1 10K/F_4 ISEN2 VRM_PWRGD [11,41] C3A PR256 3.65K/F_6 VSUM+ PC222 0.22U/25V_6X PR257 PC224 1 1 VSUM- 2 PC223 330P/50V_4X 1 2 1/F_6 B VSUM- 10P/50V_4N 2 PR258 ISEN1 PC225 0.22U/25V_6X *10K/F_4 PC226 1 100P/50V_4N 2 PC228 1 390P/50V_4X 2 VSUM+ 8 1 2 1 PC238 0.1U/10V_4X 2 PC239 0.01U/25V_4X 1 10_4 PC230 0.1U/50V_6X PC229 10U/25V_8X PR268 2 PR270 0.24UH_7X7 C3A S2 [5] S2 APU_VDD_RUN_FB_L +VDD_CORE PL15 [email protected]/F_4 LGATE1 PC242 E@1000P/50V_4X + B2A A 560U/2V_7343P_E4.5a_3pin 9 S2 [5] G2 2 APU_VDD_RUN_FB_H PC232 10U/25V_8X PC236 1 2 0.22U/25V_6X PC218 2 2.2_6 PR210 1 PHASE1 PR209 BOOT1 +VDD_CORE *0_2/S 10_4 2 *0_2/S PR264 PR267 1 5 PC237 330P/50V_4X 1 2 B2A PC227 2200P/50V_6X 2 1 PC235 1 2 1000P/50V_4X 6 2.32K/F_4 2 7 1 2 1 2 1 2 301/F_4 2 PR266 1 S1/D2 PR263 1 PQ70 FDMS3606S D1 2 C3A *0_4 D1 1 2 C3A PR269 604/F_4 1 VIN PR261 1 G1 2 130K/F_4 2 D1 PC234 0.068U/10V_4X PC233 0.1U/10V_4X VSUM- PR265 NTC_10K_6 B2A PR262 11K/F_4 PR260 2.61K/F_4 1 UGATE1 PR259 1 C3A B2A A PR271 ISEN1 PD10 ENABLE [5] FS1R2 RB500V-40_100MA 10K/F_4 PR272 3.65K/F_6 VSUM+ PR168 *20K/F_4 PR273 1/F_6 VSUM- Quanta Computer Inc. PR274 PROJECT : BY6/BY6D ISEN2 Size *10K/F_4 4 3 2 Rev CPU_CORE (ISL6277HRTZ-T) Date: 5 Document Number Tuesday, February 14, 2012 1 Sheet 42 1C of 47 5 4 3 2 1 +3V_S5 B2A PU15 G9661-25ADJF12U 4 1 VPP PGOOD PR276 2 [36,39] MAINON VEN VO VIN GND GND NC D VDDA_PWRGD 6 [36,40,42] +2.5V_VDDA 5 0.75A PR277 73.2K/F_6 PC247 10U/6.3V_6X 7 0_4 3 8 9 +3V_S5 ADJ PC243 0.1U/10V_4X D 43 PR275 100K_4 +5V_S5 0.8V PC244 10U/6.3V_6X PC245 0.1U/10V_4X PC246 *0.1U/10V_4X B2A PR278 34K/F_6 C C Vout =0.8(1+R1/R2) =2.5V VIN 1 PR285 22_8 B2A 6 4 5 2 1 2 MAIND [38,39] 3 6 4 5 3 1 PR283 100K_4 PQ90B 2N7002KDW_115MA PR282 1M/F_4 2 [36,39] MAINON PR281 22_8 3 B PR280 1M/F_4 PQ72B 2N7002KDW_115MA PR279 1M/F_4 PQ73 LTC044EUBFS8TL_30MA B2A +3V PQ90A 2N7002KDW_115MA B2A +15V PR284 22_8 B PQ72A 2N7002KDW_115MA B2A PC248 2200P/50V_4X +1.1V +5V Quanta Computer Inc. A PROJECT : BY6/BY6D Size Document Number Rev 1A DISCHARGE Date: 5 4 3 Tuesday, February 14, 2012 2 Sheet 43 1 of 47 A 5 4 3 2 1 +5V_S5 PC253 2 1 44 PR297 EV@1U/10V_4X PR288 [email protected]/F_6 [email protected]/F_6 PVCC PQ99 ISL95870A_AGND BOOT 18 [email protected]/F_6 [email protected]/50V_6X 4 5 GFX_CORE_CNTRL1 [15] GFX_CORE_CNTRL1 RTN UGATE VID1 PHASE PU16 PC281 EV@2200P/50V_4X EV@AOL1428A D Max. DCR=1.2m 17 PL16 [email protected]_10X10-O 1 2 16 EN EV@ISL95870AHRUZ-T 3 15 PR290 EV@0_4 PR301 *EV@10K/F_4 12 11 10 PR287 PR293 [email protected]/F_4 EV@158K/F_4 VO 5 + PQ98 *[email protected]/F_6 EV@TPCA8A09-H 4 PC249 1 2 3 SET1 PE_PWRGD [8,24,36] ISL95870A_AGND C3A C3A OCP:30A (Peak 26.8A ,AVG 18.76A) Total capacitor : 660 uF ESR : 9mȍ f : 300k Hz B2A *EV@1000P/50V_4X PR307 95870A_FB GFX_CORE_CNTRL1 PR302 *EV@10K/F_4 FSEL FB PC255 [email protected]/16V_4X GFX_CORE_CNTRL0 SET0 14 13 PC261 9 PR295 *EV@10K/F_4 PR319 *EV@10K/F_4 PGOOD *[email protected]/50V_6X PR317 [email protected]/F_4 SREF [email protected]/50V_6X 8 OCSET 7 +3V +VGPU_CORE PX_MODE [24] PC274 VID0 PC256 6 GFX_CORE_CNTRL0 EV@560U/2V_7343P_E4.5a_3pin PR303 [15] GFX_CORE_CNTRL0 B2A 4 GND PC279 1 2 3 19 PR323 VCC PR298 3 5 4 PGND EV@10K/F_4 2 EV@0_6 +3V PC280 EV@10U/25V_8X 20 1 LGATE PR305 ISL95870A_AGND D B2A PC257 [email protected]/10V_6X PC250 EV@10U/25V_8X VIN PC251 [email protected]/25V_4X PR299 EV@590K/F_4 Roc [email protected]/F_4 PC262 PR304 EV@10/F_6 PR320 PR326 EV@10/F_6 [email protected]/50V_6X [email protected]/F_4 Csen ISL95870A_AGND PR308 [email protected]/F_4 C B2A C PR314 [email protected]/F_4 PR292 VCORE_VCCSSENSE VCORE_VCCSSENSE [18] [email protected]/F_4 PR291 VCORE_VSSSENSE VCORE_VSSSENSE [18] [email protected]/F_4 GFX_CORE_CNTRL1 GFX_CORE_CNTRL0 +VGPU_CORE 0.9V 0 0.95V 0 1 1.0V 0 0 1.1V +1.5VSUS +3V_S5 +5V_S5 PR310 EV@100K_4 +3V_S5 PX_MODE_D 4 PC266 PR300 EV@100K_4 PR306 [7,24] PE_GPIO1 2 2 1 3 8 9 EV@0_4+3V_S5 VEN VIN GND GND 3 2 1 2 1 3 8 9 HWPG_1.8V_GPU 6 +1.8V_GPU 5 PR325 [email protected]/F_6 VEN VIN GND GND PC272 EV@10U/6.3V_6X +1.5V_GPU (Peak 1.829A ,AVG 1.2803A) NC EV@1U/10V_4X +1.5VSUS 7 PC259 EV@10U/6.3V_6X VO DGPU_PWREN [7,24] PE_GPIO1 PR313 EV@0_4 2 VO 7 B PU18 EV@G9661-25ADJF12U 4 1 VPP PGOOD ADJ PC263 [email protected]/50V_6X EV@AON7202 PU19 EV@G9661-25ADJF12U 4 1 VPP PGOOD (Peak 2.105A ,AVG 1.4735A) 1V_GPU_PG 6 NC 1V_GPU_PG +1V_GPU 1 PQ102 ADJ +5V_S5 5 PR327 [email protected]/F_4 PC275 [email protected]/10V_4X B 2 1 1 5 1 PC271 EV@10U/10V_8X (Peak 5.4A ,AVG 3.78A) PC260 EV@10U/6.3V_6X PC276 [email protected]/10V_4X PC277 *[email protected]/10V_4X PR316 EV@100K/F_4 B2A PC258 [email protected]/10V_4X PC273 *[email protected]/10V_4X Vout =0.8(1+R1/R2) VO=(0.8(R1+R2)/R2) R2<120Kohm PR322 EV@34K/F_6 =1.8V VIN +15V PR318 EV@1M/F_4 PR321 EV@1M/F_4 B2A 2 PX_MODE_D VIN PX_MODE_D B2A 6 4 PQ101A EV@2N7002KDW_115MA 5 PQ101B EV@2N7002KDW_115MA 1 3 PR137 EV@1M/F_4 +1.5V_GPU PQ25 EV@LTC044EUBFS8TL_30MA 5 2 PR289 EV@22_8 A PQ26A EV@2N7002KDW_115MA 2 PE_GPIO1 1 [7,24] PE_GPIO1 1 PR294 EV@22_8 6 3 4 A PR311 EV@22_8 PC254 EV@2200P/50V_4X PR324 EV@100K_4 3 1 [24] PX_MODE PR296 EV@1M/F_4 +3V_GPU PR144 EV@1M/F_4 2 PQ26B EV@2N7002KDW_115MA 3 PQ100 EV@LTC044EUBFS8TL_30MA Quanta Computer Inc. +VGPU_CORE PROJECT : BY6/BY6D Size Document Number Rev +VGPU_CORE (ISL95870AHRUZ-T) Date: 5 4 3 2 Monday, February 13, 2012 1 Sheet 44 of 1A 47 5 4 3 2 1 45 BY6/BY6D Power On Sequence: S5 > S0 +3V_RTC VIN +5VPCU/+3VPCU/+15V ACIN D AC not present equal to LOW; AC present equal to High S5_ON active by pull up 10k to +3VPCU D APU Power on sequence required: EC FW download Llano APU: 1.Group A ( +1.5VSUS, +2.5V_VDDA ) ramp before Group B ( +VDD_CORE, +VDDNB_CORE, +1.2V_VDDPR ) EC SPI signals Power button from switch to EC NBSWON# To turn on dual power rails S5+ NOT implemented S5+ implemented S5_ON/S5_CORE_EN S5_CORE_EN HUDSON-M2/M3: 1.+3V_S5 ramp before +1.1V_DUAL 2.+3V ramp before +1.1V 3.+3V_RTC must ramp at least 5 secs before the +3V_S5 S5+ implemented to turn off dual power rails +3V_S5 EC GPIO46 Enable +1.1V_DUAL +1.1V_DUAL_PG RSMRST_GATE# 2ms 20ms delay at least 50ms Max RTCLK 32ms Min Power button from EC to FCH PWR_BTN#_EC C C SLP_S5# SUSON +1.5VSUS APU GROUP A power +0.75V_DDR_VTT only will be shut down in S3 mode and for DDR3 SODIMM only +0.75V_DDR_VTT VDRAM_PWRGD SLP_S3# MAINON +5V/+3V +2.5V_VDDA +1.5V_RUN/+1.1V/+1.5V VDDA_PWRGD APU GROUP B power Default controlled by +3.3V +VDDNB_CORE B B +VDD_CORE +1.2V_VDDPR VRM_PWRGD +1.2V_VDDPR_PG 98ms < T <150ms FCH_PWRGD 50ms Max APU_CLKP/N 38ms Max APU_PWRGD 101ms < T <113ms A_RST#(PLTRST#) PCIRST# APU_RST# A 75ns < T <100ns 1ms < T <2.3ms A Quanta Computer Inc. PROJECT :BY6/BY6D Size Document Number Date: Monday, February 13, 2012 Rev A1A POWER SEQUENCE 5 4 3 2 1 Sheet 45 of 47 5 4 +5VPCU +-5% AC/DC Insert enable (Peak 0.07A, AVG 0.049A) OCP:0.3A 3 7 AO6402A P.38 2 +5V +-5% MAIND enable +5VPCU +-5% AC/DC Insert enable (Peak 5.0593A, AVG 3.5415A) (Peak 0.07A, AVG 0.049A) +5V_S5 +-5% S5_ON enable D 2 RT8223P P.38 (Peak 9.6193A ,AVG 6.7335A) OCP:10A +3VPCU +-5% AC/DC Insert enable AC DC (Peak 5.1520A, AVG 3.6064A) OCP:10A 3 TPS51216RUKR C OCP:0.3A 8 AON7406 P.38 +3V_S5 +-5% S5_ON enable 1 System Charger ISL88731CHRTZ-T P.37 2 RT8223P P.38 +3V +-5% MAIND enable +2.5V_VDDA +-5% MAINON enable G9661 P.43 (Peak 0.75A) (Peak 7.0410A, AVG 4.9287A) OCP:10A AC +SMDDR_VREF SUSON enable DC 10 ME2306_4A P.39 (Peak 11.5750A, AVG 8.1025A) OCP:20A 1 System Charger ISL88731CHRTZ-T P.37 +SMDDR_VTERM SUSON enable 3 TPS51216RUKR +1.5V +-5% MAIND enable (Peak 0.375A, AVG 0.2625A) (Peak 5.15A, AVG 3.605A) OCP:6A 11 +1.1V +-5% VRM_PWRGD enable AO6402A P.41 (Peak 1.145A, AVG 0.802A) (Peak 19.08A, AVG 13.356A) P.42 (Peak 53A ,AVG 36A) (Peak 5.15A, AVG 3.605A) OCP:6A 9 +3V +-5% MAIND enable AON7406 P.38 (Peak 3.3820A, AVG 2.367A) 10 +2.5V_VDDA +-5% MAINON enable G9661 P.43 (Peak 0.75A) 11 +1.8V_GPU +-5% PE_GPIO1 enable G9661 P.44 (Peak 1.829A ,AVG 1.2803A) 13 ME2306_4A P.39 14 AON7202 P.44 15 AO6402A P.41 D +1V_GPU +-5% PE_GPIO1 enable (Peak 2.105A ,AVG 1.4735A) C +1.5V +-5% MAIND enable (Peak 0.375A, AVG 0.2625A) +1.5V_GPU +-5% PX_MODE_D enable (Peak 5.4A ,AVG 3.78A) +1.1V +-5% VRM_PWRGD enable (Peak 1.145A, AVG 0.802A) B +VDD_CORE +-2% VDDA_PWRGD enable OCP 58A 6 ISL6277HRZ-T +VDDNB_CORE +-2% VDDA_PWRGD enable (Peak 33A ,AVG 25A) OCP:20A 5 +1.1V_DUAL +-5% TPS51211DSCR +1.1V_DUAL_EN enable P.41 +VDD_CORE +-2% VDDA_PWRGD enable ISL6277HRZ-T (Peak 5.0593A, AVG 3.5415A) +1.5VSUS +-3% SUSON enable +1.2V_VDDPR +-5% 4 TPS51211DSCR VDDA_PWRGD enable P.40 (Peak 8.5A, AVG 5.95A) OCP:9A 5 TPS51211DSCR +1.1V_DUAL +-5% +1.1V_DUAL_EN enable P.41 +5V +-5% MAIND enable AO6402A P.38 12 G9661 P.44 +SMDDR_VREF SUSON enable P.39 +1.2V_VDDPR +-5% 4 VDDA_PWRGD enable TPS51211DSCR P.40 (Peak 8.5A, AVG 5.95A) OCP:9A 6 OCP:0.3A 46 8 +3VPCU +-5% AC/DC Insert enable +3V_S5 +-5% S5_ON enable Power Tree Table (DIS) +SMDDR_VTERM SUSON enable +1.5VSUS +-3% SUSON enable (Peak 9.6193A ,AVG 6.7335A) OCP:10A (Peak 0.07A, AVG 0.049A) (Peak 3.3820A, AVG 2.367A) 9 P.39 B OCP:0.3A +5V_S5 +-5% S5_ON enable (Peak 0.07A, AVG 0.049A) Power Tree Table (UMA) 1 P.42 OCP 58A (Peak 53A ,AVG 36A) OCP 58A +VDDNB_CORE +-2% VDDA_PWRGD enable (Peak 33A ,AVG 25A) Power Distribution List 7 OCP 58A +VGPU_CORE +-5% PX_MODE enable ISL95870AHRUZ-T P.44 Power (Peak 26.8A ,AVG 18.76A) OCP:30A Distribution A A Quanta Computer Inc. PROJECT : BY6/BY6D Size Document Number Date: Monday, February 13, 2012 Rev 1A POWER TREE TABLE 5 4 3 2 1 Sheet 46 of 47 5 4 3 2 1 46 MODEL Model REV CHANGE LIST PAGE BY6D FROM D D BY6D MB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 A1A C B DOC NO. 204 PROJECT MODEL : BY6D APPROVED BY: DRAWING BY: PART NUMBER: DATE: Wei-Sheng REVISON: A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A A1A C B 2011/10/02 A1A A A Quanta Computer Inc. PROJECT : BY6D Size Document Number Date: Monday, February 13, 2012 Rev A1A Change List 5 4 3 2 1 Sheet 47 of 47
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