Highly Endurable Floating Body Cell Memory: Vertical Biristor
Dong-Il Moon1, Sung-Jin Choi1, Jee-Yeon Kim1, Seung-Won Ko1, Moon-Seok Kim1,
Jae-Sub Oh2, Gi-Sung Lee2, Min-Ho Kang2, Young-Su Kim2, Jeoung-Woo Kim2, and Yang-Kyu Choi1*
1
Department of EE, KAIST, 2National NanoFab Center, Daejeon 305-701, Korea
*
Email: [email protected], Phone: +82-42-350-3477, Fax: +82-42-350-8565
Abstract
A BJT named ‘biristor’, a term derived from ‘bi-stable
resistor’, is demonstrated for 4F2 high speed volatile memory
applications. For a floating body cell, a gate-less vertical
silicon pillar, which is an n-p-n BJT with an open-base, is
employed, whereas for its control device, a MOSFET
composed of a vertical silicon pillar surrounded by a gate is
utilized. A 4F2 memory cell array is realized by the
unidirectional operation of a vertical two-terminal biristor,
which consists of a cross-bar array. Due to the nature of the
gate-less structure, the biristor cell shows excellent endurance
of up to 1016.
Introduction
As semiconductor memory devices continue to scale down,
the conventional 1T/1C DRAM cell is facing process
challenges due to the high aspect ratio of the capacitor.
Floating body cell (FBC) memories, which have a
capacitor-less cell structure, have been proposed to solve the
aforementioned issues by controlling excess charges in the
floating body (FB) [1-3]. However, one of the disadvantages
of these devices is poor endurance for more than 1016 cycling
operations, because a triggering process to create the excess
charges in the FB inevitably requires a high level of voltage
[4]. As illustrated in Fig. 1, when the energetic carriers are
injected into a gate dielectric, this significantly degrades
reliability characteristics of the FBC memory. On this basis, a
gate-less biristor that shows stable binary resistance states has
been proposed for high-speed and high-density memory
applications [5].
In this work, a vertically integrated bipolar junction
transistor (BJT), which acts as a biristor, is used as an FBC
memory, and a vertical gate-all-around (GAA) MOSFET is
used as a control device to evaluate the memory performances
of the proposed biristor cell. Both devices are monolithically
integrated; the difference between them arises from whether or
not the structure has a gate. The open-base vertical BJT allows
a 4F2 memory cell array, as can be seen in Fig. 2. The vertical
978-1-4673-4871-3/12/$31.00 ©2012 IEEE
GAA MOSFET can also serve as an FBC memory. The
difference of impact on the memory lifetime between these
two devices is compared and discussed.
Device Fabrication
A schematic of the process flow for the hybrid integration of
the BJT and the MOSFET is shown in Fig. 3. The silicon (Si)
pillar was vertically patterned by use of an oxide hard mask,
and then the diameter of the Si pillar (Dpillar) was further
reduced by the sacrificial oxidation of up to 22 nm. While the
biristor cell area is screened by an oxide, the GAA MOSFET
area is opened to make a gate dielectric and a gate electrode.
Therefore, the heterogeneous devices can be monolithically
and simultaneously integrated for pair comparisons. SEM and
TEM images of the fabricated devices are shown in Fig. 4. The
non-uniform doping profile along a vertical Si pillar, shown in
Fig. 4(d), is intentionally designed for the unidirectional
operation of the two-terminal BJT in a cross-bar array; thus, it
blocks off sneak paths.
Results and Discussion
By virtue of the vertical cell structure, the biristor and the
GAA MOSFET inherently fulfill the function of a volatile
memory. The transfer characteristic of the vertical GAA
MOSFET, which is utilized as a control device, is shown in
Fig. 5. The bi-stable and unidirectional operation of the
open-base BJT is shown in Fig. 6(a). Current is abruptly
increased by impact ionization as the applied bias is increased.
Additionally, an on-state is maintained until the device
switches to an off-state by the decreased bias. Therefore, the
bi-stable state, which is indispensable for memory applications,
is defined between the latch-up (VLU) and latch-down voltage
(VLD). Each latch voltage is accurately extracted by use of a
differential curve. The cumulative distribution of VLU and VLD
from one hundred devices is plotted in Fig. 6(b). Although VLU
varies considerably, more than 1 V of the read bias window is
guaranteed from the worst case between VLU and VLD. Due to
the asymmetric doping profile near the source (S) and the
drain (D), the BJT gain (β) and the multiplication factor (M)
31.7.1
IEDM12-749
are different according to the reading direction. The latch-up
relation with β and M is summarized in Fig. 7. Because the
doping concentration near D is higher than that near S, β and
M of the forward read (FWD) are higher than those of the
reverse read (REV). Accordingly, VLU,FWD is lower than VLU,REV,
i.e., unidirectional property. If the operational voltage is
selected between VLU,FWD and VLU,REV, the memory cell remains
in the off-state for the REV. This result is also verified by
using numerical simulations, as shown in Fig. 8. In the same
bias condition, the latch process is only triggered for the FWD
via an impact ionization phenomenon. It should be noted that
the unidirectional property of the proposed two-terminal
memory cell prevents sneak path current (Isneak) through
neighboring cells in the cross-bar array and allows the
realization of a 4F2 memory architecture without external
switch elements such as a transistor or a diode, as shown in
Fig. 9. One challenging issue of the biristor is its high
operating voltage. VLU is analyzed for different device
parameters, as shown in Fig. 10. A shortened LB reduces VLU
by virtue of enhanced β, but narrowed Dpillar acts adversely on
the decrement of VLU due to the non-local effect. Thus, a novel
idea, such as lateral bandgap engineering, is required [6]. In
the simulation, SiGe is introduced as a channel material to
reduce VLU, as shown in Fig. 11. As the Ge fraction in the SiGe
alloy increases, the bandgap of the channel material becomes
lowered. Accordingly, required VLU can be reduced by the
enhancement of both M and β. Moreover, the valance band
offset can also improve the retention characteristic of the FBC
memory due to the reduction of hole leakages.
A high speed volatile memory operation with timing
diagram and bias conditions is depicted in Fig. 12. The
memory functions are enabled only for the FWD operation
with the optimized bias conditions. The writing process is
performed with a pulse width down to 5 ns, as shown in Fig.
13. If the excess holes satisfy the minimum requirement to
triggering the latch process, the current flowing through the
base is amplified by an iterative carrier generation regardless
of the write ‘1’ voltage and time condition, i.e., positive
feedback mechanism. For unidirectional and reliable memory
operation, the write ‘1’ and read bias conditions should be
carefully selected, as plotted in Fig. 14. When the read voltage
(VRead) is lower than VLD, the state ‘1’ is not distinguished from
the state ‘0’ after the write ‘1’ process due to the non-activated
latch process. On the other hand, when VRead is higher than VLU,
the state ‘0’ is not distinguished from the state ‘1’ after the
write ‘0’ process due to the unwanted latch process. The
reading operations are also investigated, as shown in Fig. 15.
Non-destructive and multiple read operations after individual
IEDM12-750
hold intervals are realized due to the positive feedback
mechanism for the state ‘1’ and low off-state leakage current
for the state ‘0’; these features can improve operating speed.
The most notable feature of the biristor, compared with
those of other FBC memories, is its superior endurance, which
is due to its gate-less and gate dielectric-free structure.
Because the GAA FET can also be used as an FBC memory,
the memory performances of the biristor and the GAA FET are
compared. In Fig. 16, the memory performance of the GAA
MOSFET is comparable with that of the biristor. However, the
memory operation of the GAA FET, which has a gate and a
gate dielectric, fails after 1011 cycles, as shown in Fig. 17. The
hysteric I-V characteristics after cyclic stress are compared in
Fig. 18. As expected, the biristor shows reliable properties
after more than 1011 write ‘1’/read/write ‘0’/read (W1/R/W0/R)
cycles. The simulation study verifies that the GAA MOSFET
operation is seriously degraded by the hot-carrier injection into
the gate dielectric, as shown in Fig. 19. The hold retention
characteristics of both memory devices are plotted in Fig. 20.
In an un-cycled state, the hold retention of the GAA memory
is better than that of the biristor because the negatively biased
gate holds the excess holes in the FB. However, after cycling
operations, the hold retention of the GAA FET becomes
unstable and worse than that of the biristor due to the
generated interface states.
Conclusions
A vertically integrated biristor was demonstrated for 4F2
memory applications. A silicon pillar was scaled down to a
diameter of 22 nm. A high speed and high endurance volatile
memory with a high sensing current was achieved by the
biristor. The gate-less and gate dielectric-free structure of the
biristor improved the endurance up to 1016. Therefore, the
suggested high density memory architecture can be applicable
for use in embedded and stand-alone memories.
Acknowledgement
This work was supported in part by the Center for Integrated
Smart Sensors funded by the MEST (2011-0031848), by the IT
R&D program of MKE/KEIT (10035320), by the Samsung
Electronics Company, Ltd, and by SK Hynix Semiconductor Inc.
References
[1] S. Okhonin et al., IEDM Tech. Dig., p. 925, 2007.
[2] T.-S. Jang et al., Symp. VLSI Tech. Dig., p. 234, 2009.
[3] I. Ban et al., Symp. VLSI Tech. Dig., p. 159, 2010.
[4] M. Aoulaiche et al., IEEE EDL, vol. 31, p. 1380, 2010.
[5] J.-W. Han et al., Symp. VLSI Tech. Dig., p. 171, 2010.
[6] S.-J. Choi et al., IEDM Tech. Dig., p. 532, 2010.
31.7.2
D
Drain current, ID (A)
S
Charge barrier
Gate
D
Charge barrier
Gate
S
10
-10
10
-12
After FBC
operation
10
-14
-1.0
Charge barrier
-0.5 0.0 0.5 1.0
Gate voltage, VG (V)
Fig. 1 (a) Operational principle of the FBC memory. A binary memory
state is defined by the existence of excess charges in the FB. Excess
charges are generated by impact ionization, but it causes damage to the
gate dielectric. (b) ID vs. VG of a GAA MOSFET. After the cycling test of
the FBC memory, the device characteristics are significantly degraded.
n+
Hard mask
1
D
Silicon
pillar
p
n+
S
D
p
FB
n+
S ILD1
3
Vertical FET
D Gate
n+
Biristor
4
p
S ILD1
n+
Metal line
ILD oxide
ILD2
D
p
G
n+
S ILD1
1 μm Si pillar
10
10
-8
-10
Current (mA)
10
(a)0.8
VD = 0.3 V, 1 V
VT = 0.3 V
DIBL = 8 mV/V
SS = 75 mV/dec
7
Ion/Ioff = 10
-12
Dpillar = 22 nm
LG = 150 nm
-14
-1.8 -1.2 -0.6 0.0 0.6 1.2 1.8
Gate voltage, VG (V)
Fig. 5 ID versus VG of the vertical
GAA MOSFET integrated with the
open-base BJT. Reasonable DIBL,
subthreshold swing (SS), and offstate leakage (Ioff) are achieved.
(a)
4
5
6
Voltage (V)
6
5 Forward direction
4
3
VLD
2
1
0
0
4
5
6
Voltage (V)
D
D
S
S
Electric field
VREV
= 6.5 V
D
p
G
n+
As
B
P
0.1
0.2
0.3
Dpillar
S
0.4
0.5
Vertical FET
17
18
19
20
10 10 10 103
Conc. (Atoms/cm )
VLD
VLU
VLU
80
60
ΔV
ΙD =
40
20
0
4
5
Voltage (V)
6
Unit (cm-3·s-1)
D
(a)
1030
1018
S
S
VREV
= 6.5 V
Fig. 7 Latch-up conditions. Base
current (IB) originates from impact
ionization. Due to the asymmetric
doping, M and β are different
according to the reading direction.
VRead
Isneak
Bidirectional
Impact ionization rate
Fig. 8 (a) E-field distribution and (b) impact ionization rate according to
reading directions. M is proportional to the electric field. Due to the higher
doping concentration near D, M and β of the FWD are higher than those
values of the REV. Thus, the impact ionization rate of the FWD, which
represents the latch-up phenomenon, is much higher than that of the REV.
Latch condition: (M-1)·β = 1
MFWD > MREV, βFWD > βREV
(b)
VRead
D
Μ ⋅β
IB
1 − ( M − 1) ⋅ β
Off
1.3
substrate
100 nm (d)
n+
22 nm
D
Off
VFWD
= 6.5 V
2.1
4F2 biristor array
Fig. 6 (a) Hysteric I-V curves of the vertical biristor with different
reading directions. The bi-stable state is only observed for FWD. Two
different peak points, which are obtained from the derivative of I with
respect to V, are defined as VLU and VLD. (b) Distribution of VLU and VLD
satisfies the sensing voltage window (ΔV) of 1 V in the forward direction.
Unit (MV/cm) (b)
VFWD
= 6.5 V
n Bulk silicon
100
0.0
0
G
(b)
Dpillar = 22 nm
0.6 LB = 150 nm
FWD
0.4
REV
0.2
dI /dV (mA/V)
Drain current, ID (A)
10
-6
p
Fig. 4 (a) Tilted SEM image of as-fabricated vertical Si pillars. TEM images of a vertical BJT
and a GAA MOSFET are shown in (b) and (c). Diameter (Dpillar) and height of the Si pillar are
22 nm and 500 nm, respectively. Base (LB) and gate length (LG) are 150 nm. (d) The SIMS
profile is depicted from D to S. By virtue of the vertical structure, the asymmetric base doping
concentration is easily controlled by the ion implantation process (3-step chain implantation).
Fig. 3 Process flow for the open-base BJT (high
speed and endurable volatile memory) and the
vertical GAA FET (control device) based on
standard CMOS process technology. The sequence
of device fabrication is shown in numerical order.
10
S
Biristor
GAA
n+
S
500 nm (c)
D
Bulk silicon substrate
BJT
n
Fig. 2 Schematic of the vertically integrated 4F2 memory cell array for the
biristor. By virtue of the vertical cell structure, an FB that serves as
volatile memory is formed on a bulk silicon substrate. For the pair
comparison of FBC memory functions, the GAA MOSFET that also has
the FB is fabricated by the same fabrication process with the biristor.
(b)
(a)
2
n+
G
Control device
(GAA MOSET)
Fresh device
D
2F
D
-8
10
State ‘0’
S
2F
VD = 0.3 V, 1 V
-6
10
Depth (μm)
(b)
Gate
State ‘1’
Cumulative percent (%)
(a)
X
Unidirectional
Fig. 9 (a) Conventional two-terminal cross-bar array. Although the target
cell is an off-state (dark color), unwanted leakage current through
neighboring on-state cells (light color) can occur due to the bidirectional
current path. (b) The asymmetrically doped device and its array. The
sneak path in cross-bar array is blocked by the unidirectional current path.
31.7.3
IEDM12-751
0.6
0.4
0.7
0.3
0.6 0.7 0.8 0.9
Scaling factor
(a)
Fig. 11 Concept of lateral bandgap
engineering. VLU decreases as Ge
composition in the channel
increases, because β increases as
the valence band offset increases.
(b)
VFWD_Read = 5 V
6.0
0.2
6.5
7.0
VWrite '1' (V)
0.0
7.5
Forward
4.6
5.1
5.6
6.1
VRead (V)
GAA
Biristor
(b)
Biristor
Black (biristor)
Red (GAA FET)
Positive feedback
Write ‘1’
Read
‘0’
VD (BL)
Read
6.5 V
VD (BL)
D
-3
-2
-1
0
10 10 10 10
Read time (sec)
1
5 ns
5 ns
5V
1V
VG (WL)
-0.5 V
Biristor/GAA
VG (V)
VD (V)
VS (V)
Write ‘1’
-/1
6.5 / 5
0/0
Write ‘0’
- / -0.5
-1 / -1
0/0
Read
- / -0.5
5/5
0/0
Hold
- / -1
0/0
0/0
0.4
0.2
0.0
0.2
VG = 0 V
0.0
0.6
0.4
1
2
3 4 5
Voltage (V)
Biristor (BJT)
(Line) After cycling
6
7
0
0.4
0.2
0.2
0.0
0.0
0
1
2
3 4 5
Voltage (V)
6
7
(c)0.5
Write '1'
Dpillar = 22 nm
LB = 150 nm
VRead = 5 V
VHold = 0 V
0.2
Write '0'
0.6
Read '0' X 10
0.0
0.5
1.0
1.5
Time (sec)
2.0
VRead = 5.3 V
Biristor (BJT)
0.3
VRead = 5 V
Read '1'
ΔI = 0.42 mA
0.2
ΔI = 0.2 mA
0.1
Read '0'
0.0
0.0
0.5
1
2
S
1.0
1.5
Time (msec)
1
2
Biristor
6
7
10
3 4 5
Voltage (V)
4
6
Oxide
Gate (G)
7
2
4
7
0
(MV/cm)
10
13
10 10 10 10
P/R/E/R cycles (#)
16
10
Biristor (BJT)
0.3 Circle: Fresh device
10
Square: After 10 cycles
0.2
0.1 GAA (FET)
1
Fig. 19 Simulated distribution of
electric fields for both devices. The
electric field in the biristor is weak,
but that in the GAA FET is strong
because of the biased G and D.
31.7.4
1
Read '1'
0.4
D
D
VRead = 5 V
Fig. 17 Endurance comparison of
the biristor and the GAA FET. By
extrapolation, reliable operation of
the biristor is guaranteed up to 1016
cycles regardless of the applied bias.
6
Gate (G)
Oxide
Vertical FET
0.2
0.0
VG = 0 V, VD = 5 V, VS = 0 V
S
VRead = 4.7 V
GAA (FET)
2.0
Oxide
3 4 5
Voltage (V)
0.4
Write '0'
Oxide
Fig. 18 Aging characteristics after 1011 cycling stress. (a) The proposed
biristor maintains a bi-stable state, and there is no notable difference
observed during the cyclic operation. (b) The GAA memory does not
show latch-up/latch-down and hysteric I-V characteristics. Therefore, the
GAA FET does not work as a memory cell due to the hot carrier stress.
IEDM12-752
-5
0.3
2
Biristor (BJT)
GAA (FET)
Write '1'
0.4
VG = 0 V
0
10
Fig. 15 (a) Read retention characteristics. A binary memory state is
continually read out over 10 seconds due to the autonomous operation. (b)
Multiple read operations after 1012 W1/R/W0/R cycles. With the
introduction of the refresh process for reading a memory cell, the binary
memory state of the vertical biristor is repeatedly read out without failure.
GAA (FET)
11
After 10 cycles
0.6
I (mA)
0
I (mA)
0.4
GAA (FET)
Fresh device
I (mA)
I (mA)
(b)0.6
-6
tHold = 0.1 sec
10
Fig. 16 (a) Measurement set-up for the biristor and the GAA MOSFET. (b) Pulse waveforms and operational bias
conditions to evaluate the memory characteristics of both devices. The biristor only uses one pulse at the drain,
but the GAA MOSFET demands two pulses at the gate and the drain. (c) ΔI of 0.42 mA and 0.2 mA are extracted
after the write ‘1’ and the write ‘0’ process from the biristor and the GAA MOSFET, respectively. The binary
state is steadily read out because the reading operation is non-destructive due to the positive feedback mechanism.
Biristor (BJT)
Fresh device
-7
5V
-1 V
-1 V
(a)0.6
-8
10
10
10
Write time (sec)
0.4
0.0
10
-9
0.1
Read '0'
-4
Read '0'
Fig. 13 Evaluation of write ‘1’ and
write ‘0’ operation. Regardless of
writing time, the binary state is
consistently defined. High speed
operation at nsec is thus guaranteed.
S
0.1
10
VRead = 5 V
Read '1' X 10
EV
6.6
VWrite '0' = -1 V
0.5
0.2
0.0
Fig. 14 Available bias windows (a) write ‘1’ and (b) read operation. A
wide bias range over 1 V is achieved. No VWrite ‘1’ dependence on ΔI is
observed, but ΔI increases as VRead increases. The required voltage of the
REV is much higher than that of the FWD, i.e., unwanted operation
through the REV can be prevented by selection of proper bias conditions.
(a)
Current (mA)
Reverse
EC
Forward read
VWrite '1' = 6.5 V
10
Read '1'
0.3
Read '1'
0.0
(b)
0.4
Current (mA)
0.0
ΔI (mA)
ΔI (mA)
Forward
0.2
0.1
(a)
VFWD_Write '1' = 6.5 V
0.4
0.2
Fig. 12 Typical timing diagram
with bias conditions and the high
speed memory characteristics. The
sensing current window (ΔI) is
nearly 0.42 mA with a hold interval.
Reverse
0.4
0.3
Forward
Reverse
0.6
0.5
Read '1'
0.4
0.3
ΔI = 0.42 mA
0.2
Write '0' Read '0'
0.1 Hold Hold Hold Hold Hold
0.0
0.0
0.1
0.2
0.3
0.4
Time (msec)
0.6 VREV_Write '1' = 7.4 V
VREV_Read = 6.2 V
0.6
Simulation 0.0
-1 V
Write '1'
0 10 20 30 40 50
Germanium composition, x (%)
1.0
Fig. 10 VLU versus LB and Dpillar.
Increments of M and β contribute to
lower VLU at shorter LB. However,
VLU increases as Dpillar is reduced
due to decrements of M and β.
0.1
0.5
0.8
0.5
0.2
0.7
0.4
0V
ΔI (V)
0.9
0.8
Vpulse
(VP)
Current (mA)
Dpillar /Dpillar_Ref
FWD: VD = VP, VS = 0 V, REV: VD = 0 V, VS = VP
6.5 V
5V
0.3
Current (mA)
1.0
0.9
VLU_Ref at x = 0 %
Current (mA)
Scaling factor
LB /LB_Ref
Si1-xGex
Current (mA)
1.1
VLU /VLU_Ref (V/V)
VLU /VLU_Ref (V/V)
1.2
1.0
Valence band offset (eV)
Simulation
1.3
Read '0'
0.0
-4
10
-3
-2
-1
10
10
10
Hold time (sec)
0
10
Fig. 20 Hold retention with
consideration of memory cycling.
After cycling, hold retention of the
biristor is maintained, but the GAA
memory is significantly degraded.