0.5 Ω CMOS, 1.8 V to 5.5 V,
Dual SPDT/2:1 Mux, Mini LFCSP
ADG854
FEATURES
FUNCTIONAL BLOCK DIAGRAM
0.8 Ω typical on resistance
Less than 1 Ω maximum on resistance at 85°C
1.8 V to 5.5 V single supply
High current carrying capability: 300 mA continuous
Rail-to-rail switching operation
Fast-switching times: <17 ns
Typical power consumption: <0.1 μW
1.30 mm × 1.60 mm mini LFCSP
ADG854
S1A
D1
S1B
IN1
IN2
S2A
D2
07087-001
S2B
APPLICATIONS
Cellular phones
PDAs
MP3 players
Power routing
Battery-powered systems
PCMCIA cards
Modems
Audio and video signal routing
Communication systems
SWITCHES SHOWN FOR
A LOGIC 1 INPUT
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG854 is a low voltage CMOS device containing two
independently selectable single-pole, double-throw (SPDT)
switches. This device offers ultralow on resistance of <1 Ω over
the full temperature range. The ADG854 is fully specified for
5.5 V and 3.3 V supply operation.
1.
<1 Ω over full temperature range of –40°C to +85°C.
2.
Single 1.8 V to 5.5 V operation.
3.
Compatible with 1.8 V CMOS logic.
4.
High current handling capability: 300 mA continuous
current per channel.
5.
Low THD + N: 0.08% typical.
6.
1.30 mm × 1.60 mm mini LFCSP.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. The
ADG854 exhibits break-before-make switching action.
The ADG854 is available in a 1.3 mm × 1.6 mm 10-lead
mini LFCSP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADG854* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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• PCN-PDN Information
EVALUATION KITS
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• Symbols and Footprints
DOCUMENTATION
DISCUSSIONS
Data Sheet
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• ADG854: 0.5 Ω CMOS, 1.8 V to 5.5 V, Dual SPDT/2:1 Mux,
Mini LFCSP
SAMPLE AND BUY
User Guides
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• UG-401: Evaluating the ADG854, 0.5 Ω CMOS, 1.8 V to 5.5
V, Dual SPDT/2:1 Mux in Mini LFCSP Package
REFERENCE MATERIALS
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number.
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ADG854
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Applications ....................................................................................... 1
Pin Configurations and Function Description..............................6
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ..............................................7
General Description ......................................................................... 1
Test Circuits ..................................................................................... 10
Product Highlights ........................................................................... 1
Terminology .................................................................................... 12
Revision History ............................................................................... 2
Outline Dimensions ....................................................................... 13
Specifications..................................................................................... 3
Ordering Guide .......................................................................... 13
Absolute Maximum Ratings............................................................ 5
REVISION HISTORY
6/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADG854
SPECIFICATIONS
VDD = 4.2 V to 5.5V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels, ∆RON
+25°C
0.8
0.85
0.02
−40°C to +85°C
Unit
0 to VDD
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
1
0.04
On Resistance Flatness, RFLAT (ON)
0.17
0.23
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
±10
±30
pA typ
pA typ
VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA
VDD = 5.5 V
VS = 0.6 V/4.2 V, VD = 4.2 V/0.6 V; see Figure 17
VS = VD = 0.6 V or 4.2 V; see Figure 18
μA typ
μA max
pF typ
VIN = VGND or VDD
0.05
RL = 50 Ω, CL = 35 pF
VS = 3 V/0 V; see Figure 19
RL = 50 Ω, CL = 35 pF
VS = 3 V; see Figure 19
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V; see Figure 20
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 21
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22
S1A to S2A/S1B to S2B, RL = 50 Ω, CL = 5 pF,
f = 100 kHz; see Figure 25
S1A to S1B/S2A to S2B, RL = 50 Ω, CL = 5 pF,
f = 100 kHz; see Figure 24
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 3.5 V p-p
RL = 50 Ω, CL = 5 pF; see Figure 23
RL = 50 Ω, CL = 5 pF; see Figure 23
0.002
2.5
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
30
−75
−85
−73
dB typ
0.08
−0.06
100
19.5
50
% typ
dB typ
MHz typ
pF typ
pF typ
0.002
μA typ
μA max
28
9.2
8
1.0
1
VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA
V min
V max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
Total Harmonic Distortion + Noise, THD + N
Insertion Loss
−3 dB Bandwidth
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = 4.2 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 16
2.0
0.8
17
23
6
8.5
14
tOFF
Test Conditions/Comments
Guaranteed by design, not subject to production test.
Rev. 0 | Page 3 of 16
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
ADG854
VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels, ∆RON
+25°C
1.3
1.5
0.03
−40°C to +85°C
Unit
0 to VDD
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
1.7
0.05
On Resistance Flatness, RFLAT (ON)
0.48
0.66
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tON
±10
±30
pA typ
pA typ
VDD = 2.7 V, VS = 0 V to VDD, IDS = 100 mA
VDD = 3.6 V
VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; see Figure 17
VS = VD = 0.6 V or 3.3 V; see Figure 18
μA typ
μA max
pF typ
VIN = VGND or VDD
0.05
RL = 50 Ω, CL = 35 pF
VS = 1.5 V/0 V; see Figure 19
RL = 50 Ω, CL = 35 pF
VS = 1.5 V; see Figure 19
RL = 50 Ω, CL = 35 pF
VS1 = VS2 = 1 V; see Figure 20
VS = 1.5 V, RS = 0 V, CL = 1 nF; see Figure 21
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see Figure 22
S1A to S2A/S1B to S2B; RL = 50 Ω, CL = 5 pF,
f = 100 kHz; see Figure 25
S1A to S1B/S2A to S2B; RL = 50 Ω, CL = 5 pF,
f = 100 kHz; see Figure 24
RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p
RL = 50 Ω, CL = 5 pF; see Figure 23
RL = 50 Ω, CL = 5 pF; see Figure 23
0.002
4
Break-Before-Make Time Delay, tBBM
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
23
−75
−85
−73
dB typ
0.15
−0.07
100
20
52
% typ
dB typ
MHz typ
pF typ
pF typ
0.002
μA typ
μA max
43
8
13
1.0
1
VDD = 2.7 V, VS = 0.6 V, IDS = 100 mA
V min
V max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
Total Harmonic Distortion, THD
Insertion Loss
–3 dB Bandwidth
CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
VDD = 2.7 V, VS = 0 V to VDD, IDS = 100 mA; see Figure 16
1.35
0.7
25
37
7
7.4
22
tOFF
Test Conditions/Comments
Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 16
VDD = 3.6 V
Digital inputs = 0 V or 3.6 V
ADG854
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
Analog Inputs 1
Digital Inputs1
Peak Current per Channel, S or D
Continuous Current per Channel,
S or D
Operating Temperature Range
Storage Temperature Range
Junction Temperature
10-Lead Mini LFCSP
θJA Thermal Impedance,
3-Layer Board
Reflow Soldering, Pb-Free
Peak Temperature
Time at Peak Temperature
1
Rating
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V or
10 mA, whichever occurs first
500 mA (pulsed at 1 ms,
10% duty cycle maximum)
300 mA
−40°C to +85°C
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at any one
time.
ESD CAUTION
131.6°C/W
260(+0/−5)°C
10 sec to 40 sec
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Rev. 0 | Page 5 of 16
ADG854
9 S2A
8 D2
VDD 6
7 S2B
07087-002
1 S1A
TOP VIEW
(Not to Scale)
IN1 4
S1B 3
ADG854
IN2 5
D1 2
10 GND
PIN CONFIGURATION AND FUNCTION DESCRIPTION
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 3, 7, 9
2, 8
4
5
6
10
Mnemonic
S1A, S1B, S2B, S2A
D1, D2
IN1
IN2
VDD
GND
Description
Source Terminal. This pin can be an input or output.
Drain Terminal. This pin can be an input or output.
Logic Control Input.
Logic Control Input.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Table 5. ADG854 Truth Table
Logic (IN1/IN2)
0
1
Switch A (S1A or S2A)
Off
On
Rev. 0 | Page 6 of 16
Switch B (S1B or S2B)
On
Off
ADG854
TYPICAL PERFORMANCE CHARACTERISTICS
0.9
1.2
VDD = 3.3V
TA = 25°C
0.8
TA = +85°C
1.0
ON RESISTANCE (Ω)
0.6
0.5
0.4
VDD
VDD
VDD
VDD
0.3
0.2
= 4.2V
= 4.5V
= 5.0V
= 5.5V
07087-003
0
1
TA = –40°C
0.6
0.4
0.2
0.1
0
TA = +25°C
0.8
3
2
4
5
07087-006
ON RESISTANCE (Ω)
0.7
0
6
0
0.5
1.0
VD, VS (V)
1.5
2.0
2.5
3.0
VD, VS (V)
Figure 3. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V
Figure 6. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3.3 V
1.1
1.6
VDD = 5V
TA = 25°C
1.4
0.9
LEAKAGE (nA)
1.0
0.8
0.6
VDD
VDD
VDD
VDD
0.4
= 2.7V
= 3.0V
= 3.3V
= 3.6V
07087-004
0
0.5
1.0
0.5
IS (ON) ++
IS (OFF) +–
IS (ON) – –
IS (OFF) –+
0.3
0.1
0.2
0
ID,
ID,
ID,
ID,
0.7
1.5
2.0
2.5
3.0
3.5
–0.1
10
4.0
07087-007
ON RESISTANCE (Ω)
1.2
20
30
Figure 4. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V
0.9
40
50
60
70
80
TEMPERATURE (°C)
VD, VS (V)
Figure 7. Leakage Current vs. Temperature, VDD = 5 V
0.8
VDD = 5V
VDD = 3.3V
0.7
TA = +85°C
0.6
TA = +25°C
0.6
LEAKAGE (nA)
0.5
TA = –40°C
0.4
0.3
0.2
IS (ON) ++
IS (OFF) +–
IS (ON) – –
IS (OFF) –+
0.2
0
07087-005
0.1
0
ID,
ID,
ID,
ID,
0.4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
–0.2
5.0
07087-008
ON RESISTANCE (Ω)
0.8
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
VD, VS (V)
Figure 5. On Resistance vs. VD (VS) for Different Temperatures, VDD = 5 V
Rev. 0 | Page 7 of 16
Figure 8. Leakage Current vs. Temperature, VDD = 3.3 V
ADG854
70
0
VDD = 5V
–10
TA = 25°C
VDD = 5V, 3.3V
–20
50
ATTENUATION (dB)
40
30
VDD = 3V
20
VDD = 2.5V
07087-009
0
1
2
3
–40
–50
–60
–70
10
0
–30
4
5
–80
–90
0.1
6
1
SOURCE VOLTAGE (V)
10
FREQUENCY (MHz)
100
07087-012
CHARGE INJECTION (pC)
60
1k
Figure 12. Off Isolation vs. Frequency
Figure 9. Charge Injection vs. Source Voltage
35
0
–10
30
TA = 25°C
VDD = 5V, 3.3V
S1A to S1B
–20
tON (3.3V)
CROSSTALK (dB)
TIME (ns)
25
20
tON (5V)
15
tOFF (5V)
10
–30
S1A to S2A
–40
–50
–60
–70
–80
tOFF (3.3V)
–40
–20
0
20
40
60
80
–90
–100
0.1
100
TEMPERATURE (°C)
Figure 10. tON/tOFF Times vs. Temperature
1
10
FREQUENCY (MHz)
100
1k
07087-013
0
–60
07087-010
5
Figure 13. Crosstalk vs. Frequency
0
0.25
–2
VDD = 2.7V
THD + N (%)
–6
–8
–10
–12
TA = 25°C
VDD = 5V, 3.3V
0.15
VDD = 3.6V
VDD = 4.2V
0.10
VDD = 5.5V
0.05
–16
0.1
1
10
FREQUENCY (MHz)
100
1k
0
100
Figure 11. Bandwidth
1k
10k
FREQUENCY (Hz)
100k
07087-014
–14
07087-011
INSERTION LOSS (dB)
0.20
–4
Figure 14. Total Harmonic Distortion + Noise (THD+N) vs. Frequency
Rev. 0 | Page 8 of 16
ADG854
0
–20
TA = 25°C
VDD = 5V, 3.3V
–60
–80
–100
–120
–140
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1G
07087-015
PSRR (dB)
–40
Figure 15. PSRR vs. Frequency
Rev. 0 | Page 9 of 16
ADG854
TEST CIRCUITS
S
A
IDS
D
ID (OFF)
A
VS
VD
V1
07087-020
IS (OFF)
Figure 17. Off Leakage
RON = V1/IDS
S
NC
ID (ON)
D
A
VD
Figure 18. On Leakage
Figure 16. On Resistance
VDD
0.1µF
VDD
VS
VOUT
D
RL
50Ω
IN
50%
VIN
50%
CL
35pF
90%
VOUT
90%
GND
tON
tOFF
07087-022
S1B
S1A
Figure 19. Switching Times, tON, tOFF
0.1µF
VDD
VDD
VIN
S1B
S1A
VOUT
VOUT
D
RL
IN
CL
35pF
50Ω
80%
50%
80%
tBBM
tBBM
07087-023
GND
Figure 20. Break-Before-Make Time Delay, tBBM
VDD
SW ON
D
VS
SW OFF
VIN
S1B
NC
S1A
VOUT
1nF
IN
VOUT
ΔVOUT
GND
QINJ = CL × ΔVOUT
Figure 21. Charge Injection
Rev. 0 | Page 10 of 16
07087-024
VS
50%
0V
07087-021
VS
D
07087-019
S
ADG854
VDD
VDD
0.1µF
0.1µF
NETWORK
ANALYZER
S1B
S1A
VS
D
GND
VOUT
VS
D
S1B
RL
50Ω
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT
VS
Figure 24. Channel-to-Channel Crosstalk (S1A to S1B/S2A to S2B)
VDD
NETWORK
ANALYZER
NETWORK
ANALYZER
VOUT
50Ω
S1A
50Ω
VS
GND
VOUT
50Ω
VS
INSERTION LOSS = 20 log
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
D2
NC
S2B
D
RL
50Ω
S2A
S1A
D1
S1B
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
NC
50Ω
VOUT
VS
Figure 25. Channel-to-Channel Crosstalk (S1A to S2A, S1B to S2B)
Figure 23. Bandwidth
Rev. 0 | Page 11 of 16
07087-028
VDD
S1B
RL
50Ω
VS
Figure 22. Off Isolation
0.1µF
VDD
S1A
50Ω
VOUT
07087-025
RL
50Ω
OFF ISOLATION = 20 log
VOUT
50Ω
50Ω
07087-026
NC
NETWORK
ANALYZER
07087-027
VDD
ADG854
TERMINOLOGY
CD, CS (On)
On switch capacitance. Measured with reference to ground.
IDD
Positive supply current.
CIN
Digital input capacitance.
VD (VS)
Analog voltage on Terminal D and Terminal S.
RON
Ohmic resistance between Terminal D and Terminal S.
tON
Delay time between the 50% and 90% points of the digital input
and switch on condition.
RFLAT (ON)
The difference between the maximum and minimum values of
on resistance as measured on the switch.
tOFF
Delay time between the 50% and 90% points of the digital input
and switch off condition.
ΔRON
On resistance match between any two channels.
tBBM
On or off time measured between the 80% points of both
switches when switching from one to another.
IS (Off)
Source leakage current with the switch off.
ID (Off)
Drain leakage current with the switch off.
Charge Injection
Measure of the glitch impulse transferred from the digital input
to the analog output during on/off switching.
ID, IS (On)
Channel leakage current with the switch on.
Off Isolation
Measure of unwanted signal coupling through an off switch.
VINL
Maximum input voltage for Logic 0.
Crosstalk
Measure of unwanted signal that is coupled from one channel to
another because of parasitic capacitance.
VINH
Minimum input voltage for Logic 1.
−3 dB Bandwidth
Frequency at which the output is attenuated by 3 dB.
IINL (IINH)
Input current of the digital input.
CS (Off)
Off switch source capacitance. Measured with reference to ground.
CD (Off)
Off switch drain capacitance. Measured with reference to ground.
On Response
Frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
Ratio of the harmonics amplitude plus noise of a signal to the
fundamental.
Rev. 0 | Page 12 of 16
ADG854
OUTLINE DIMENSIONS
0.20 DIA
TYP
0.55
0.40
0.30
1.30
1
1.60
0.40
BSC
6
4
0.35
0.30
0.25
BOTTOM VIEW
TOP VIEW
0.60
0.55
0.50
PIN 1
IDENTIFIER
9
0.05 MAX
0.02 NOM
033007-A
0.20 BSC
SEATING
PLANE
Figure 26. 10-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
1.30 × 1.60 mm Body, Ultrathin Quad
(CP-10-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG854BCPZ-REEL 1
ADG854BCPZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
10-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
10-Lead Lead Frame Chip Scale Package [LFCSP_UQ]
Z = RoHS Compliant Part.
Rev. 0 | Page 13 of 16
Package Option
CP-10-10
CP-10-10
Branding
C
C
ADG854
NOTES
Rev. 0 | Page 14 of 16
ADG854
NOTES
Rev. 0 | Page 15 of 16
ADG854
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07087-0-6/08(0)
Rev. 0 | Page 16 of 16