ISSN: 2278 – 909X
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Volume 5, Issue 7, July 2016
A PARALLEL SELF-TIMED ADDER
(PASTA) AND SUBTRACTOR (PASTS)
USING VHDL
1
Jismy Theresa,
PG Scholar in VLSI Design,
2
Manju V.M
Assistant Professor, ECE Department,
3
Veena K
Assistant Professor, ECE Department,
IES college of Engineering, Thrissur, Kerala

Abstract: Integer addition is one of the most important
operations
in digital computer
systems
because the
performance of processors is significantly influenced by the
speed of their adders. This paper describe the design of a 16-bit
parallel self-timed adder (PASTA) &Parallel self-timed
subtractor (PASTS) using VHDL.PASTA design uses
multiplexers along with half adders. PASTS
design uses
multiplexers along with half subtractor. Subtraction was
implemented by PASTS &2’s complement addition using
PASTA. It is based on a recursive formulation for performing
multibit binary addition. The operation is parallel for those
bits that do not need any carry chain propagation. The
simulation results show the proposed model attains with less
time and with less complexity.
Index Terms- asynchronous circuits, binary adders, binary
subtractor
I. INTRODUCTION
The most important operation of processor that can
perform is binary addition. The operation is based on the
recursive formulation for performing multibit binary addition.
The binary subtraction is another arithmetic operation.
The serial adder has slower, uses shift registers, requires one
full adder circuit, Time required for addition depends on
number of bits and it is sequential circuit. But the parallel
adder is Faster, It uses registers with parallel load capacity,
No. of full adder circuit is equal to No. of bits in binary adder
and time required does not depend on the number of bits.
Here half adders are used instead of full adder .Here the
operation is parallel for those bits so that no need any carry
chain propagation.
In cellular phones, PDA and other high performance,
the clockless chip processor approach must be needed.
Clockless processors also called asynchronous or self -timed.
In self timed system, that doesn’t use the oscillating crystal
that serves as the regularly “ticking” clock [2]. So the clock
less chip will run faster than clock chip in order to avoid the
need of clock tick. Also in clockless chip, the major
advantage that have of low electromagnetic interference.
Asynchronous circuits do not assume any
quantization of time. In absence of clocks, the logic flow in
asynchronous
circuit
is
controlled
by
request –acknowledgement handshaking protocol. But
handshaking block for small elements, such as bit adders and
bit subtractions are expensive. So these managed using dual
rail carry propagation in adders and borrow propagation in
subtractor.
The system presents an asynchronous parallel self
timed subtractor (PASTS) proposed using the PASTA [1].
The algorithm of PASTA is mainly depends on cellular
automata [4]. This system also implements 2’s complement
addition for subtraction. The design of PASTA&PASTS is
regular and uses half adders and half subtractor along with
multiplexers requiring minimal inter connections
respectively.
II.LITERATURE SURVEY
Addition is a fundamental operation for any digital
system, digital signal processing or control system. A fast and
accurate operation of a digital system is greatly influenced by
the performance of the resident adders. Adders are also very
important component in digital systems because of their
extensive use in other basic digital operations such as
subtraction, multiplication and division.
A. Ripple Carry Adder
The ripple carry adder is constructed by cascading
full adders (FA) blocks in series. One full adder is
responsible for the addition of two binary digits at any stage
of the ripple carry. The carryout of one stage is fed directly to
the carry-in of the next stage. A number of full adders may be
added to the ripple carry adder or ripple carry adders of
different sizes may be cascaded in order to accommodate
binary vector strings of larger sizes. For an n-bit parallel
adder, it requires n computational elements (FA). One of the
most serious drawbacks of this adder is that the delay
increases linearly with the bit length. As mentioned before,
each full adder has to wait for the carry out of the previous
stage to output steady-state result. Therefore even if the adder
has a value at its output terminal, it has to wait for the
propagation of the carry before the output reaches a correct
value
1982
All Rights Reserved © 2016 IJARECE
ISSN: 2278 – 909X
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Volume 5, Issue 7, July 2016
B. Carry Look-Ahead Adder
In the ripple-carry adder, its limiting factor is the
time it takes to propagate the carry. The carry look-ahead
adder [3] solves this problem by calculating the carry signals
in advance, based on the input signals. The result is a reduced
carry propagation time. The Propagate P and generate G in a
full-adder, is given as:
Pi =
Carry propagate
Carry generate
Both propagate and generate signals depend only on the input
bits and thus will be valid after one gate delay. The new
expressions for the output sum and the carryout are given by:
These equations show that a carry signal will be generated in
two cases:
1) If both bits and are 1
2) If either
or
is 1 and the carry-in
is 1.
Where
The primary inputs, Ai and Bi, are single rail. The carry
bits are encoded by using two separate signals (dual-rail
signaling):
means that no carry emerges from the
ith one-bit adder and means
that a carry emerges
from the ith one-bit adder. The completion or acknowledge
signal (
) for each stage is turned on by the arrival of
either
.This is most economically detected by an
OR-gate. If desired, an AND-gate can be added to flag the
error condition
. Once all the stages have
computed their carries, the addition is completed. An n-input
AND gate may be used to signal the completion
(i.e,
. The enable signal is used to start
the computation and to ensure that no false completion signal
will be generated. When enable = 0, all
(i = 1…n)
signals are set to zero. The completion signal, finish, must be
zero, too. Thus, no false completion can be asserted. After all
the input data have arrived at the input ports of the CCSA, the
enable signal is turned on to start the addition operation.
Upon the completion of the addition, the finish signal is
turned on.
Let's apply these equations for a 4-bit adder:
III.DESIGN OF PASTA&PASTS
Adders have a special significance in VLSI designs
and it is used in computer and many other processors to
perform the arithmetic functions. The adder first accepts two
input operands to perform half additions for each bit.
Subsequently, it iterates using earlier generated carry and
sum to perform half additions repeatedly until all carry bits
are consumed and settled at zero level [1].
A .ARCHITECTURE OF PASTA
These expressions show that
and
its previous carry-in. Therefore
does not need to wait for
to propagate. As soon as
do not depend on
is computed
steady state. The same is also true for
and
The system mainly includes mux, half adder, and
completion detection unit as shown in fig2. The system deals
VHDL implementation of two 16-bit number additions using
existing technique PASTA [1]. Here completion detection
unit directly checking all carry bits is zero or not. If all carry
bits are zero the output can be displayed.
can reach
.The general
expression is
C Asynchronous Adders
C.1 Carry-Completion Sensing Adders
A Carry-Completion Sensing Adder (CCSA) [3] may be
regarded as an asynchronous version of an RCA. Instead of
using clock pulses to synchronize adder operation, a CCSA
uses some extra circuitry to implement the start and
completion signals.. The CCSA scheme computes the
in
the following way:
Fig 1: state diagram [1] (a) initial phase
(b) iterative phase
1983
All Rights Reserved © 2016 IJARECE
ISSN: 2278 – 909X
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Volume 5, Issue 7, July 2016
D. Architecture of PASTS
In PASTS half subtractor module and directly
subtracting two inputs. The general architecture of PASTS is
shown in fig3.The selection input for two input multiplexers
corresponds to the Req handshake signal and will be a single
0 to 1 transition denoted by Sel. It will initially select the
actual operands during Sel=0and will switch to
feedback/borrow paths for subsequent iterations using Sel=1.
The feedback path from the HSs enable the multiple
iterations to continue until the completion when all carry
signals will assume zero values.
Fig 2: block diagram of 16-bit PASTA
The selection input for two input multiplexers
corresponds to the Req-handshake signal and will be a single
0 to 1 transition denoted by Sel. It will initially select the
actual operands during Sel=0and will switch to
feedback/carry paths for subsequent iterations using Sel=1.
The feedback path from the HAs enable the multiple
iterations to continue until the completion when all carry
signals will assume zero values. The main working principle
related with quantum cellur automata[4]
Fig 3:block diagram of 16-bit PASTS
B. State Diagram
Two state diagrams are drawn for the initial phase
and the iterative phase of the PASTA architecture as in fig 1.
Each state is represented by (
pair where
represent carry out and sum values, respectively, from the
bit adder block. During the initial phase, the circuit merely
works as a combinational HA operating in fundamental mode.
It is apparent that due to the use of HAs instead of FAs, state
(11) cannot appear.
During the iterative phase (Sel=1), the feedback
path through multiplexer block is activated. The carry
transitions ( ) are allowed as many times as needed to
complete the recursion. From the definition of fundamental
mode circuits, the present design cannot be considered as a
fundamental mode circuit as the input–outputs will go
through several transitions before producing the final output.
It is not a Muller circuit working outside the fundamental
mode either as internally; several transitions will take place,
as shown in the state diagram. This is analogous to cyclic
sequential circuits where gate delays are utilized to separate
individual states.
C. Recursive Formula for Binary Addition
Let
denote the sum and carry, respectively,
for
bit at the
iteration. The initial condition (j=0) for
addition is formulated as follows
The
iteration for the recursive addition is formulated by
;
0
;
0
The recursion is terminated at
iteration when the
following condition is met:
E. State Diagram of PASTS
Two state diagrams are drawn for the initial phase
and the iterative phase of the PASTS architecture. Each state
is represented by (
pair where
represent
borrow out and difference values, respectively, from the
bit subtractor block. During the initial phase, the circuit
merely works as a combinational HS operating in
fundamental mode. It is apparent that due to the use of HSs
instead of FSs, state (10) cannot appear.
(a)
(b)
Fig 4: state diagram (a) initial phase
(b) Iterative phase
For (a) notation State
For (b) notation State
) Transition
) Transition
During the iterative phase (Sel=1), the feedback
path through multiplexer block is activated. The borrow
transitions ( ) are allowed as many times as needed to
complete the recursion. From the definition of fundamental
mode circuits, the present design cannot be considered as a
fundamental mode circuit as the input–outputs will go
through several transitions before producing the final output.
It is not a Muller circuit working outside the fundamental
mode either as internally; several transitions will take place,
as shown in the state diagram. This is analogous to cyclic
sequential circuits where gate delays are utilized to separate
individual states.
1984
All Rights Reserved © 2016 IJARECE
ISSN: 2278 – 909X
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Volume 5, Issue 7, July 2016
F. Recursive Formula for Binary Subtraction
Let
denote the sum and carry, respectively,
for
bit at the jth iteration. The initial condition (j=0) for
addition is formulated as follows
The
by
iteration for the recursive subtraction is formulated
;
0
;
0
The recursion is terminated at
following condition is met:
iteration when the
G.Subtraction Using PASTA
Subtraction of two 16 bit numbers using 2’s
complement addition technique using PASTA and also
changing half adder module. In this system one of the inputs
will be complemented. Adding one with the given output by
using method PASTA. A t last the another input and output
get from the just earliest stage again added using PASTA.
synthesis program, only if it is part of the logic design. A
simulation program is used to test the logic design using
simulation models to represent the logic circuits that interface
to the design. This collection of simulation models is
commonly called a test bench. VHDL is strongly typed and is
not case sensitive. When a VHDL model is translated into the
"gates and wires" that are mapped onto a programmable logic
device such as a CPLD or FPGA, then it is the actual
hardware being configured, rather than the VHDL code being
"executed" as if on some form of a processor chip.
The key advantage of VHDL, when used for
systems design, is that it allows the behavior of the required
system to be described (modeled) and verified (simulated)
before synthesis tools translate the design into real hardware
(gates and wires).Another benefit is that VHDL allows the
description of a concurrent system. VHDL is a dataflow
language, unlike procedural computing languages such as
BASIC, C, and assembly code, which all run sequentially,
one instruction at a time.
A VHDL project is multipurpose. Being created
once, a calculation block can be used in many other projects.
However, many formational and functional block parameters
can be tuned (capacity parameters, memory size, element
base, block composition and interconnection structure).A
VHDL project is portable. Being created for one element
base, a computing device project can be ported on another
element base, for example VLSI with various technologies.
Fig 5: Flow graph of binary subtraction of 2 input using
PASTA
IV. EXPERIMENT RESULT AND DISCUSSION
Fig 6: Addition and subtraction of two 16 bit number
The system is implemented using Xilinx ISE Design
Suite 14.2.using VHDL language. The Xilinx® ISE
Simulator (ISim) is a Hardware Description Language (HDL)
simulator that enables you to perform functional and timing
simulations for VHDL, Verilog and mixed language designs.
The ISE design suit 14.2 supports the devices like Kintex-7
325T, Kintex-7 410T, Virtex®-7 X485T.Performance
increase of ~3.5% for the -2 speed grades for Kintex-7 and
Virtex-7 FPGAs.
VHDL Language
VHDL (VHSIC Hardware Description Language) is
a hardware description language used in electronic design
automation to describe digital and mixed-signal systems such
as field-programmable gate arrays and integrated circuits.
VHDL can also be used as a general purpose parallel
programming language.
VHDL is commonly used to write text models that
describe a logic circuit. Such a model is processed by a
Fig 7: RTL schematic of two 16 –bit number addition and
subtraction
1985
All Rights Reserved © 2016 IJARECE
ISSN: 2278 – 909X
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Volume 5, Issue 7, July 2016
Fig 8: Two 8-bit number addition and subtraction using 2’s
complement addition and PASTS
“Self-Timed
Carry-Lookahead
Adders”IEEE
TRANSACTIONS ON COMPUTERS, VOL. 49,
NO. 7, JULY 2000
[4]Pabitra Pal Choudhury, Sudhakar Sahoo, Mithun
Chakraborty, “Implementation of Basic Arithmetic
Operations Using Cellular Automaton” in
proc.ICIT,2008.pp.79-80
[5]C. Cornelius, S. Koppe, and D. Timmermann,
“Dynamic circuit techniques in deep submicron
technologies: Domino logic reconsidered,” in Proc.
IEEE ICICDT
, Feb. 2006, pp. 1–4
[6]M. Anis, S. Member, M. Allam, and M. Elmasry,
“Impact of technology scaling on CMOS logic
styles,” IEEE Trans. Circuits Syst., Analog Digital
Signal Process. , vol. 49, no. 8, pp. 577–588, Aug.
2002.
AUTHORS
Jismy Theresa, currently pursing PG
in VLSI Design from IES college of
Engineering,Thrissur,Kerala,India.She
received her B.Tech in Electronics and
Communication from Vidya Academy
of Science &Technology, Thrissur, Kerala, India in
2015.
Fig 9: RTL schematic of 8 bit numbers operation
V.
CONCLUSION
In this paper the
VHDL implementation of a
parallel self-timed adder (PASTA) and PASTS (parallel
self-timed subtraction) was implemented .It is an efficient
method for processors. Initially, the theoretical foundation
for a single-rail wave-pipelined adder is established. The
design achieves a very simple n-bit adder and n-bit subtractor
Moreover, the circuits works in a parallel manner for
independent carry chains, as well as borrow chains and thus
achieves logarithmic average time performance over random
input values. . The system is self- timed because of clockless
operation the system will work in fast and with less
complexity. Simulation results are used to verify the
advantages of the proposed approach
ACKNOWLEDGEMENT
I express my sincere thanks to my guides Ms.Manju
V.M and Ms.Veena K. for their valuable guidance and useful
suggestions, which helped me in the project work.
Mrs. Manju V M, currently working
as an Assistant Professor/PG
coordinator in Department of
Electronics and Communication
Engineering at IES College of
Engineering, Thrissur, Kerala, India.
She received the B.E degree in Electronics and
Communication from Anna University Chennai, in
2006 and M.E degree in VLSI Design from Anna
University, Trichi in 2009. Her interested research
areas are low power VLSI design and digital system
design
Mrs. Veena K is currently working
as Assistant Professor of electronics
and engineering with the IES college
of Engineering Thrissur, Kerala for
last 5 years. She is specialized in
VLSI Design. She is also member of
The Indian Society for Technical Education New
Delhi. She has presented and reviewed a number of
research paper in national and international
conferences
REFERENCES
[1]Mohammed Ziaur Rahman,Lindsay Kleeman and
Mohammad Ashfack“Recursive Approach to the
Design of a Parallel self -timed Adder” IEEE
transactions on Very large scale integration (VLSI )
systems ,vol.23.no.1.january 2015
[2]D .Geer “Is It Time for Clockless Chips?”IEEE
comput, vol.38.n0.3,pp,18-19,mar 2005.
[3]Fu-Chiung Cheng, Stephen H. Unger, Fellow, IEEE,
and Michael Theobald, Student Member, IEEE
1986
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