Hardware Reference Manual
Confidentiality Notice
Copyright (c) 2016 eInfochips. - All rights reserved
This document is authored by eInfochips and is eInfochips intellectual property, including the copyrights
in all countries in the world. This file may not be distributed, copied, or reproduced in any manner,
electronic or otherwise, without the express written consent of eInfochips. eInfochips reserves the right
to change details in this publication without notice. Product and company names herein may be the
trademarks of their respective owners.
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Contents
1
2
3
Document Details.................................................................................................................................. 5
1.1
Document History ......................................................................................................................... 5
1.2
Definition, Acronyms and Abbreviations ...................................................................................... 5
1.3
References .................................................................................................................................... 8
Preface .................................................................................................................................................. 9
2.1
Intended Audience ........................................................................................................................ 9
2.2
Intended Use ................................................................................................................................. 9
Overview ............................................................................................................................................. 10
3.1
4
Key Features................................................................................................................................ 11
System Block Diagram ......................................................................................................................... 12
4.1
Q820 SOM IMAGE ....................................................................................................................... 14
4.2
SoM’s I/F exported to B2B connector. ........................................................................................ 23
4.2.1
MIPI CSI2 Interface.............................................................................................................. 23
4.2.2
MIPI DSI Interface ............................................................................................................... 24
4.2.3
Digital Audio I2S Interface................................................................................................... 26
4.2.4
PCM Interface ................................................................................................................... 26
4.2.5
USB Interface ...................................................................................................................... 27
4.2.6
JTAG Interface ..................................................................................................................... 27
4.2.7
uSD Card Interface .............................................................................................................. 28
4.2.8
BLSP Interface ..................................................................................................................... 28
4.2.9
PCIe Interface ...................................................................................................................... 29
4.2.10
SSC Interface ..................................................................................................................... 29
4.2.11
PMIC GPIOs ......................................................................................................................... 30
4.2.12
Wi-Fi + BT Interface ............................................................................................................. 30
4.2.13
GPS Interface ..................................................................................................................... 30
4.2.14
Boot Configuration .............................................................................................................. 30
4.2.15
Systems LEDs ....................................................................................................................... 31
4.2.16
Power .................................................................................................................................. 31
4.3
Electrical Specifications............................................................................................................... 34
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4.3.1
Absolute Maximum Ratings ................................................................................................ 34
4.3.2
Operating Conditions .......................................................................................................... 34
4.4
5
Mechanical Specification ............................................................................................................ 35
About eInfochips ................................................................................................................................. 36
List of Figures
Figure 1 : Q820 SOM Block Diagram ........................................................................................................... 12
Figure 2 : Q820 Carrier Block Diagram ........................................................................................................ 13
Figure 3 : Top View of Q820 SOM ............................................................................................................... 14
Figure 4 : Bottom View of Q820 SOM ......................................................................................................... 14
List of Tables
Table 1: Document History ........................................................................................................................... 5
Table 2 : Definition, Acronyms and Abbreviations ....................................................................................... 7
Table 3 : References ...................................................................................................................................... 8
Table 4 : Q820 SOM Connectors Pin outs ................................................................................................... 22
Table 5 : MIPI CSI0 Pin outs ........................................................................................................................ 23
Table 6 : MIPI CSI1 Pin outs ........................................................................................................................ 23
Table 7 : MIPI CSI2 Pin outs ........................................................................................................................ 24
Table 8 : Dedicated I2C Signals ................................................................................................................... 24
Table 9 : MIPI DSI0 Pin outs ........................................................................................................................ 25
Table 10 : MIPI DSI1 Pin outs ...................................................................................................................... 25
Table 11 : HDMI Pin outs ............................................................................................................................ 25
Table 12 : I2S Interface Pin outs ................................................................................................................. 26
Table 13 : PCM Interface Pin outs ............................................................................................................... 26
Table 14 : USB 2.0 Interface Pin outs .......................................................................................................... 27
Table 15 : USB 3.0 Interface Pin outs .......................................................................................................... 27
Table 16 : JTAG Interface Pin outs .............................................................................................................. 27
Table 17 : SD Card Interface Pin outs.......................................................................................................... 28
Table 18 : BLSP Interface Pin outs............................................................................................................... 28
Table 19 : PCIe Interface Pin outs ............................................................................................................... 29
Table 20 : SSC Interface Pin outs................................................................................................................. 30
Table 21 : PMIC GPIOs................................................................................................................................. 30
Table 22 : Boot Configurations ................................................................................................................... 31
Table 23 : Power Pins .................................................................................................................................. 33
Table 24 : Absolute Maximum Ratings ....................................................................................................... 34
Table 25 : Operating Conditions ................................................................................................................. 34
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1 Document Details
1.1 Document History
Author
Name
0.1
eInfochips
Reviewer
Date
Review
Date
Name
Approver
Name
22-March-16
Date
Description
Of Changes
Initial release
Table 1: Document History
1.2 Definition, Acronyms and Abbreviations
Definition/Acronym/Abbreviation
Description
SOM
System On Module
BLE
Bluetooth Low Energy
BOM
Bill of Material
Bpp
Bits Per Pixel
BT
Bluetooth
CPU
Central Processing Unit
CSI
Camera Serial Interface
DC
Direct Current
DDR
Double Data Rate
DMIPS
Dhrystone MIPS
DSI
Display Serial Interface
eI
eInfochips
GB
Giga Byte
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GPIO
General Purpose Interface
GPS
Global Positioning System
HD
High Definition
HDMI
High Definition Multimedia Interface
HSIC
High-speed Serial Interface Connect
I/O
Input Output
I2C
Inter-Integrated Circuit
IC
Integrated Circuit
Inc.
Incorporated
JTAG
Joint Test Application Group
KB
Kilo Byte
LAN
Local Area Network
LNA
Low Noise Amplifier
LPDDR
Lower Power DDR
MB
Mega Byte
Mbps
Mega Bits Per Second
MIPI
Mobile protocol working Alliance (not an Acronym)
MIPS
Million Instruction Per Second
MISO
Master In Slave Out
Mm
Millimeter
MMC
Multi Media Card
MOSI
Master Out Slave In
MP
Mega Pixel
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MPP
Multipurpose Pins
OTG
On The Go
PCIe
Peripheral Component Interface – Express
PLL
Phase Loop Locked
PMIC
Power Management IC
RAM
Random Access Memory
RF
Radio Frequency
RH
Relative Humidity
RoHS
Restriction of Hazardous Substances
Rx
Receive
SATA
Serial
SATA
Serial Advance Technology Attachment
SiP
System In Package
SMPS
Switched Mode Power Supply
SOM
System On Module
SPI
Serial peripheral Interface
Tx
Transmit
UART
Universal Asynchronous Interface
USB
Universal Serial Bus
VCO
Voltage Controlled Oscillator
WLAN
Wireless LAN
Table 2 : Definition, Acronyms and Abbreviations
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1.3 References
No.
Document
Version
1
Q820_SOM Schematic File
1.0
2
Q820_SOM Layout File
1.0
Remarks
Table 3 : References
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2 Preface
This document provides an overview of the Q820 SOM
Design based on Qualcomm’s APQ8096 SoC. It provides detailed information about the hardware
components and associated software Android 6.0 (Marshmallow).
2.1 Intended Audience
This document is intended for technically qualified personnel. It is not intended for general audiences.
2.2 Intended Use
The development platform supports a wide range of industry interfaces and offers a comprehensive
hardware and software design. It comes with Android 6 software packages and sample demo applications
for easy adaption.
This platform enables developers to evaluate and create solutions targeted at various market segments
while customers and OEMs can build their products based on these designs directly or with
customizations.
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3
Overview
Q820 is high performance System on Module. The Q820 SOM provides an ideal building block for simple
integration with a wide range of products in target markets requiring rich multimedia functionality,
powerful graphics processing and video capabilities, as well as high-processing power, in a compact, RoHS
compliant, cost effective SOM with low power consumption.
The Q820 SOM leverages one of the most cutting edge mobile processor by Qualcomm for embedded and
industrial product designs. Qualcomm Snapdragon™ 820 (APQ8096) quad core Kryo™ CPU two of them
run at a maximum of 2.2 GHz while two other run at a maximum of 1.6GHz, the Hexagon 680 DSP, the
Spectra image processor, the Adreno 530 GPU.
The SOM is equipped with full range of interfaces available in the Qualcomm Snapdragon APQ8096 SoC,
which are routed to the carrier board through total 300 pins of three (100 pins each) Board to Board
connector.
Supported Products:





Carrier board compatible to SOM
Camera Module OV5640 5MP, S5K3M2XX 13MP, IMX230 21MP
Display Module
HDMI Input add on board
DMIC (Digital Mic) board which supports three Mic on it.
Supported operating systems:


Android 6.0 (Marshmallow)
Linux BSP (TBD)
The Development kit consist of eInfochips’ Q820 System on Module (SOM), a carrier board exposing all
the available IO and a range of accessories to fast track your product development and is ideal for rapid
prototyping of end product. With the variety of peripherals, this kit is targeted for wide range of
applications like next generation embedded and IoT devices, faster connectivity, higher through put and
performance at lower power.
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3.1 Key Features
CPU





Qualcomm Snapdragon 820 (14 nm
FinFET Process)
Qualcomm Quad Core Kryo™ CPU
o Two high-performance Kryo
cores Up to 2.2 GHz
o Two low power Kryo cores up to
1.6 GHz
Qualcomm Adreno 530 graphics
processing unit (GPU)
Qualcomm Hexagon 680 DSP
Qualcomm Spectra ISP
Memory
 RAM:
4 GB LPDDR4 up to 1866 MHz clock rate
 Storage:
32 GB UFS2.0 Flash 1-lane, Gear 3 Or
16 GB eMMC5.1
Camera
 3 x 4 lane MIPI CSI (4+4+4 or 4+4+2+1)
DPHY1.2 at 2 Gbps per lane speed
 Dual ISP up to 28MP
 Camera Module based on OV5640 5MP,
CONNECTIVITY
 WLAN 802.11a/b/g/n/ac 2.4/5.0 GHz 2x2
MIMO support
 Bluetooth 4.1
 Qualcomm IZat Gen 8C GPS
 Gigabit Ethernet RJ45 connector
 PCIe Gen2 1x Female Slot
 uSD Socket for external storage
 Debug UART on 3 pin header
 JTAG connector
 2x 24 pin header for
o I2C, UART, SPI, PCM, PM_GPIO
o SSC I2C, SSC UART, SSC SPI, 2xI2S
Display
 2 X MIPI DSI 4 Lane, 60fps, up to
2560x1600 (Single port), 4096x2160
(Dual Port)
 1x HDMI 2.0 (4k@60fps or 4k30
Miracast) Output type A connector
USB


2 X USB 2.0 Host, Type A
1x USB 3.0 OTG Micro AB
S5K3M2XX 13MP, IMX230 21MP supported
Audio
 Carrier card has Audio codec WCD9335
along with two Audio Amplifiers
WSA8810
 3.5mm ANC Audio Jack
 2x 16 pin Audio header which supports.
Input:
o 3xAnalog Mic
o 3xDigital Mic
Output:
o 2x Stereo Amplified Output
o 2x External Headphone Output
o 1x Earphone Output
Version 1.0
Physical & Operating Characteristics
 Dimension:
o SOM: 53mm x 25mm
o Carrier: 110mm x 85mm
 Storage Temperature Range:
o -20 to 85 C
 Operating Temperature Range:
o 0 to 60 C
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Operating System
 Android 6.0 (Marshmallow)
 Linux BSP (TBD)
4
Power Input
 12V @ 5A through DC Jack
 Battery Connector
System Block Diagram
Figure 1 : Q820 SOM Block Diagram
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Figure 2 : Q820 Carrier Block Diagram
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4.1
Q820 SOM IMAGE
Figure 3 : Top View of Q820 SOM
Figure 4 : Bottom View of Q820 SOM
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The Q820 SOM has three Hirose DF40C-100DP-0.4V (51) Connectors. The pin outs for these three
connectors is described below.
Pin No.
Net Name
Default Pin Function
J4.1
J4.2
J4.3
J4.4
J4.5
J4.6
J4.7
J4.8
J4.9
J4.10
J4.11
J4.12
J4.13
J4.14
J4.15
J4.16
J4.17
J4.18
J4.19
J4.20
J4.21
J4.22
J4.23
J4.24
J4.25
J4.26
J4.27
J4.28
J4.29
J4.30
J4.31
J4.32
J4.33
J4.34
J4.35
J4.36
J4.37
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
USB_VBUS
VBATT+
USB_VBUS
USB2_VBUS_DET
USB_VBUS
SPKR_AMP_EN1
USB_VBUS
SPKR_AMP_EN2
GND
VSENSE_BATT_P
LED0_RED_DRV
VSENSE_BATT_M
LED0_GREEN_DRV
WLED_VREG
LED0_BLUE_DRV
WLED_SINK1
LED1_GREEN_DRV
WLED_SINK2
PCIE1_RST_N
BACKLIGHT_CNTL
PCIE1_WAKE_N
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
Main battery Input supply (3.8V)
USB_VBUS Input supply
Main battery Input supply (3.8V)
USB_VBUS Input supply
USB2_VBUS Detection pin Test Point.
USB_VBUS Input supply
Speaker Amplifier1 Enable
USB_VBUS Input supply
Speaker Amplifier2 Enable
Digital Ground
Battery Supply Positive Sense pin
RGB LED driver(From PMI8994)
Battery Supply Negative Sense pin
RGB LED driver(From PMI8994)
LCD Back Light supply
RGB LED driver (From PMI8994)
WLED Low side input sink1
RGB LED driver(From PMI8994)
WLED Low side input sink2
PCIE Slot Reset Pin
LCD Backlight Control PWM
PCIE Slot Wake GPIO
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Pin No.
J4.38
J4.39
J4.40
J4.41
J4.42
J4.43
J4.44
J4.45
J4.46
J4.47
J4.48
J4.49
J4.50
J4.51
J4.52
J4.53
J4.54
J4.55
J4.56
J4.57
J4.58
J4.59
J4.60
J4.61
J4.62
J4.63
J4.64
J4.65
J4.66
J4.67
J4.68
J4.69
J4.70
J4.71
J4.72
J4.73
J4.74
J4.75
J4.76
Version 1.0
Net Name
GND
PCIE1_CLK_REQ_N
USB1_HS_DM
CLK_SDC2_SD_CARD
USB1_HS_DP
BLSP6_I2C_SDA
GND
BLSP3_I2C_SDA
USB2_HS_DM
SD_CARD_DET
USB2_HS_DP
BLSP6_I2C_SCL
GND
BLSP1_UART_RX
JTAG_TDO
AUDIO_SLIMBUS_D0
JTAG_SRST_N
AUDIO_SLIMBUS_D1
JTAG_TRST_N
BLSP3_I2C_SCL
JTAG_TMS
BLSP1_UART_CTS_N
JTAG_TDI
SDC2_DAT3
JTAG_TCK
SDC2_CMD
PCM2_CLK
SDC2_DAT0
CODEC_RST_N
SDC2_DAT2
PCM2_DIN
SDC2_DAT1
PCM2_SYNC
BLSP1_UART_RTS_N
PCM2_DOUT
BLSP1_UART_TX
MI2S_3_D0
AUDIO_SLIMBUS_CLK
MI2S_3_MCLK
Default Pin Function
Digital Ground
PCIE Slot CLK request GPIO pin
USB interface 1 data Negative line
SD card CLK pin
USB interface 1 data Positive line
BLSP6 I2C Data lane
Digital Ground
BLSP3 I2C Data lane
USB interface 2 data Negative line
SD Card Detection Pin
USB interface 2 data Positive line
BLSP6 I2C Clock lane
Digital Ground
BLSP1 UART RX Data lane
JTAG interface TDO Pin
Audio Slim bus interface D0 Pin.
JTAG interface System Reset Pin.
Audio Slim bus interface D1 Pin.
JTAG interface TRST Pin.
BLSP3 I2C CLK lane
JTAG interface TMS Pin.
BLSP1 UART CTS Pin
JTAG interface TDI Pin.
SDC2 Interface data 3 lane
JTAG interface TCK Pin.
SDC2 Interface Command line
PCM interface 2 CLK line
SDC2 Interface data 0 lane
Audio Codec Reset Pin
SDC2 Interface data 2 lane
PCM interface 2 Data input
SDC2 Interface data 1 lane
PCM interface 2 SYNC Pin
BLSP1 UART RTS Pin
PCM interface 2 DOUT Pin
BLSP1 UART TX Pin
MI2S Interface 3 Data 0
Slim bus Interface Clock pin.
MI2S Interface 3 Clock Pin
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Pin No.
J4.77
J4.78
J4.79
J4.80
J4.81
J4.82
J4.83
J4.84
J4.85
J4.86
J4.87
J4.88
J4.89
J4.90
J4.91
J4.92
J4.93
J4.94
J4.95
J4.96
J4.97
J4.98
J4.99
J4.100
J5.1
J5.2
J5.3
J5.4
J5.5
J5.6
J5.7
J5.8
J5.9
J5.10
J5.11
J5.12
J5.13
J5.14
J5.15
Version 1.0
Net Name
APQ_RESOUT_N
MI2S_3_D1
SSC_PWR_EN
MI2S_3_WS
SSC_I2C_2_SDA
MI2S_3_SCK
SSC_I2C_2_SCL
HDMI_RST_N
SSC_SYNC_OUT
GND
SSC_SPI_3_MISO
HDMI_INT_GPIO
SSC_SPI_3_CS_N
SSC_UART_3_RX
SSC_SPI_3_CLK
SSC_I2C_1_SDA
SSC_SPI_3_MOSI
GND
SSC_I2C_1_SCL
USB3OTG_VBUS_EN
SSC_UART_3_TX
CSI2_RST
JTAG_PS_HOLD
CSI0_RST
HDMI_TX2_M
GND
HDMI_TX2_P
MIPI_DSI1_D1_M
GND
MIPI_DSI1_D1_P
HDMI_TX0_M
GND
HDMI_TX0_P
MIPI_DSI1_CLK_M
GND
MIPI_DSI1_CLK_P
MIPI_CSI1_D3_P
GND
MIPI_CSI1_D3_M
Default Pin Function
APQ Reset Out Pin Test Point
MI2S Interface 3 Data 1 Pin
SSC Power Enable Pin
MI2S Interface 3 WS Pin
SSC Interface I2C2 Data lane
MI2S Interface 3 SCK Pin
SSC Interface I2C 2 CLK lane
HDMI Input Reset Pin (Active Low)
SSC Interface Sync Out Pin
Digital Ground
SSC Interface SPI 3 MISO Pin
HDMI Input Interrupt Pin.
SSC Interface SPI 3 CS Pin
SSC Interface UART 3 RX Pin
SSC Interface SPI 3 CLK Pin
SSC Interface I2C 1 Data lane
SSC Interface SPI 3 MOSI Pin
Digital Ground
SSC Interface I2C 1 Clock lane
USB3 OTG VBUS Enable Pin.
SSC Interface UART 3 TX Pin
MIPI CSI2 Camera Reset Pin.
JTAG PS Hold Pin
MIPI CSI0 Camera Reset Pin.
HDMI interface line 2 Negative Output
Digital Ground
HDMI interface line 2 Positive Output
MIPI DSI1 1 line Negative out
Digital Ground
MIPI DSI1 1 line Positive out
HDMI interface line 0 Negative Output
Digital Ground
HDMI interface line 0 Positive Output
MIPI DSI1 Clock line Negative out
Digital Ground
MIPI DSI1 Clock line Positive out
MIPI DSI1 3 line Positive out
Digital Ground
MIPI DSI1 3 line Negative out
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Pin No.
J5.16
J5.17
J5.18
J5.19
J5.20
J5.21
J5.22
J5.23
J5.24
J5.25
J5.26
J5.27
J5.28
J5.29
J5.30
J5.31
J5.32
J5.33
J5.34
J5.35
J5.36
J5.37
J5.38
J5.39
J5.40
J5.41
J5.42
J5.43
J5.44
J5.45
J5.46
J5.47
J5.48
J5.49
J5.50
J5.51
J5.52
J5.53
Version 1.0
Net Name
MIPI_DSI1_D0_P
GND
MIPI_DSI1_D0_M
MIPI_CSI1_D0_M
GND
MIPI_CSI1_D0_P
MIPI_DSI1_D2_P
GND
MIPI_DSI1_D2_M
MIPI_CSI1_D1_P
GND
MIPI_CSI1_D1_M
MIPI_DSI1_D3_P
GND
MIPI_DSI1_D3_M
MIPI_CSI1_D2_P
GND
MIPI_CSI1_D2_M
HDMI_TX1_M
GND
HDMI_TX1_P
MIPI_CSI1_CLK_M
GND
MIPI_CSI1_CLK_P
HDMI_CLK_M
GND
HDMI_CLK_P
CAM_MCLK1
GND
CAM_MCLK2
CSI_SW_SEL
GND
GND
CAM_MCLK3
MIPI_CSI0_CLK_P
CAM_MCLK0
MIPI_CSI0_CLK_M
GND
GND
Default Pin Function
MIPI DSI1 0 line Positive out
Digital Ground
MIPI DSI1 0 line Negative out
MIPI CSI1 0 line Negative out
Digital Ground
MIPI CSI1 0 line Positive out
MIPI DSI1 2 line Positive out
Digital Ground
MIPI DSI1 2 line Negative out
MIPI CSI1 1 line Positive out
Digital Ground
MIPI CSI1 1 line Negative out
MIPI DSI1 3 line Positive out
Digital Ground
MIPI DSI1 3 line Negative out
MIPI CSI1 2 line Positive out
Digital Ground
MIPI CSI1 2 line Negative out
HDMI interface line 1 Negative Output
Digital Ground
HDMI interface line 1 Positive Output
MIPI CSI1 Clock line Negative out
Digital Ground
MIPI CSI1 Clock line Positive out
HDMI interface line CLK Negative Output
Digital Ground
HDMI interface line CLK Positive Output
MIPI CSI CAM MCLK1 Pin
Digital Ground
MIPI CSI CAM MCLK2 Pin
CSI Switch Select GPIO Pin
Digital Ground
Digital Ground
MIPI CSI CAM MCLK3 Pin
MIPI CSI0 Clock line Positive out
MIPI CSI CAM MCLK0 Pin
MIPI CSI0 Clock line Negative out
Digital Ground
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Pin No.
J5.54
J5.55
J5.56
J5.57
J5.58
J5.59
J5.60
J5.61
J5.62
J5.63
J5.64
J5.65
J5.66
J5.67
J5.68
J5.69
J5.70
J5.71
J5.72
J5.73
J5.74
J5.75
J5.76
J5.77
J5.78
J5.79
J5.80
J5.81
J5.82
J5.83
J5.84
J5.85
J5.86
J5.87
J5.88
J5.89
J5.90
J5.91
Version 1.0
Net Name
GND
MIPI_CSI2_CLK_M
MIPI_CSI0_D0_P
MIPI_CSI2_CLK_P
MIPI_CSI0_D0_M
GND
GND
MIPI_CSI2_D0_M
MIPI_CSI0_D1_P
MIPI_CSI2_D0_P
MIPI_CSI0_D1_M
GND
GND
MIPI_CSI2_D1_P
MIPI_CSI0_D2_P
MIPI_CSI2_D1_M
MIPI_CSI0_D2_M
GND
GND
MIPI_CSI2_D2_P
MIPI_CSI0_D3_P
MIPI_CSI2_D2_M
MIPI_CSI0_D3_M
GND
GND
MIPI_CSI2_D3_P
PCIE1_CLK_M
MIPI_CSI2_D3_M
PCIE1_CLK_P
GND
GND
PCIE2_CLK_P
PCIE1_RX_M
PCIE2_CLK_M
PCIE1_RX_P
GND
GND
PCIE2_RX_M
Default Pin Function
Digital Ground
MIPI CSI2 Clock line Negative out
MIPI CSI0 0 line Positive out
MIPI CSI2 Clock line Positive out
MIPI CSI0 0 line Negative out
Digital Ground
Digital Ground
MIPI CSI2 0 line Negative out
MIPI CSI0 1 line Positive out
MIPI CSI2 0 line Positive out
MIPI CSI0 1 line Negative out
Digital Ground
Digital Ground
MIPI CSI2 1 line Positive out
MIPI CSI0 2 line Positive out
MIPI CSI2 1 line Negative out
MIPI CSI0 2 line Negative out
Digital Ground
Digital Ground
MIPI CSI2 2 line Positive out
MIPI CSI0 3 line Positive out
MIPI CSI2 2 line Negative out
MIPI CSI0 3 line Negative out
Digital Ground
Digital Ground
MIPI CSI2 3 line Positive out
PCIE interface 1 Clock Negative Output
MIPI CSI2 3 line Negative out
PCIE interface 1 Clock Positive Output
Digital Ground
Digital Ground
PCIE interface 2 Clock Positive Output
PCIE interface 1 RX Negative Output
PCIE Interface 2 Clock Negative Output
PCIE interface 1 RX Positive Output
Digital Ground
Digital Ground
PCIE interface 2 RX Negative Output
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Hardware Reference Manual
Pin No.
J5.92
J5.93
J5.94
J5.95
J5.96
J5.97
J5.98
J5.99
J5.100
J6.1
J6.2
J6.3
J6.4
J6.5
J6.6
J6.7
J6.8
J6.9
J6.10
J6.11
J6.12
J6.13
J6.14
J6.15
J6.16
J6.17
J6.18
J6.19
J6.20
J6.21
J6.22
J6.23
J6.24
J6.25
J6.26
J6.27
J6.28
J6.29
J6.30
Version 1.0
Net Name
PCIE1_TX_M
PCIE2_RX_P
PCIE1_TX_P
GND
GND
PCIE2_TX_P
VREG_DISP
PCIE2_TX_M
VREG_DISN
MIPI_DSI0_CLK_P
MIPI_DSI0_D3_P
MIPI_DSI0_CLK_M
MIPI_DSI0_D3_M
GND
GND
DSI_BACKLIGHT_PWM
MIPI_DSI0_D2_P
CSI_I2C1_SDA
MIPI_DSI0_D2_M
CSI_I2C1_SCL
GND
CSI_I2C0_SDA
MIPI_DSI0_D0_M
CSI_I2C0_SCL
MIPI_DSI0_D0_P
BLSP12_DSI_I2C_SCL
GND
BLSP12_DSI_I2C_SDA
MIPI_DSI0_D1_P
BLSP8_I2C_SCL
MIPI_DSI0_D1_M
HDMI_HOTPLUG_DET
GND
HDMI_CEC
USB1_SS_TM
USB_HUB_RESET_N
USB1_SS_TP
HDMI_DDC_CLK
GND
Default Pin Function
PCIE interface 1 TX Negative Output
PCIE interface 2 RX Positive Output
PCIE interface 1 TX Positive Output
Digital Ground
Digital Ground
PCIE interface 2 TX Positive Output
Supply for External Display Positive
PCIE interface 2 TX Negative Output
Supply for External Display Negative
MIPI display serial interface 0 clock – positive
MIPI display serial interface 0 lane 3 – positive
MIPI display serial interface 0 clock – negative
MIPI display serial interface 0 lane 3 – Negative
Digital Ground
Digital Ground
PWM Signal for External Display
MIPI display serial interface 0 lane 2 – Positive
I2C interface Data for CSI
MIPI display serial interface 0 lane 2 – Negative
I2C interface Clock for CSI
Digital Ground
I2C interface Data for CSI
MIPI display serial interface 0 lane 0 – Negative
I2C interface Clock for CSI
MIPI display serial interface 0 lane 0 – Positive
BLSP interface I2C Clock for DSI
Digital Ground
BLSP interface I2C Data Lane for DSI
MIPI display serial interface 0 lane 1 – Positive
BLSP interface I2C Clock
MIPI display serial interface 0 lane 1 – Negative
HDMI Hot Plug Detect Signal
Digital Ground
HDMI interface CEC line
Super Speed USB interface TX Negative
USB HUB RESET signal (active low)
Super Speed USB interface TX Positive
HDMI interface DDC clock line
Digital Ground
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Hardware Reference Manual
Pin No.
J6.31
J6.32
J6.33
J6.34
J6.35
J6.36
J6.37
J6.38
J6.39
J6.40
J6.41
J6.42
J6.43
J6.44
J6.45
J6.46
J6.47
J6.48
J6.49
J6.50
J6.51
J6.52
J6.53
J6.54
J6.55
J6.56
J6.57
J6.58
J6.59
J6.60
J6.61
J6.62
J6.63
J6.64
J6.65
J6.66
Version 1.0
Net Name
HDMI_DDC_DATA
USB1_SS_RP
BLSP9_SPI_CLK
USB1_SS_RM
BLSP8_UART_TX
GND
BLSP8_UART_RX
BOOT_CONFIG_2
PCIE2_CLK_REQ_N
BOOT_CONFIG_3/CSI1_RST
PCIE2_WAKE_N
USB_BOOT/HDMI_MI2S_4_MC
LK
BLSP8_I2C_SDA
MAG_SENSOR_INT1
PCIE2_RST_N
MAG_SENSOR_INT2
AUDIO_INT1
ALSPG_INT_N
TX_GTR_THRES
GYRO_SENSOR_INT2
BLSP9_SPI_CS_N
BATT_THERM
BLSP9_SPI_MISO
GND
BLSP9_SPI_MOSI
AUDIO_INT2
VREG_S12A_1P15
VOLUME_UP_N
VREG_S12A_1P15
GND
PM_RESIN_N
PM_MPP_GPIO_07
PHONE_ON_N
DSI0_RST_N
PM_MPP_GPIO_06
GND
Default Pin Function
HDMI interface DDC data line
Super Speed USB interface RX Positive
BLSP interface SPI Clock
Super Speed USB interface RX Negative
BLSP interface UART TX
Digital Ground
BLSP interface UART RX
Boot configuration bit 2
PCIE Clock Request Signal (active Low)
Boot configuration bit 2/ CSI RESET Signal
PCIE interface WAKE Signal (Active Low)
USB BOOT Signal/ HDMI MI2S 4 Master Clock
BLSP interface I2C Data Line
Interrupt Signal for Magneto sensor
PCIE interface RESET Signal (Active Low)
Interrupt Signal for Magneto sensor
Interrupt Signal for Audio interface
PMIC GPIO for Sensors
PMIC GPIO for Sensors
Interrupt Signal for Gyro Sensor
BLSP interface for SPI Chip select
Battery Thermistor Pin
BLSP interface for SPI MISO
Digital Ground
BLSP interface for SPI MOSI
Interrupt Signal for Audio interface
1.15V Supply for Carrier Board
Volume UP pin for Audio (Active Low)
1.15V Supply for Carrier Board
Digital Ground
PMIC RESET input pin (Active Low)
PMIC MPP GPIO pin
PHONE ON General purpose pin
RESET pin for DSI interface
PMIC GPIO on Carrier Board
Digital Ground
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Hardware Reference Manual
Pin No.
J6.67
J6.68
J6.69
J6.70
J6.71
J6.72
J6.73
J6.74
J6.75
J6.76
J6.77
J6.78
J6.79
J6.80
J6.81
J6.82
J6.83
J6.84
J6.85
J6.86
J6.87
J6.88
J6.89
J6.90
J6.91
J6.92
J6.93
J6.94
J6.95
J6.96
J6.97
J6.98
J6.99
J6.100
Net Name
USB_SS_ID
GYRO_SENSOR_INT1
PM_MPP_GPIO_02
DSI_TOUCH_INT
PM_MPP_GPIO_04
BOOT_CONFIG_1
GND
HDMI_MI2S_4_D3
VREG_L13A_2P95
HDMI_MI2S_4_D0
VREG_L13A_2P95
HDMI_MI2S_4_WS
USB_HS1_VBUS_DET
HDMI_MI2S_4_D1
GND
HDMI_MI2S_4_SCK
VCOIN
HDMI_MI2S_4_D2
VREG_L21A_2P95
LTE_COEX_RX
VREG_L21A_2P95
LTE_COEX_TX
VREG_S4A_1P8
VREG_S4A_1P8
VREG_S4A_1P8
GND
VREG_S4A_1P8
GND
AUDIO_CODEC_MCLK
GND
VREG_1P225
GND
VREG_1P225
GND
Default Pin Function
Super Speed USB ID detect pin
Interrupt Signal for Gyro Sensor
PMIC GPIO for Carrier Board
Interrupt Signal for DSI Touchscreen
PMIC GPIO for Carrier Board
Boot configuration bit 1
Digital Ground
HDMI MI2S 4 Data Lane 3 signal
2.95V Supply for Carrier Board
HDMI MI2S 4 Data Lane 0 signal
2.95V Supply for Carrier Board
HDMI MI2S 4 Word Select signal
High Speed USB VBUS Detect signal
HDMI MI2S 4 Data Lane 1 signal
Digital Ground
HDMI MI2S 4 Serial Clock signal
Input supply from Coin Cell Battery
HDMI MI2S 4 Data Lane 2 signal
2.95V Supply for Carrier Board
LTE COEX RX test Point Pin.
2.95V Supply for Carrier Board
LTE COEX TX test Point Pin.
1.8V Supply for Carrier Board
1.8V Supply for Carrier Board
1.8V Supply for Carrier Board
Digital Ground
1.8V Supply for Carrier Board
Digital Ground
Audio Codec Interface MCLK Pin
Digital Ground
1.225V Supply for Carrier Board.
Digital Ground
1.225V Supply for Carrier Board.
Digital Ground
Table 4 : Q820 SOM Connectors Pin outs
Version 1.0
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Hardware Reference Manual
4.2
SoM’s I/F exported to B2B connector.
4.2.1 MIPI CSI2 Interface
The Q820 SOM Supports three 4-Lane MIPI CSI Interface with following features:



Three 4-Lane MIPI CSI with 4+4+4 or 4+4+2+1 Configuration, 2.0 Gbps per Lane
Dual 14-bit image signal processing (ISP) – 28 MP and 13 MP, 600 MHz; 32 MP 30 ZSL with
dual-ISP; 16 MP 30 ZSL with single-ISP; Temp NR v2, ASF3, Demosaic, Dual-AF, LTM, CAC,
Green Imbalance, Pedestal, stats upgrades, and image quality enhancements
Two Dedicated I2C (CCI0 & CCI1) channel for Camera Control
Pin outs for MIPI CSI interfaces on B2B Connector are as below:
Pin No.
J5.50
J5.52
J5.56
J5.58
J5.62
J5.64
J5.68
J5.70
J5.74
J5.76
J5.51
Net Name
MIPI_CSI0_CLK_P
MIPI_CSI0_CLK_M
MIPI_CSI0_D0_P
MIPI_CSI0_D0_M
MIPI_CSI0_D1_P
MIPI_CSI0_D1_M
MIPI_CSI0_D2_P
MIPI_CSI0_D2_M
MIPI_CSI0_D3_P
MIPI_CSI0_D3_M
CAM_MCLK0
Default Pin Function
MIPI Camera Serial Interface 0 Clock Positive
MIPI Camera Serial Interface 0 Clock Negative
MIPI Camera Serial Interface 0 lane-0 Positive
MIPI Camera Serial Interface 0 lane-0 Negative
MIPI Camera Serial Interface 0 lane-1 Positive
MIPI Camera Serial Interface 0 lane-1 Negative
MIPI Camera Serial Interface 0 lane-2 Positive
MIPI Camera Serial Interface 0 lane-2 Negative
MIPI Camera Serial Interface 0 lane-3 Positive
MIPI Camera Serial Interface 0 lane-3 Negative
Master Clock 0 for Camera
Table 5 : MIPI CSI0 Pin outs
Pin No.
J5.39
J5.37
J5.21
J5.19
J5.25
J5.27
J5.31
J5.33
J5.13
J5.15
J5.43
Net Name
MIPI_CSI1_CLK_P
MIPI_CSI1_CLK_M
MIPI_CSI1_D0_P
MIPI_CSI1_D0_M
MIPI_CSI1_D1_P
MIPI_CSI1_D1_M
MIPI_CSI1_D2_P
MIPI_CSI1_D2_M
MIPI_CSI1_D3_P
MIPI_CSI1_D3_M
CAM_MCLK1
Default Pin Function
MIPI Camera Serial Interface 1 Clock Positive
MIPI Camera Serial Interface 1 Clock Negative
MIPI Camera Serial Interface 1 lane-0 Positive
MIPI Camera Serial Interface 1 lane-0 Negative
MIPI Camera Serial Interface 1 lane-1 Positive
MIPI Camera Serial Interface 1 lane-1 Negative
MIPI Camera Serial Interface 1 lane-2 Positive
MIPI Camera Serial Interface 1 lane-2 Negative
MIPI Camera Serial Interface 1 lane-3 Positive
MIPI Camera Serial Interface 1 lane-3 Negative
Master Clock 1 for Camera
Table 6 : MIPI CSI1 Pin outs
Version 1.0
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Hardware Reference Manual
Pin No.
J5.57
J5.55
J5.63
J5.61
J5.67
J5.69
J5.73
J5.75
J5.79
J5.81
J5.45
Net Name
MIPI_CSI2_CLK_P
MIPI_CSI2_CLK_M
MIPI_CSI2_D0_P
MIPI_CSI2_D0_M
MIPI_CSI2_D1_P
MIPI_CSI2_D1_M
MIPI_CSI2_D2_P
MIPI_CSI2_D2_M
MIPI_CSI2_D3_P
MIPI_CSI2_D3_M
CAM_MCLK2
Default Pin Function
MIPI Camera Serial Interface 2 Clock Positive
MIPI Camera Serial Interface 2 Clock Negative
MIPI Camera Serial Interface 2 lane-0 Positive
MIPI Camera Serial Interface 2 lane-0 Negative
MIPI Camera Serial Interface 2 lane-1 Positive
MIPI Camera Serial Interface 2 lane-1 Negative
MIPI Camera Serial Interface 2 lane-2 Positive
MIPI Camera Serial Interface 2 lane-2 Negative
MIPI Camera Serial Interface 2 lane-3 Positive
MIPI Camera Serial Interface 2 lane-3 Negative
Master Clock 2 for Camera
Table 7 : MIPI CSI2 Pin outs
Pin No.
J6.9
J6.11
J6.13
J6.15
J5.49
Net Name
CSI_I2C1_SDA
CSI_I2C1_SCL
CSI_I2C0_SDA
CSI_I2C0_SCL
CAM_MCLK3
Default Pin Function
Camera I2C0 Data Line
Camera I2C0 Clock Line
Camera I2C1 Data Line
Camera I2C1 Clock Line
Master Clock 3 for Camera
Table 8 : Dedicated I2C Signals
4.2.2 MIPI DSI Interface
The Q820 SOM Supports the concurrent displays two 4-Lanes MIPI DSI1.2 interface and one
HDMI Transmit interface.

DSI0 and DSI1
o 1920 x 1200 with DSI0/1
o 2560 x 1600 with VESA DSC 1.1
o 3840 x 2160 with DSI0 + DSI1 with VESA DSC1.1
 HDMI Transmit
o Up to 4096 x 2160 at 60 fps
 Maximum Concurrency Configurations
o 3840 x 2400 or 4096 x 2160 at 60Hz primary display + 4096 x 2160 at 60Hz
HDMI Display
o 2560 x 1600 at 60 fps primary display + 2560 x 1600 at 60 fps secondary display
+ 3840 x 2160 at 60 fps HDMI
Pin outs for MIPI DSI Interfaces on B2B connector are as below:
Version 1.0
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Hardware Reference Manual
Pin No.
J6.1
J6.3
J6.16
J6.14
J6.20
J6.22
J6.8
J6.10
J6.2
J6.4
Net Name
MIPI_DSI0_CLK_P
MIPI_DSI0_CLK_M
MIPI_DSI0_D0_P
MIPI_DSI0_D0_M
MIPI_DSI0_D1_P
MIPI_DSI0_D1_M
MIPI_DSI0_D2_P
MIPI_DSI0_D2_M
MIPI_DSI0_D3_P
MIPI_DSI0_D3_M
Default Pin Function
MIPI Display Serial Interface 0 Clock Positive
MIPI Display Serial Interface 0 Clock Negative
MIPI Display Serial Interface 0 lane-0 Positive
MIPI Display Serial Interface 0 lane-0 Negative
MIPI Display Serial Interface 0 lane-1 Positive
MIPI Display Serial Interface 0 lane-1 Negative
MIPI Display Serial Interface 0 lane-2 Positive
MIPI Display Serial Interface 0 lane-2 Negative
MIPI Display Serial Interface 0 lane-3 Positive
MIPI Display Serial Interface 0 lane-3 Negative
Table 9 : MIPI DSI0 Pin outs
Pin No.
J5.12
J5.10
J5.16
J5.18
J5.6
J5.4
J5.22
J5.24
J5.28
J5.30
Net Name
MIPI_DSI1_CLK_P
MIPI_DSI1_CLK_M
MIPI_DSI1_D0_P
MIPI_DSI1_D0_M
MIPI_DSI1_D1_P
MIPI_DSI1_D1_M
MIPI_DSI1_D2_P
MIPI_DSI1_D2_M
MIPI_DSI1_D3_P
MIPI_DSI1_D3_M
Default Pin Function
MIPI Display Serial Interface 1 Clock Positive
MIPI Display Serial Interface 1 Clock Negative
MIPI Display Serial Interface 1 lane-0 Positive
MIPI Display Serial Interface 1 lane-0 Negative
MIPI Display Serial Interface 1 lane-1 Positive
MIPI Display Serial Interface 1 lane-1 Negative
MIPI Display Serial Interface 1 lane-2 Positive
MIPI Display Serial Interface 1 lane-2 Negative
MIPI Display Serial Interface 1 lane-3 Positive
MIPI Display Serial Interface 1 lane-3 Negative
Table 10 : MIPI DSI1 Pin outs
Pin No.
J5.42
J5.10
Net Name
HDMI_CLK_P
HDMI_CLK_M
Default Pin Function
HDMI Interface Clock Positive
HDMI Interface Clock Negative
J5.9
J5.7
J5.36
J5.34
J5.3
J5.1
J6.25
J6.29
J6.31
J6.23
J4.84
HDMI_TX0_P
HDMI_TX0_M
HDMI_TX1_P
HDMI_TX1_M
HDMI_TX2_P
HDMI_TX2_M
HDMI_CEC
HDMI_DDC_CLK
HDMI_DDC_DATA
HDMI_HOTPLUG_DET
HDMI_RST_N
HDMI Interface Transmit lane 0 Positive
HDMI Interface Transmit lane 0 Negative
HDMI Interface Transmit lane 1 Positive
HDMI Interface Transmit lane 1 Negative
HDMI Interface Transmit lane 2 Positive
HDMI Interface Transmit lane 2 Negative
HDMI Interface CEC Signal
HDMI Interface DDC Clock Signal
HDMI Interface DDC Data Signal
HDMI Interface Hot plug detect Signal
HDMI Interface Reset Signal
Table 11 : HDMI Pin outs
Version 1.0
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Hardware Reference Manual
4.2.3 Digital Audio I2S Interface
The Q820 SOM supports two digital I2S ports on Connector. Both I2S port is provided on
Expansion Connector & out of them one is also used for HDMI Audio signals.
Pin outs for I2S Interface is as below:
Pin No.
J4.72
J4.78
Net Name
MI2S_3_D0
MI2S_3_D1
Default Pin Function
MI2S 3 digital audio interface serial Data 0 Signal
MI2S 3 digital audio interface serial Data 1 Signal
J4.76
J4.80
J4.82
J6.74
J6.84
J6.80
J6.76
MI2S_3_MCLK
MI2S_3_WS
MI2S_3_SCK
HDMI_MI2S_4_D3
HDMI_MI2S_4_D2
HDMI_MI2S_4_D1
HDMI_MI2S_4_D0
USB_BOOT/HDMI_MI2S_4_
MCLK
HDMI_MI2S_4_WS
HDMI_MI2S_4_SCK
MI2S 3 digital audio interface master clock Signal
MI2S 3 digital audio interface word select Signal
MI2S 3 digital audio interface Serial clock Signal
MI2S 4 digital audio interface serial Data 3 Signal
MI2S 4 digital audio interface serial Data 2 Signal
MI2S 4 digital audio interface serial Data 1 Signal
MI2S 4 digital audio interface serial Data 0 Signal
MI2S 4 digital audio interface master clock Signal/ Forced
USB Boot Pin
MI2S 4 digital audio interface word select Signal
MI2S 4 digital audio interface Serial clock Signal
J6.42
J6.78
J6.82
Table 12 : I2S Interface Pin outs
4.2.4 PCM Interface
APQ8096 supports four PCM Ports; out of them one PCM interface is used for Wi-Fi + BT
(QCA6174) Interface. One PCM port is provided on B2B connector.
Pin outs of PCM interface comes on B2B connector are as below:
Pin No.
J4.64
J4.68
Net Name
PCM2_CLK
PCM2_DIN
Default Pin Function
PCM interface 2 Clock signal
PCM interface 2 Data In signal
J4.72
J4.70
PCM2_DOUT
PCM2_SYNC
PCM interface 2 Data Out signal
PCM interface 2 Sync signal
Table 13 : PCM Interface Pin outs
Version 1.0
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Hardware Reference Manual
4.2.5 USB Interface
The Q820 supports two USB ports one USB 2.0 high speed & one USB 3.0 super speed
Pin outs for USB Interface is as below:
Pin No.
J4.48
J4.48
Net Name
USB2_HS_DP
USB2_HS_DM
Default Pin Function
High Speed USB Interface 2 Data Positive
High Speed USB Interface 2 Data Negative
J4.20
J4.96
J6.27
USB2_VBUS_DET
USB3OTG_VBUS_EN
USB_HUB_RESET_N
VBUS Detection Signal
OTG_VBUS Enable Signal
USB Hub Reset Signal (Active Low)
Table 14 : USB 2.0 Interface Pin outs
Pin No.
J4.42
J4.40
Net Name
USB1_HS_DP
USB1_HS_DM
Default Pin Function
High Speed USB Interface 1 Data Positive
High Speed USB Interface 1 Data Negative
J6.28
J6.26
J6.32
J6.34
J6.79
J6.67
USB1_SS_TP
USB1_SS_TM
USB1_SS_RP
USB1_SS_RM
USB_HS1_VBUS_DET
USB_SS_ID
Super Speed USB Interface 1 Transmit Positive
Super Speed USB Interface 1 Transmit Negative
Super Speed USB Interface 1 Receive Positive
Super Speed USB Interface 1 Receive Negative
USB_VBUS Detect Signal
USB Interface ID Pin
Table 15 : USB 3.0 Interface Pin outs
4.2.6
JTAG Interface
The Q820 SOM has one JTAG Interface for debug purpose with following features:
 32KB embedded trace buffer (ETB)
 5-pin system trace interface for debug
 Supports Advanced Event Triggering (AET)
 All processors can be emulated via JTAG ports
 Frequency: 20MHz
Pin outs for JTAG Interface which comes on connector are as below:
Pin No.
J4.52
J4.58
Net Name
JTAG_TDO
JTAG_TMS
Default Pin Function
JTAG Data Output
JTAG mode-select input
J4.60
J4.62
J4.54
J4.56
J4.99
JTAG_TDI
JTAG_TCK
JTAG_SRST_N
JTAG_TRST_N
JTAG_PS_HOLD
JTAG data input
JTAG clock input
JTAG reset for debug
JTAG reset
Power-supply hold control input
Table 16 : JTAG Interface Pin outs
Version 1.0
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Hardware Reference Manual
4.2.7
uSD Card Interface
The Q820 SOM has uSD Card Interface for connecting external memory devices for storing
data.
Pin outs for SD Card interface which comes on connector are as below:
Pin No.
J4.61
J4.67
Net Name
SDC2_DAT3
SDC2_DAT2
Default Pin Function
Secure digital controller 2 data bit 3
Secure digital controller 2 data bit 2
J4.69
J4.65
J4.63
J4.41
J4.47
SDC2_DAT1
SDC2_DAT0
SDC2_CMD
CLK_SDC2_SD_CARD
SD_CARD_DET
Secure digital controller 2 data bit 1
Secure digital controller 2 data bit 0
Secure digital controller 2 Command
Secure digital controller 2 Clock
Secure digital card detection
Table 17 : SD Card Interface Pin outs
4.2.8
BLSP Interface
The Q820 SOM has Eight BLSP Ports from which three BLSP Ports are 4 bit width & three BLSP
Ports are two bit wide. As processor supports 12 BLSP Ports user can configure BLSP Ports as
I2C, UART, or SPI.
Pin outs for BLSP interface which comes on connector are as below:
Pin No.
J4.51
J4.73
Net Name
BLSP1_UART_RX
BLSP1_UART_TX
Default Pin Function
BLSP1 UART RX lane
BLSP1 UART TX lane
J4.71
J4.59
J4.45
J4.57
J4.43
J4.49
J6.21
J6.43
J6.35
J6.37
J6.55
J6.53
J6.33
J6.51
J6.17
J6.19
BLSP1_UART_RTS_N
BLSP1_UART_CTS_N
BLSP3_I2C_SDA
BLSP3_I2C_SCL
BLSP6_I2C_SDA
BLSP6_I2C_SCL
BLSP8_I2C_SCL
BLSP8_I2C_SDA
BLSP8_UART_TX
BLSP8_UART_RX
BLSP9_SPI_MOSI
BLSP9_SPI_MISO
BLSP9_SPI_CLK
BLSP9_SPI_CS_N
BLSP12_DSI_I2C_SCL
BLSP12_DSI_I2C_SDA
BLSP1 UART RTS lane
BLSP1 UART CTS lane
BLSP3 I2C Data lane
BLSP3 I2C Clock lane
BLSP6 I2C Data lane
BLSP6 I2C Clock lane
BLSP8 I2C Clock lane
BLSP8 I2C Data lane
BLSP interface UART TX (Used as Debug UART)
BLSP interface UART RX (Used as Debug UART)
BLSP interface for SPI MOSI
BLSP interface for SPI MISO
BLSP interface SPI Clock
BLSP interface for SPI Chip select
BLSP interface I2C Clock for DSI
BLSP interface I2C Data Lane for DSI
Table 18 : BLSP Interface Pin outs
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4.2.9
PCIe Interface
Processor APQ8096 Supports three PCIe Ports, out of them one PCIe (PCIe0) port is used on
SOM Board for Wi-Fi + BT ( QCA6174 ) interface & other two PCIe ports (PCIe1 & PCIe2) are
provided on Connector.
Pin outs for two PCIe Ports (PCIe1 & PCIe2) which comes on Connector are as below:
Pin No.
J5.82
J5.80
Net Name
PCIE1_CLK_P
PCIE1_CLK_M
Default Pin Function
PCIE interface 1 Clock Positive
PCIE interface 1 Clock Negative Output
J5.94
J5.92
J5.88
J5.86
J4.35
J4.37
J4.39
J5.85
J5.87
J5.97
J5.99
J5.93
J5.91
J6.45
J6.41
J6.39
PCIE1_TX_P
PCIE1_TX_M
PCIE1_RX_P
PCIE1_RX_M
PCIE1_RST_N
PCIE1_WAKE_N
PCIE1_CLK_REQ_N
PCIE2_CLK_P
PCIE2_CLK_M
PCIE2_TX_P
PCIE2_TX_M
PCIE2_RX_P
PCIE2_RX_M
PCIE2_RST_N
PCIE2_WAKE_N
PCIE2_CLK_REQ_N
PCIE interface 1 TX Positive Output
PCIE interface 1 TX Negative Output
PCIE interface 1 RX Positive Output
PCIE interface 1 RX Negative Output
PCIE Slot Reset Pin
PCIE Slot Wake GPIO
PCIE Slot CLK request GPIO pin
PCIE interface 2 Clock Positive Output
PCIE Interface 2 Clock Negative Output
PCIE interface 2 TX Positive Output
PCIE interface 2 TX Negative Output
PCIE interface 2 RX Positive Output
PCIE interface 2 RX Negative Output
PCIE interface RESET Signal (Active Low)
PCIE interface WAKE Signal (Active Low)
PCIE Clock Request Signal (active Low)
Table 19 : PCIe Interface Pin outs
4.2.10 SSC Interface
Processor APQ8096 Supports the feature of always on sensor interface which can support the
different sensor interface like magnetometer, accelerometer and gyroscope based on the I2C,
SPI protocols. The Q820 SOM has three port SSC interface on B2B connector.
Pin No.
J4.95
J4.92
Net Name
SSC_I2C_1_SCL
SSC_I2C_1_SDA
Default Pin Function
SSC Interface I2C 1 Clock lane
SSC Interface I2C 1 Data lane
J4.81
J4.83
J4.93
J4.87
J4.91
J4.89
SSC_I2C_2_SDA
SSC_I2C_2_SCL
SSC_SPI_3_MOSI
SSC_SPI_3_MISO
SSC_SPI_3_CLK
SSC_SPI_3_CS_N
SSC Interface I2C2 Data lane
SSC Interface I2C 2 CLK lane
SSC Interface SPI 3 MOSI Pin
SSC Interface SPI 3 MISO Pin
SSC Interface SPI 3 CLK Pin
SSC Interface SPI 3 CS Pin
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J4.90
J4.97
J4.79
J4.85
SSC_UART_3_RX
SSC_UART_3_TX
SSC_PWR_EN
SSC_SYNC_OUT
SSC Interface UART 3 RX Pin
SSC Interface UART 3 TX Pin
SSC Power Enable Pin
SSC Interface Sync Out Pin
Table 20 : SSC Interface Pin outs
4.2.11 PMIC GPIOs
The Q820 SOM has five PMIC GPIOs on B2B connector which can be used as GPIO, CLOCK or
PWM as per software configuration.
Pin No.
J6.69
J6.71
Net Name
PM_MPP_GPIO_02
PM_MPP_GPIO_04
Default Pin Function
PMIC GPIO for Carrier
PMIC GPIO for Carrier
J6.65
J6.62
J6.61
PM_MPP_GPIO_06
PM_MPP_GPIO_07
PM_RESIN_N
PMIC GPIO for Carrier
PMIC GPIO for Carrier
PMIC GPIO for Carrier
Table 21 : PMIC GPIOs
4.2.12 Wi-Fi + BT Interface
The Q820 SOM has low power QCA6174-1A Integrated Dual-Band 2 X 2 802.11ac WLAN +
Bluetooth 4.1 module. QCA6174 IC is integrated with processor using PCIe, UART & PCM
Interface .The QCA6174A is a single-die wireless local area network (WLAN) and Bluetooth
combo solution to support 2 × 2 multiple input, multiple output (MIMO) with two spatial
streams IEEE802.11 a/b/g/n/ac WLAN standards and Bluetooth 4.1 + HS enabling seamless
integration of WLAN/Bluetooth and low energy technology.
4.2.13 GPS Interface
The Q820 SOM supports GPS interface, for which the WGR7640 GPS receiver is integrated with
the Processor APQ8096. X.FL connector is provided on SOM and carrier card which are
connected through X.FL cable. Carrier board has U.FL connector to connect external antenna
using it.
4.2.14 Boot Configuration
The Q820 SOM has 4 pins for Boot Configuration on B2B connector. According to the status
of boot configuration pin user can boot the board in different modes. User can also use
this boot configuration pins as GPIOs.
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Table 22 : Boot Configurations
4.2.15 Systems LEDs
The Q820 SOM contains two LEDs for the indication purpose. Two LEDs mounted on the SOM board
Reference LED2 and LED3. LED2 is used for the processor out of RESET Indication and LED3 is used for VPH
Power on.
4.2.16 Power
The Q820 SOM has VABTT+ Pins on B2B connector for supply the PMIC PMI8994 which generates VPH
required for PM8996 PMIC on SOM Board. PM8996 PMIC generate different supply rail for Processors
and various ICs on SOM Board. There is some supply rail provided on B2B connector which is generated
by PM8996 for external use.
Pin No.
J4.1
J4.2
J4.3
J4.4
J4.5
J4.6
J4.7
J4.8
J4.9
J4.10
J4.11
J4.12
J4.13
J4.14
Version 1.0
Net Name
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
VBATT+
Default Pin Function
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
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J4.15
J4.16
J4.18
J4.17
J4.19
J4.21
J4.23
J6.89
J6.90
J6.91
J6.93
J6.57
J6.59
J6.75
J6.77
J6.85
J6.87
J6.97
J6.99
J6.83
J5.98
J5.100
J4.25
J4.38
J4.44
J4.50
J4.86
J4.94
J5.2
J5.5
J5.8
J5.11
J5.14
J5.17
J5.20
J5.23
J5.26
J5.29
J5.32
J5.35
J5.38
Version 1.0
VBATT+
VBATT+
VBATT+
USB_VBUS
USB_VBUS
USB_VBUS
USB_VBUS
VREG_S4A_1P8
VREG_S4A_1P8
VREG_S4A_1P8
VREG_S4A_1P8
VREG_S12A_1P15
VREG_S12A_1P15
VREG_L13A_2P95
VREG_L13A_2P95
VREG_L21A_2P95
VREG_L21A_2P95
VREG_1P225
VREG_1P225
VCOIN
VREG_DISP
VREG_DISN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Main Battery Input Supply
Main Battery Input Supply
Main Battery Input Supply
USB_VBUS Input Supply
USB_VBUS Input Supply
USB_VBUS Input Supply
USB_VBUS Input Supply
1.8V Supply For Carrier
1.8V Supply For Carrier
1.8V Supply For Carrier
1.8V Supply For Carrier
1.15V Supply For Carrier
1.15V Supply For Carrier
2.95V Supply For Carrier
2.95V Supply For Carrier
2.95V Supply For Carrier
2.95V Supply For Carrier
1.225V Supply For Carrier
1.225V Supply For Carrier
3.0V from Coin Cell
Supply for Backlight Driver
Supply for Backlight Driver
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
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J5.41
J5.44
J5.47
J5.48
J5.53
J5.54
J5.59
J5.60
J5.65
J5.66
J5.71
J5.72
J5.77
J5.78
J5.83
J5.84
J5.89
J5.90
J5.95
J5.96
J6.5
J6.6
J6.12
J6.18
J6.24
J6.30
J6.36
J6.54
J6.60
J6.66
J6.73
J6.81
J6.92
J6.94
J6.96
J6.98
J6.100
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Table 23 : Power Pins
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4.3 Electrical Specifications
4.3.1
Absolute Maximum Ratings
Parameter
Min
Max
Unit
VBATT+
Main Battery Input Supply Voltage
-0.5
6.0
V
VPH
VPH Input Supply Voltage
-0.5
6.0
V
VCOIN
RTC Input Supply Voltage
-0.5
3.5
V
USB_VBUS
USB VBUS Input Supply Voltage
-0.5
6.0
V
Table 24 : Absolute Maximum Ratings
4.3.2
Operating Conditions
Parameter
Min
Typ
Max
Unit
VBATT+
Main Battery Input Supply Voltage
3.2
3.8
4.5
V
VPH
VPH Input Supply Voltage
3.2
3.7
4.5
V
VCOIN
RTC Input Supply Voltage
2.0
3.0
3.3
V
USB_VBUS
USB VBUS Input Supply Voltage
2.0
5.0
5.25
V
Table 25 : Operating Conditions
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4.4 Mechanical Specification
The Dimension of Q820 SOM is 53mm X 25mm.
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5
About eInfochips
eInfochips is a partner of choice for Fortune 500 companies for product innovation and hi-tech
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Today, more than 1400 chip mates operate from over 10 Design Centers and dozen Sales Offices spread
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Technical Assistance:
eInfochips Qualcomm portal
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Tel: +1-408-496-1882
Fax: +1-801-650-1480
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