COMPUTER ARCHITECTURE‐ IT0205
M.Thenmozhi/Kayalvizhi Jayavel/M.B.Panbu
Asst.Prof.(Sr.G)/Asst.Prof.(Sr.G)/Asst.Prof.(O.G)
Department of IT
SRM University, Kattankulathur
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Disclaimer
The contents of the slides are solely for the purpose of teaching students at SRM University. All copyrights and Trademarks of organizations/persons apply even if not specified explicitly. 2
UNIT‐IIi : computer arithmetic
Fixed point binary Data Representation
– Signed magnitude
– Signed 1’s complement
– Signed 2’s complement
Addition and subtraction algorithms
Booth multiplication algorithm
Division algorithm
Binary‐coded decimal (BCD) data
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Data representation
Signed magnitude – consists of the magnitude and negative sign (sign bit in binary, ‘0’ for positive and ‘1’ for negative)
– E.g. +14 = 0 0001110, ‐14= 1 0001110
Signed 1’s complement – leaving out the sign bit, convert all 1’s to 0’s and 0’s to 1’s in the signed magnitude form of the data
– E.g. ‐14 = 1 1110001
Signed 2’s complement – Add 1 to signed 1’s complement representation of the data
– E.g. ‐14 = 1 1110010 4
Addition and subtraction algorithms
Signed magnitude addition and subtraction – For an add operation, identical signs dictate that the magnitudes be added, different signs require that the magnitudes be subtracted
– For subtraction operation, different signs dictate that magnitudes be added, identical signs require that magnitudes be subtracted
AVF – Add‐overflow flip‐flop holds the overflow bit when A and B are added
Addition of A and B is done through parallel adder.
Flowchart for add and subtract operation is shown in the next slide
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Flowchart for add and subtract
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Multiplication algorithm
Booth Multiplication Algorithm – procedure for multiplying binary integers in signed‐2’s complement representation
Booth algorithm requires examination of the multiplier bits and shifting of the partial product
Qn ‐ LSB of multiplier
Extra flip flop Qn+1 is appended to the multiplier bits to facilitate double bit inspection of the multiplier.
Compare bits of Qn and Qn+1
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Booth multiplication algorithm
0 0 – shift only
1 1 – shift only
0 1 – Add multiplicand to AC and shift
1 0 – Subtract multiplicand from AC and shift
Initial value of Sequence counter specifies the number of cycles to complete the algorithm.
QR – contents of multiplier, BR – contents of multiplicand
Combined contents of AC and QR gives the product depending on the operands’ sign.
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Flow chart for booth algorithm
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Division algorithm
Binary division – simpler because the quotient digits are either 0 or 1 and there is no need to estimate how many times the dividend or partial remainder fits into the divisor
Division operation may result in a quotient with an overflow.
Divide overflow flip flop (DVF) is used to detect overflow Divisor – B register, Dividend – A and Q register
If the signs of divisor and dividend are alike, the sign of the quotient is plus. Otherwise it is minus.
Best way to avoid divide overflow is to use floating point data.
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Flowchart for divide operation
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Binary Coded Decimal arithmetic
Computers capable of performing decimal arithmetic must store the decimal data in binary coded form
Each input digit does not exceed 9, the output sum cannot be greater than 9+9+1=19
BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD
A decimal parallel –adder that adds n decimal digits needs n BCD adder stages with the output‐carry from one stage connected to the input‐
carry of the next higher order stage
BCD subtraction – take 9’s or 10’s complement of the subtrahend and adding it to the minuend
9’s complement of a BCD digit can be obtained through a combinational circuit
BCD adder and BCD 9’s complementer = BCD adder/subtractor
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Single stage of a decimal arithmetic unit
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Block diagram of bcd adder
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Data Representation of Positive and negative data
View subtraction process as a process of addition
Steps in forming the booth table
Purposes of AVF and DVF
Divide overflow
BCD representation of decimal data
9’s complement and 10’s complement of decimal data
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