Review
DOI: 10.1002/ijch.201400040
The Mechanism of Operation of Lateral and Vertical
Organic Field Effect Transistors
Ariel J. Ben-Sasson, Michael Greenman, Yohai Roichman, and Nir Tessler*[a]
This review paper is dedicated to the memory of Professor Michael Bendikov
Abstract: In this contribution, we describe the working principles of organic field effect transistors. To place it in context, we start with a brief description of some aspects of
semiconductor field effect transistors. We then describe the
standard structure and properties of laterally aligned field
effect transistors and at the end, touch upon some properties of the newly developed vertically stacked field effect
transistors.
Keywords: molecular electronics · organic devices · polymers · transistors · VOFET
1 Introduction
2. The Field Effect Transistor
Field effect transistors (FETs) are the basis for all electronic circuits and processors, and the ability to create
FETs from organic materials[1–9] raises exciting possibilities for low-cost, disposable electronics such as identification tags and smart barcodes.[10] The molecular nature of
organic semiconductors allows sub-micron structures to
be created at low cost using new soft-lithography[11–12] and
self-assembly techniques,[13–15] in place of expensive conventional optical lithography,[3] and their emissive nature
allows for optical transmission elements to be integrated
directly with electronic circuits[16–20] in a way that is not
possible with (non-emissive) silicon circuitry. However,
although it is easy to argue for the importance of plastic
FETs by drawing comparisons with silicon circuits, one
must be aware that the two material systems (and the corresponding device structures) are very different, and the
behaviour and performance of organic FETs (OFETs) do
not necessarily match those of their silicon counterparts.
In particular, one should not expect plastic circuits to replace silicon as the favoured basis for electronic circuitry,
but one should instead look for new and emerging applications made possible by this new technology. In this contribution, we recognise that we cannot take the physical
models developed for Si-FETs, merely substitute the text
silicon with organic, and expect the existing models to
apply equally well to organic devices.[21] Instead, we will
need to examine the physics of OFETs more-or-less from
scratch to develop a working understanding of this new
technology. We start by covering the basics of MOS-FETs
found in text books[22] and follow with the modifications
and/or emphasis required when dealing with organic transistors. At the end, we also briefly mention a relatively
new device architecture, the vertical FET.[23]
The transistor is a three-terminal component in which the
current flow between two of the terminals – known as the
source and the drain – is controlled by the bias applied to
the third terminal – known as the gate. This is most
simply illustrated by considering the conventional (inorganic) metal-oxide-semiconductor (MOS) FET, found in
almost all modern circuitry. The MOSFET consists of
a conductive substrate which is either negatively (N) or
positively (P) doped, a two electrode region (oppositely
doped), and a metal-oxide double layer. The basic principle of the MOSFET is illustrated in Figure 1,[22] where
Figures 1a and 1b show the device in its Off and On state,
respectively. In order to drive a current between the
source and drain electrodes in the Off state, one has to
apply a voltage (VDS) across three regions: (i) a P-N junc-
Isr. J. Chem. 2014, 54, 568 – 585
Figure 1. Schematic of the principle of operation for the “standard” semiconductor FET.
[a] A. J. Ben-Sasson, M. Greenman, Y. Roichman, N. Tessler
Sara and Moshe Zisapel Nano-Electronic Center
Department of Electrical Engineering
Technion – Israel Institute of Technology
Haifa 32000 (Israel)
e-mail: [email protected]
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
568
Review
Dr. Ariel J. Ben-Sasson holds a B.Sc. in
biomedical eng. (cum laude, 2005),
and an M.Sc. and a Ph.D. in nanoscience (2013) from Technion - Israel
Institute of Technology. His Ph.D. in organic electronics, supervised by Prof.
Nir Tessler and Prof. Gitti Frey, focused
on the development of the novel vertical organic field effect transistor, its
block-copolymer based self-assembly
fabrication methods, and underpinning
physical model. Ariel earned 8 awards,
among which are the SPIE, EMRS,
TSMC and Azrieli Fellowship. He is currently a postdoctoral fellow
at Prof. David Baker’s lab, where he develops protein-engineering
tools aimed at introducing a molecular-design approach for proteins as smart materials.
Michael Greenman is in a direct Ph.D.
program at the electrical engineering
faculty in Technion. Michael’s main research is organic TFT’s, focusing on
vertical organic field effect transistors.
He also finished his bachelor degree in
the electrical engineering faculty in
Technion in 2011, specializing in nanoelectronics and optoelectronics.
Dr. Yohai Roichman received his Ph.D.
from Technion IIT, Electrical Engineering department. In the following years,
Yohai held research positions at Princeton University and New York University.
Yohai’s research focused on charge
transport in organic semiconductors,
statistical properties of transport out of
equilibrium systems, and holographic
optical trapping. Yohai has published
30 peer review papers and 7 patents.
Currently, Yohai is a private investor,
founder of a technological and financial
holding company.
Professor Nir Tessler received his B.Sc.
summa cum laude from the Electrical
Engineering department, Technion
Israel Institute of Technology in 1989.
In 1995, he submitted his D.Sc. dissertation on carrier dynamics in ultrafast
III-V lasers. In 1996, he published the
first optically pumped conjugated polymer laser. After “falling in love” with organic optoelectronics, he strived to
contribute to the understanding that
organics can be used in numerous applications. Nir is currently the head of
the microelectronics and nanoelectronics research centres at the
Technion where he is trying to assist in areas outside his field of expertise.
Isr. J. Chem. 2014, 54, 568 – 585
tion; (ii) an N-doped bulk region; and (iii) an N-P junction. In this case, one of the junctions is always oriented
in the reverse direction to the applied field and hence,
the current flowing through it is based on the negligible
density of minority carriers (holes in N type region),
making its value negligibly small. In the On state, a large
negative bias is applied to the gate electrode. The metallic
gate, the oxide layer and the N-type bulk semiconductor
act in effect as a capacitor, with the gate forming one
plate, the oxide acting as the dielectric spacer, and the
semiconductor forming the other plate. As with any capacitor, if a bias is applied across the plates, opposite and
equal charges will accumulate on the two plates. Hence,
electrons accumulate at the gate and holes accumulate at
the oxide-semiconductor interface. If the bias applied to
the gate is sufficiently high, the interfacial hole density
will be large enough to change the semiconductor from
N- to P-type. In this case, the current flowing through the
reverse-bias diode is enhanced due to the high density of
holes in the N region; namely, current flows between the
two P-type source and drain electrodes through the intermediate P-type layer (the channel).
The basic operation of organic FETs and MOSFETs
are in many ways similar, although there are important
differences that arise from the different device structures
involved. In general, OFETs comprise three parts: (i)
a metal or doped-organic conductor; (ii) an insulator; and
(iii) a p-conjugated semiconductor. Hence, they can be
described as CIp-FETs and two typical CIp-FET structures are shown in Figure 2. Notably, unlike the
MOSFET of Figure 1, there is no P-N junction involved
and the source/drain electrodes are attached directly to
the p-conjugated semiconductor that makes up the channel. Figures 2a and 2b represent two common CIp-FET
architectures, named bottom and top contact configuration, respectively[24] . In the bottom contact configuration,
the source/drain electrodes are in direct contact with the
insulator (and the channel), while in the top contact configuration, the source/drain electrodes are placed on the
other side of the p-conjugated material.
Figure 2. Schematic of an organic transistor based on conductor,
insulator and p-conjugated material (CIp technology).
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
569
Review
Figure 3. Simulated charge density profile for p-channel top contact CIp-transistor VDS = 1. (a) (VGSVT) = 0; (b) (VGSVT) = 1. The figure
shows the p-conjugated layer only, and the position of the source drain and the insulator are schematically shown for a better orientation.
Before going deeply into the operation of CIp-FETs,
we illustrate the effect of applying the gate voltage by
simulating such a device. In Figure 3, we show the charge
density distribution in a top contact CIp-FET for two
gate-source bias values. The simulated structure consists
of a source-drain distance (L) of 1.5 mm, the p-conjugated
layer thickness is 50 nm, and the insulator is 100 nm
thick. Note that at zero gate-source bias, Figure 3a, there
is no charge density connecting the source and drain, thus
the resistance is very high, as is typical of high band-gap,
and undoped, organic materials. Once a gate bias that exceeds a certain threshold value is applied, a high charge
density is created next to the insulator interface (Figure 3b), thus significantly reducing the resistance between
the source and the drain. As a result, charge (current)
flows through a very thin region that it is termed the
“channel”.
2.1 The CIp Capacitor
Figure 4. Schematic comparison between metal-oxide-metal and
metal-oxide-semiconductor capacitors.
It is evident from the discussion above that the process of
capacitive channel formation is critical to FET operation.
The capacitive effect determines the charge density in the
channel and hence the threshold voltage (VT) at which
the conductivity becomes substantial (switch On). To understand the operation of CIp-FETs, we start by considering a simple metal-insulator-metal parallel plate capacitor
of the kind shown in Figure 4a, in which an insulating
layer is sandwiched between two metallic electrodes. In
this case, the entire applied voltage is dropped across the
resistive oxide layer, giving rise to a uniform bulk field of
magnitude Eins = V/dins, with no penetration of the electric
field into either of the electrodes (beyond the so called
skin-depth). The abrupt change of the electric field from
Eins in the insulator to zero at the metal electrodes has its
origins in the formation of vanishingly thin sheets of extremely high charge-density at the surface of the two
electrodes. In the CIp-FET, one electrode is made of
a semiconductor where the penetration of the electric
field, which is charge density dependent, becomes more
significant and hence, the charge occupies a larger region
near the interface. In this case, part of the applied voltage
(termed “threshold voltage”) is dedicated to the formation of the charge layer, thus reducing the voltage that
drops across the insulator and consequently, reducing the
total charge that accumulates at the semiconductor interface (i.e., the effective capacitance is reduced).
In the following, we try to answer the question: what is
the voltage required to achieve conduction between the
source and the drain? Or, what is the threshold voltage
(VT)? Based on Figure 1 (MOS technology),1 it is the
voltage required to invert the type of the interface from
N to P. This leads us to the next question: what actually
happens at the interface? Or, what is this inversion pro-
Isr. J. Chem. 2014, 54, 568 – 585
1
The situation for CIp technology (Figure 2) is different and will be
discussed below.
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
570
Review
cess? To answer this question, in the context of CMOS
technology,i we consider a doped semiconductor being
part of a capacitor. In Figure 5, the dopants are represented by encircled charge signs, thus the left column describes a P-type and the right column an N-type semiconductor, respectively. Before applying a voltage (top of
Figure 5), the semiconductor is electrically neutral where
every dopant atom is compensated by a free charge.
When a negative (positive) bias is applied to N-type (P-
ðEF EFi Þ
ðEFi EF Þ
n ¼ ni e kT ðp ¼ ni e kT Þ. In the case of a metal, the last
(relevant) band is partially filled with electrons (high density) and the Fermi-level lies within the electronic band
(see Figure 6).
Figure 6. Energy band diagram of intrinsic, N-type, and P-type
semiconductors.
Figure 5. The formation of a depletion layer followed by inversion.
type) based capacitor, positive (negative) charge appears
near the interface. At first, it is mainly composed of
dopant atoms that have been stripped of their free electron (hole). By depleting the free charges near the interface, we create a depletion layer. When the voltage is
made larger, we arrive at a point where, very close to the
interface, free holes (electrons) start to accumulate and
create a very thin layer whose type has been inverted to
P-type (N-type); namely, the type of free charges at the
interface is now opposite to what it was at the “no bias”
state.
To invert the type of the material, the Fermi-level at
the interface has to be moved to the other side of EFi
(Figure 6). The voltage shift required for the inversion
2
process is: ðVInvert ¼ q ½EF EFi Þ. However, as shown in
Figure 5, before inversion is created, a depletion layer is
formed. The creation of this space
charge is associated
1 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
with a voltage drop ðVDepletion ¼ Cins 2ee0 qND VInvert Þ[22] that
adds to the inversion voltage. So the threshold voltage
associated with the semiconductor material is only:
VT_Material = VInvert + VDepletion.
Turning now to transistors made using CIp technology
(Figure 2):what is the gate voltage required to achieve
conduction between the source and the drain? Based on
Figure 2, it is the voltage required to populate (charge)
the p-conjugated layer. Typically, a well behaved CIpFET is made using an intrinsic (undoped) p-conjugated
layer2 and the Fermi level lies approximately in the
middle of the HOMO-LUMO gap (EF EFi). Therefore,
following the above discussion, we note that for an undoped p-conjugated material, there is no inversion nor
depletion and if we follow the convention for Si devices
then VT Material p jSi ¼ 0. However, the true meaning of the
threshold voltage is the value beyond which all the applied bias results in capacitive charging Q = (VVT)Cins.
Since the charge density becomes significant only when
the Fermi level is brought close to the respective
1
(HOMO/LUMO) level, we get VTMaterial ffi 2q Eg . We use
the approximate sign, since in amorphous semiconductors
the “band edge” is soft and the effective threshold voltage may be bias dependent (Figure 7).[25]
n
2.1.1 The Role of the Semiconductor Parameters
How does the process of inversion depend on the material parameters? This is commonly answered with the aid
of an energy band diagram (Figure 6), where the position
of the Fermi-level (EF) between the conduction band
edge (EC) and the valence band edge (EV) depicts the
density of electrons and holes in the semiconductor.
For an intrinsic semiconductor, there is an equal density
(ni) of electrons and holes and the Fermi-level lies approximately in the middle of the electronic gap. When
there is an excess charge, then the Fermi-level shifts
up (down) for excess of electrons (holes) and the
charge density, at the low density limit, is given by
Isr. J. Chem. 2014, 54, 568 – 585
2.1.2 The Role of the Device Parameters
In the device, we bring together a semiconductor and
a metal and let them reach equilibrium through the insulating layer3. As we see below, the device structure also
2
3
The case of doped p layer will be discussed later in the text.
Even when the insulator is perfect and there is no charge transfer
through it, the situation of common Fermi-level is achieved once
an external source is applied at zero bias (short-circuit).
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
571
Review
Figure 7. (a) For an intrinsic semiconductor with a sharp band
edge, applying a voltage to the gate will shift the Fermi level towards the band. Once the Fermi level approaches the band edge,
the Fermi level “locks” and any additional voltage goes for charging the channel (cDV). (b) For a disordered semiconductor where
the “band edge” is soft, the Fermi level doesn’t lock and goes into
the LUMO density of states.
makes a contribution to VT. Recall that the Fermi level of
an intrinsic semiconductor lies midway between the
HOMO and the LUMO (Figure 6). The Fermi level of
the semiconductor, as drawn in Figure 8, therefore lies
the semiconductor: in the limit dins = 1, the full potential
1
V ¼ q ðFM FS Þ is dropped across the insulator, whereas
in the limit dins = 0, the full potential is dropped across the
semiconductor. To restore the bands of the semiconductor
(and insulator) to their flat state, one has to apply a com1
pensating external bias of VFB ¼ q ðFM FS Þ4. Namely, to
reach a position where the threshold voltage is dependent
on the material parameters, we have to first apply a
voltage to compensate for the effect of the structure
ðVT Structure ¼ VFB Þ. The total threshold voltage is
ðVT ¼ VT Structure þ VT Material Þ. Sometimes, during the manufacturing process charges get trapped in the insulator
(charged defects), thus affecting the charge balance
across the insulator and consequently, the degree of band
bending and the magnitude of the flat-band voltage[22] .
In the discussion so far, we considered that the only
barrier to current flow is the lack of relevant charge carriers in the channel region. However, generally speaking,
there could also be a barrier at the source metal/p-layer
interface. If such a barrier exists, the device characteristics are distorted, including an enhancement of the apparent threshold voltage.[24]
3. Possible Applications
Figure 8. Band profile of a metal-insulator-semiconductor structure.
below that of the metal contact. In making an electrical
connection between the organic layer and the metal, electrons will therefore flow from the metal to the semiconductor, so as to bring the Fermi-level at the semiconductor up towards the metal Fermi-level; as with the single
layer devices considered in Ref. [22], this creates a built1
in potential of V ¼ q ðFM FS Þ, which tilts the bands of
the insulator and the semiconductor upwards. The width
of the spacer layer determines the potential drop across
Isr. J. Chem. 2014, 54, 568 – 585
It is too early to predict where organic or CIp field effect
transistors will find their main use. It seems to be commonly accepted that they will not replace inorganic FETs
but rather, be used in products where inorganic transistors cannot be used due to their mechanical properties or
cost. Such applications could be:
1. Flexible displays, where the CIp-FET is used to actively switch the pixels of light emitting diodes or liquid
crystals.
2. Smart cards or smart tags, which require a relatively
low density of transistors and flexibility in circuit design.
High-end products may combine plastic circuitry with
plastic displays to provide instant feedback to the user/
customer.
3. Pharmaceutical, where the organic nature of the
device may be used to better couple the device with detection capabilities of chemical or biological moieties.
The required performance will naturally depend on the
application sought, but if logic circuitry is to be used to
perform a slightly complex function, then the operating
voltages will need to be compatible with existing technologies (< 5 V) and the current flowing through a single
transistor will need to exceed several mAs to avoid noise
and related errors.
4
We assume here that F is given in eV.
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
572
Review
4. The Transistor Characteristics
4.1 The Linear Regime
It is important to understand how the source-drain current will depend on the source-gate bias. We start by calculating the current that will flow across the channel, carried by the charge that has been accumulated by the capacitor-effect. Here we assume that the decrease of
charge density along the channel is small and that the
charge density is to a good approximation uniform along
the channel (in the ^z and ŷ directions). If we assume that
the transistor has the dimensions of W and L (see
Figure 1), we can write the formula for the current IDS
that flows between source and drain as:
IDS ¼
#Charge QChannel ðW LÞ
¼
time
ttransit
Figure 9. Schematic of the I-V characteristics in the linear regime.
4.2 The Non-Linear Regime and the Saturation Effect
The transistor is said to operate outside the linear regime
when the main assumption underlying the linear regime
(quasi-uniform charge density across the channel) breaks.
Figure 10 shows the charge distribution across the transis-
ð1Þ
where QChannel is the areal charge density in the channel
and ttransit is the time it takes a charge to move across the
channel between the source and drain electrodes. If we
assume that the electron velocity is characterised by
a constant mobility (m), we can calculate the transit time
as:
ttransit ¼
L
L
L
L2
¼
¼ VDS ¼ mVDS
v mE m
ð2Þ
L
The charge area density (QChannel) can be found from
the capacitor characteristics, assuming that fs (Figure 4)
is
bias independent
and is fixed at its value for VGS = VT
s jVG ¼VT ¼ VInvert . For the undoped p-layer, this is equivalent to the assumption that fs is negligible, since for the
intrinsic layer VInvert = 0.
Qchannel ¼ Cins ðVGS VT Þ
ð3Þ
Finally, we arrive at the expression for the current:
I¼
IDS
Cins ðVGS VT Þ W L
L2
mVDS
)
ð4Þ
W
¼ mCins ðVGS VT ÞVDS
L
One can also derive the device resistivity in its On
state: RON ¼
VDS
IDS
¼
h
W
L
mCins ðVGS VT Þ
i1
and we find it is
a trans-resistor (hence transistor). As Equation (4) represents a linear relation between the current and voltage,
the regime for which it holds is called the “linear regime”
(Figure 9).
Isr. J. Chem. 2014, 54, 568 – 585
Figure 10. Schematic of the charge density across the channel for
different drain voltages (VG = 5, VS = 0) and assuming VT = 0. The
thickness of the yellow line is used to denote the charge density in
the channel. (a) VDS = 0 and the charge density is uniform across
the channel. (b) VDS < (VGSVT) and the charge density only slightly
changes across the channel. (c) VDS = VGS and the charge density
next to the drain contact is zero. (d) VDS > (VGSVT) so that a small
region empty of charge develops near the drain electrode and the
channel length is slightly reduced.
tor channel for fixed gate (+ 5 V) and source (0 V) voltage, with a varying drain (0, 3, 5, + 7 V) voltage (i.e., Pchannel). As long as the bias between gate and source
and between gate and drain are similar, one can assume
the charge density to be relatively uniform across the
channel; namely, for VDS ! VGSVT, the transistor is said
to be in the linear regime. When VDS approaches
ðVGS VT Þ, the formula for the current has to be re-evaluated.
Before formally deriving the transistor I-V curve, let us
examine the effect of VDS, as depicted in Figure 10. The
charge density in the channel is proportional to the potential difference between the channel and the gate (Q =
CV). As was discussed in previous sections, the non-zero
threshold voltage, VT ¼
6 0, is associated with Fermi level
alignment and charge accumulation at V = 0. Therefore,
the actual charge that accumulates at the insulator/organ-
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
573
Review
ic interface is the sum of that found at V = 0 and that induced by the external voltage: Q = CVCVT = C(VVT).
The potential across the channel is set by
two boundary conditions at the source (VS) and
at the drain (VD). As VD approaches VGVT,, the
charge
density
near
the
drain
is
reduced
ðQD ¼ C½VD ðVG VT Þ < C½VS ðVG VT Þ ¼ QS Þ,
thus enhancing the resistivity of the channel. When this
effect takes place, the slope of the I-V curve is reduced
(higher resistivity) and the curve starts to saturate. Once
VD is equal to VGVT, a region empty of the channel type
carriers is formed. When the value of VD crosses VGVT,
the size of this “empty” region is enhanced. Since this
region is “empty” of channel type carriers, its resistivity is
very high and the entire extra potential drops across this
region5 and the potential at the edge of the channel is
pinned at VGVT. Namely, the region where the channel
exists remains with the boundary conditions of VS on one
side and VGVT on the other for any VD that exceeds
VGVT. As the resistance per unit length is high, the
length of this empty region can be very small and still
provide the required resistivity to accommodate the
excess potential drop. Since once VD exceeds VGVT, the
boundary conditions of the channel region are fixed and
the current that will flow across the channel will become
independent of VD. The resulting curve will be like that
shown in Figure 11.
Qchannel ðyÞ ¼ Cins ½ðVG VðyÞÞ VT ð5Þ
where V(y) is the electrochemical potential in the channel
at point y and ½VG ðVðyÞ þ VT Þ is the voltage that
drops across the insulator. Before proceeding, we show
that even in this case, where a charge gradient along the
channel is inherent, the current in a conventional transistor is mainly drift current. To do so, we write the expressions for the drift and diffusion currents:
mEN ¼ m
D
Vðy2 Þ Vðm1 Þ Nðm1 Þ þ Nðm2 Þ
y1 y2
2
@N
Nðm1 Þ þ Nðm2 Þ
¼D
@y
y1 y2
Inserting Equation (5):
mEN ¼ m
D
Vðy1 Þ Vðm2 Þ
Vðm1 Þ þ Vðm2 Þ
Cins q1 VG VT
y1 y2
2
@N kT
Vðm1 Þ Vðm2 Þ
¼
mCins q1
@y
q
y1 y2
And finally the ratio between the two currents is:
mEN V VðyÞ V G
T
@N kT
D @y q
ð6Þ
Equation (6) shows that as long as the voltage drop
across the insulator is much larger than kT/q, the current
is mainly drift current and hence we can write:
IDS ¼ IDS ðyÞ ¼ W mQchannel ðyÞEðyÞ ¼ W mQchannel ðyÞ
dVðyÞ
dy
ð7Þ
Integrating across the channel, we find:
ZL
Figure 11. N-type transistor IDSVDS characteristics for several
values of VGS as derived by Equations (10) and (12). Here, W/L =
600, Cins = 50 nFcm2, m = 104 cm2 V1 s1 and VT = 1 V. The dashed
line depicts the transition from linear to saturation regimes.
To derive the I-V curve formally, we recall that the
charge is not uniform across the channel and in reality
decreases rapidly from the start to the end of the channel
(see Figure 3). Accordingly, we write Qchannel = Qchannel(y)
and its value is:
5
In principle, the region that is empty of channel-type carriers
(holes or electrons) may be filled with the other type of carrier
(electron or hole). We assume that the conductivity associated
with this other-type carrier is negligibly small (low mobility, contact limited).
Isr. J. Chem. 2014, 54, 568 – 585
IDS dy ¼
0
ZL
W mQchannel ðyÞ
dVðyÞ
dy
dy
ð8Þ
0
If VDS ðVGS VT Þ (Figures 10a to 10c), we can replace the integration between y = 0 and y = L with an integration between V(0) = 0 and V(L) = VD.
ZL W mQchannel ðyÞ
R
dVðyÞ
dy
dy ¼
ð9Þ
VDS
0
W mCins ½ðVGS V Þ VT dV
0
As the current is constant:
V
V 2 DS
IDS L ¼ W mCns ðVGS VT ÞV 2 0
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
574
Review
and so finally, for VGS in accumulation regime and
VDS ðVGS VT Þ:
IDS
2 W
VDS
¼
mCns ðVGS VT ÞVDS 2
L
ð10Þ
In the above, we have assumed that: (a) the charges in
the channel are electrons (voltages taken as positive); (b)
there is charge in the channel anywhere between y = 0
and y = L; and (c) VS and VD can be used as the two
boundary conditions for the channel (see Figure 10). Assumption (c) is true as long as the contacts are ideal and
no (or negligible) voltage drops across them. Assumption
(a) is true as long as VDS ðVGS VT Þ; however, when
the magnitude of VDS exceeds that of ðVGS VT Þ,
a region empty of charge is created near the drain electrode (see Figure 10). In this case, Equation (8) has to be
rewritten:
ZLEFF
IDS dy ¼
0
ZLEFF
W mQchannel ðyÞ
dVðyÞ
dy where LEFF L
dy
0
ð11Þ
W mQchannel ðyÞ
dVðyÞ
dy ¼
dy
0
Z
5. Extracting Material Parameters of CIp-FET
5.1 Field Effect Mobility
If the current flow through a transistor is only affected by
the transistor channel, then its I-V characteristics should
follow Equations (10) and (12); namely:
m¼
8
>
< WC ðV
L
>
:
IDS
V2
DS
GS VT ÞVDS 2
IDS SAT
W
2
L Cins ½VG VT Linear regime
ð13Þ
Saturation regime
Sometimes, it is useful to use the derivative of the
above equations. For example, in the linear regime:
@
@
W
V2
IDS ¼
mCins ðVGS VT ÞVDS DS
2
@VGS
@VGS L
ð14Þ
Applying the derivation:
ð15Þ
In cases where the mobility is independent of the gate
bias (or charge density), Equation (15) reduces to:
VGS VT
W mCins ½ðVGS V Þ VT dV
0
m¼
SAT
W
¼
mCins ½VGS VT 2
2LEFF
ð12Þ
for VGS in accumulation regime and VDS ðVGS VT Þ.
Since the region that is empty of charge has high resistivity it can accommodate relatively high voltage across
a short distance. In typical transistors, this region
ðL LEFF Þ is small compared to the geometrical channel
length (L) and one can approximate LEFF as ðLEFF ffi LÞ.
This approximation breaks for short-channel transistors
(as will be briefly discussed later).
Finally, the FET that we have discussed above is extensively used in electrical circuits and when it is placed in
such a circuit design-sheet it is drawn using the symbol
shown in Figure 12.
Isr. J. Chem. 2014, 54, 568 – 585
@
@VGS DS
W
L
and finally,
IDS
ins
2
@
@
W
VDS
I ¼
C ðVGS VT ÞVDS 2
@VGS DS @VGS L ins
W
þm
C V
L ins DS
Equation (9) turns into
ZLEFF
Figure 12. The electrical symbol describing N- and P-channel FETs.
I
Cins VDS
ð16Þ
and the mobility is proportional to the slope of the curve
in Figure 13 in the regime where it is linear. The advantage of Equation (6) is that it is independent of VT and
hence is not prone to errors in the threshold voltage extraction; however, the first term in Equation (15) is often
non-negligible in amorphous organic materials and the
use of Equation (6) will give rise to artificial peaks in the
mobility versus gate bias curve.
5.2 Background Doping
The above discussion assumes that the p-conjugated layer
is undoped and hence, its conductivity is zero unless
charged (populated) by the applied gate-source bias. In
some cases, there exists a doping density in the p-conjugated layer, be it intentional or unintentional.[26–28] In
most cases, the doping would be of the same type as the
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
575
Review
Figure 13. Calculated (using Equations (10) and (12)) IDSVGS characteristics of N-channel transistor for several values of VDS. Here, W/
L = 600, Cins = 50 nFcm2, m = 104 cm2 V1 s1 and VT = 1 V.
channel, although recently, inversion type FETs have also
been reported.[28] In the most common case, there would
be two effects due to doping: (a) the Fermi level would
shift (typically maximum 1 V) and the flat band voltage
(VFB) would shift accordingly; (b) at high enough
doping, a finite conductivity between the source and
drain electrodes appears and is associated with the bulk
conductivity of the p-conjugated layer. The bulk conductivity is electrically in parallel with the channel conductivity.
IDS
Bulk
¼ qND
W
md V
L p DS
ð17Þ
Figure 14. Calculated (using Equations (10), (12) and (24)) IDSVGS
characteristics of doped N-channel transistor VDS = 0.1 V. Here, ND =
0, 1 1016 cm3, 3 1016 cm3, 1 1017 cm3 ; W/L = 600; m =
104 cm2 V1 s1; VT = 1 V; eins = ep = 3; dins = dp = 100 nm. (a) Linear
scale. (b) log10(y) scale.
The reduced conductivity of the bulk is associated with
the formation of a depletion layer similar to that shown
in Figure 4, reducing the conducting layer thickness to
(dpWdep). Following the notation in Figure 4, we move
to formally derive the bulk current. Defining
V ¼ ðVGS VT Þ, we write:
1
ep
1
E d þ E W
V ¼ Eins dins þ Emax Wdep ¼ eins max ns 2 max dep
2
ð18Þ
Solving for Emax :
Emax ¼ V
ep
eins
1
dins þ 2 Wdep
ð19Þ
Since the electric field decreases linearly across Wdep :
Here ND is the bulk doping density, dp is the p-conjugated layer thickness and the rest have their usual meanqND
ing. If we assume that the transistor shown in Figure 13
ð20Þ
W
Emax ¼
ep e0 dep
16
3
has now a doping density of ND = 10 cm , then it characteristics are as shown in Figure 14.
Using Equations (19) and (20):
We note that for VGS > VT (VGS > 1 V), the curves in
Figure 14a are similar to those in Figure 13, but are shifte e
V
e e
p 0
Wdep ¼ Emax p 0 ¼ ed upward by IDS Bulk which, according to Equation (7), is
ð21Þ
ep
1
qND
qN
D
independent of VGS (VDS = 0.1 V) in this range. For
eins dins þ 2 Wdep
(VGSVT) < 0, the current is decreasing, indicating the reduction in the bulk-related current (as the channel is in
Rearranging the terms, we arrive at:
Off state for all VGS < VT). Examining the same data on
a semi-log scale, Figure 14b, it seems as if the threshold
1 2
e
e e
ð22Þ
W þ p d W þV p 0 ¼0
voltage is shifting to negative values. However, at high
qND
2 dep eins ins dep
enough gate voltage, the curves are almost identical, suggesting a constant threshold voltage. Since, in the preswith the only physical solution being:
ence of doping, the current-voltage
8
ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
r
characteristics at the low current end
2
>
ep
e e
< ep d þ
do not follow Equation (2), the voltd
2ðVGS VT Þ qNp D0 ðVGS VT Þ < 0
ins
ins
eins
eins
ð23Þ
age extracted from this range is some- Wdep ¼ >
:
ðVGS VT Þ 0
0
times called the switch-on voltage
(VSO), while the threshold voltage
Above, we used V = VGSVT. If we assume that VDS is
(VT) would be reserved for the value
extracted from the range that can be
relatively small, so that we can assume ðVGS VT Þ, and
hence Wdep, to be uniform across the device:
fitted to Equation (0).
Isr. J. Chem. 2014, 54, 568 – 585
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
576
Review
IDS
Bulk
¼ qND
W m dp Wdep VDS
L
ð24Þ
We observe that the current drops to zero once the depletion layer extends across the entire p-conjugated layer.
If we know the voltage at which it happens, we can use
Equations (18) and (20) to derive the dopant density
(Wdep = dp):
2Vpinch e0
ND ¼ 2
d
2d d
q epp þ epinsins
For example, based on
Figure 14, we find for the highest doping Vpinch ¼ VGS IDS ¼0 VT ¼ 9V and hence
ND ¼
2 9 8:85 1014
¼ 9:94 1016 ½cm3 ð100107 Þ
2100107 100107
19
1:6 10
þ
3
3
A more comprehensive treatment of doped devices
that includes the effect of non-uniform Wdep can be found
in Ref. [26].
To conclude this section, we plot the same calculation
as in Figure 14, but let the mobility be charge density dependent ðm / N 0:5 Þ so as to mimic some of the disordered
material based FETs.[29–30] We note that in this case, there
is a kink in the curves that is reminiscent of the threshold
voltage (Figure 15).
Figure 16. Simulated charge density (2D simulation) and potential
at the middle of the channel for p-channel transistor and a bias of
VDS = (VGSVT) = 1. XChannel denotes the effective channel depth (~
7 nm here).
expressions, as for each point along the y-axis
there exists a different effective capacitance and
CIns ) CIns EFF ¼ CIns EFF ðVGS ; yÞ.
In the present text, we try instead to examine the validity of our assumption and give the reader a sense for the
associated effect on the device performance. To derive an
expression for the charge profile perpendicular to the insulator, we start with the basic current continuity and
Poisson equations:
Jh ¼ qpmh E q
@
@
@
ðD pÞ ¼ qpmh E qDh p qp Dh
@x h
@x
@x
ð25Þ
At steady-state, there is no current flow in the x direc@
@
tion and if we assume Dh @x p p @x Dh, we arrive at:
Jh ¼ qpmh E qDh
Figure 15. Calculated (using Equations (10), (12) and (24)) IDSVGS
characteristics of doped N-channel transistor VDS = 0.1 V. Here, ND =
0, 1 1016 cm3, 3 1016 cm3, 1 1017 cm3 ; W/L = 600; m / N0.5 ;
VT = 1 V; eins = ep = 3; dins = dp = 100 nm. (a) Linear scale. (b) log10(y)
scale.
@p
¼0
@x
ð26Þ
and the boundary conditions for the electric field are:
Ejx¼0 ¼
ep
e ðV VT Þ VðyÞ
E p G
; Ejx¼dp ¼ 0
eins ins eins
dins
ð27Þ
Using (26) and the Poisson equation, we can derive:
6. Advanced Topics
E
6.1 The Channel Depth
In the development of the I-V characteristics above, we
did not consider the charge density profile along the xaxis (Figure 16). This was justified by the assumption we
made for Equation (3) that fs (see Figure 4) is constant
once the gate voltage is above threshold. In other words,
we neglected any changes in the charge profile and the
associated change in the voltage drop across it. Adding
this effect rigorously will significantly complicate the
Isr. J. Chem. 2014, 54, 568 – 585
@E Dh @ 2 E
¼
mh @x2
@x
ð28Þ
or
1 @ 2 Dh @ @E
E ¼
mh @x @x
2 @x
ð29Þ
Integrating over x once (assuming D/m to be a slowly
varying function of x):
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
577
Review
mh 2
@E
E þC ¼
2Dh
@x
ð30Þ
where C is a constant to be determined by the boundary
conditions. Integrating between point x to the air interface (dp) we arrive at:
Zdp
0
@x ¼
Z0
E
x
mh
2Dh
@E0
E02 þ C
then use Equation (34) to calculate the charge density
profile (T = 300 K).
Examining Figure 17, we note that at low voltage drop
across the insulator, the channel is rather extended and
the charge density extends a considerable way into the pconjugated layer. The functional form of the density dis-
ð31Þ
and if D/m is approximately constant across the layer:
"rffiffiffiffiffiffiffiffiffi
#
rffiffiffiffiffiffiffiffiffiffiffiffi
2CDh
Cmh
tan
E¼
ðx LÞ
mh
2Dh
ð32Þ
This electric field creates “band” bending across the pconjugated layer that is directly derived from the existence of charge at the channel. The bending across the
entire layer is:
DVchannel ¼ ZL
"rffiffiffiffiffiffiffiffiffi
#
rffiffiffiffiffiffiffiffiffiffiffiffi ZL
2CDh
Cmh
Edx ¼ tan
ðx LÞ
mh
2Dh
0
"rffiffiffiffiffiffiffiffiffi #!
2Dh
Cmh
log cos
dx ¼ L
mh
2Dh
0
ð33Þ
and the charge density across the p-conjugated layer is:
e e @E Cep e0
¼
p¼ p 0
q @x
q
"rffiffiffiffiffiffiffiffiffi
#2 !
Cmh
tan
ðx LÞ þ1
2Dh
ð34Þ
where C is to be determined from:
eins
E ¼ Ejx¼0 ¼
ep ins
"rffiffiffiffiffiffiffiffiffi
#
rffiffiffiffiffiffiffiffiffiffiffiffi
2CDh
Cmh
tan
ð0 LÞ
mh
2Dh
ð35Þ
To illustrate the use of Equations (32) to (35), we calculated the charge density profile for two different electric fields at the insulator (E0). The first one was chosen
to be close to the conditions used for Figure 16 and the
second for a higher applied voltage. We first use Equation (35) to find the integration constant C (Table 1) and
Table 1. The parameters used for Figure 17.
Eins [Vcm1]
4
5 · 10
3 · 105
dp [cm]
7
50·10
50·107
Isr. J. Chem. 2014, 54, 568 – 585
C
DVchannel [V]
3.5457e + 009
4.7943e + 009
0.069
0.153
Figure 17. Calculated charge density profile for two electric fields
at the insulator (different VGS). The right axis is for E0 = 5 104 V cm1 and the left axis for E0 = 3 105 V cm1 (ep = 3). The inset
shows the effect of D/m being a (slowly-varying) function of the
charge density (E0 = 5 104 V cm1). The full line in the inset was
calculated using D/m = 2 kT/q (see Ref. [31]) and only the first
10 nm are shown.
tribution tells us that for a thinner p-conjugated layer, the
effect will be more pronounced. Also, at higher applied
bias, the channel becomes more confined as most of the
added charge accumulates near the insulator interface. Finally, the inset shows the effect of the enhanced Einsteinrelation as discussed in Refs. [21, 32–33], and demonstrates that for higher values of D/m, the charge is more
spread across the polymer. As the low field result suggests, for a relatively thin layer, the channel depth would
be dictated by the film thickness and the charge density
would change significantly less between the insulator and
air interface. Under such conditions, one can utilise
Kelvin probe techniques to probe the channel properties
and extract the generalised Einstein relation or the density of states.[34–35]
To complete the picture, we mention that it has been
shown that organic amorphous (disordered) semiconductors are degenerate at all practical densities[31] and hence:
D
kT
m ¼ h q with h being a function of the charge density[31–32] . For example, using the calculation shown in the
inset to Figure 17 (h = 2), DVChannel ffi 0:25 eV. Also,
a change in the value of the band bending (DVChannel) is
an indication that the chemical potential (quasi Fermi
level, EF) in the p-conjugated layer is also shifting, thus
modifying the effective threshold voltage (this is on top
of the effect of the soft “band edge” discussed previously)[25] .
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
578
Review
Next we move to also evaluate a simple expression for
the effective channel depth. If we define XChannel as the
depth at which the charge density drops to its e1 value:
px1
mx1
Dx
e ¼
¼ exp Df12 ! Df12 ¼ 1
px2
Dx1
mx1
1
ð36Þ
If the decay was exponential with x, then XChannel would
accommodate ~ 60 % of the charge, but in practice it is
usually less; namely, the average electric field would be
~ 80 % of its maximum value (or more) and hence:
0:8
eins
E
E X
¼
ep ins Channel m
Figure 18. Charge density (a) and potential (b) distribution for
a top contact CIp-FET shortly after switching the gate voltage from
0 to 5 V (VDS = 3 V).
ð37Þ
and
XChannel dins
ep kT
h
VG VðyÞ eins q
ð38Þ
Using common parameters as dins = 100e7cm,
VGSVT = 1V; VDS = 1V we find that near the source
ðVG VðyÞ ¼ VGS Þ XChannel = 2.6 nm h and at the centre
of the channel ðVG VðyÞ VT ffi 0:5V Þ XChannel = 5.2 nm
h. Note that the approximate expression of Equation (37) is in good agreement with the numerical simulation results shown in Figure 16. Namely, in organic transistors where the molecular distance is about 0.5 nm, the
channel will extend over several monolayers, especially at
low gate bias. We reiterate that a more precise expression
for XChannel can be derived directly from Equation (34).
Figure 19. Equivalent circuit description of the FET immediately
after switching the gate voltage.
through the charged regions underneath the contacts. A
nave estimate of the time it would take to build the
channel would be to consider the time it would take for
a charge to drift the channel length under the applied
source drain bias:
6.2 Switch On (Transient Dynamics)
FETs are largely used as a switching element in a circuit,
the speed of which is determined by the time it takes to
switch the transistor On (and Off). Therefore, it is essential that we have some understanding of the mechanism
by which the transistor channel is built as a function of
time[36–38] . We also take this opportunity to look more
into the operation of the top contact CIp-FET structure
(see Figure 2). Figure 18 shows the charge density and potential distribution at about 100 ns after the gate voltage
has been switched from VG = 0 to VG = 5 V, while keeping the source and drain voltage constant at VS = 0 and
VD = 3 V, respectively.
At first, the source and drain are isolated from each
other (as the channel that will connect them has not been
formed yet). At this short time, we mainly see the capacitive nature of the FET structure that was discussed in section 2.1. Namely, the region under the drain and source
contacts is charged and the voltage applied to the source
and drain is projected onto the insulator interface. This
situation is illustrated in Figure 19.
After the source and drain have been projected onto
the insulator interface, the channel will start to form
Isr. J. Chem. 2014, 54, 568 – 585
Dt ¼
L
L2
ð5 104 Þ2
¼ 16:66ms
¼
¼
mE mVDS 5 103 3
ð39Þ
However, examining Figure 18b, we note that at this initial stage, the voltage actually drops across a much shorter distance and only across the part of the channel that
has been filled (also see Equation (5)). In Figure 20, we
plot the simulated charge build up at the channel, which
is similar6 in shape to the potential across it (P CinsV).
We note that the channel is built within less than 5 ms,
being less than a third of the nave value of 16.66 ms calculated above. The relation between the charge density
(P) and the potential (V) has also been used in a time-dependent Kelvin-probe measurement to experimentally
monitor the channel build-up[37] .
As P CinsV, we also note that the drain-source bias
drops across the entire channel length only after the
entire channel has been formed. The equivalent circuit
describing the channel build up is as shown in Figure 21.
6
The deviation is related to the potential drop across the channel
itself as described in Equation (33).
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
579
Review
where DL is the distance separating two elements (typically, dividing the channel into 10 elements is enough to
capture the distributed nature of the charge build up).
To solve the circuit in Figure 21, we must define the
boundary conditions:
(
V1 ¼ VS ; Vnþ1 ¼ VD ;
for i6¼1; n þ 1 Vi jt¼0 ¼ 0
Figure 20. Charge density distribution at the channel as a function
of time (m = 5 103 cm2 V1 s1) after switch On.
To calculate the dynamics of the system, we rely on the
capacitor characteristics, which state that the current en
dV
tering (charging) the capacitor is Ii ¼ c dt i and on
Kirchhoffs law, which states Ii ¼ IRi1 IRi , to give:
dVi
1
Vi1 Vi Vi Viþ1
¼
dt
Ri1
Ri
Cins W DL
ð42Þ
If m is field and density independent and Vi are all positive, we arrive at an expression similar to the continuous
form[37]:
dVi
m 2
2
V 2Vi2 þ Viþ1
¼
dt
2DL2 i1
Figure 21. The equivalent distributed circuit describing the channel build up.
In Figure 21, RS and RD are the contact resistances,
which would be negligible in a well-behaved FET. Ri,i + 1 is
the serial resistance associated with the current that flows
through, and fills up, the channel. The charge density at
each node is calculated using the voltage dropping across
the gate insulator at the position of the node (remember
that a minimum voltage drop of VT is required to bring
the Fermi level close enough to the transport band and
initiate charging):
(C
pi ¼
ins ½ðVi VG ÞVT q
ni dp
½ðVi VG Þ VT > 0
else
½cm2 ð40Þ
Here, ni times dp represents the 2D residual charge
density in the film that is not due to any bias (since we assumed an intrinsic semiconductor, we use ni here). Equation (40) is written assuming a P-channel and a similar expression can be written for the N-channel where the applied bias has the opposite sign. The resistance, Ri,i + 1, is
derived from the conductivity using the average charge
density of the nodes at its two ends:
Ri;iþ1 ¼
DL
1
½W
W qm p1 þp2 iþ1
Isr. J. Chem. 2014, 54, 568 – 585
ð41Þ
ð43Þ
and finally, the transient currents take the form of:
8
2 ðtÞ
< IS ðtÞ ¼ VS V
R1
ð44Þ
: I ðtÞ ¼ VD Vn ðtÞ
D
Rn
To illustrate the use of Equations (41) to (44), we have
calculated the transient current measured at the source
using parameters similar to those used in the 2D numerical simulation that resulted in Figure 20. The solid line is
calculated for VGS = VDS = 5 V and the dashed line for
VDS = 3 V. We note that the two curves are identical but
for the last microseconds. This is expected, since at early
times the drain voltage has no effect on the charge density near the source contact (see Figure 20). Examining
Figure 20, we note that the charge distribution near the
drain affects the source only at about t = 3 ms, which is in
very good agreement with the point at which the two
curves in Figure 22 start to deviate. Namely, Equations (41) to (44) are a reasonably good approximation
for the physical picture studied here and experimentally
measured in Ref. [38]. As Equation (44) suggests, the
completion of channel charging could also be detected if
one measures the source and drain currents separately
and looks for the point in time where the two become
equal.[39]
The above equations suggest that the transistor switch
On characteristics are rather universal and only depend
on the channel length and the insulator capacitance.
However, there is a hidden dependence which may make
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
580
Review
Figure 22. Calculated (Equation (44)) transient current for a gate
voltage step between 0 and 5 V. The solid line is calculated for
VDS = 5 V and the dashed line for VDS = 3 V.
the transient curve material dependent. Since the mobility may be charge density dependent,[30,40–42] and this dependence varies with the morphology of the p-conjugated
layer, the functional form of this transient curve is no
longer necessarily universal in shape.
any effect in the semiconductor, due to the shielding of
the gate field by the source electrode. In the architecture
of Ma and coworkers, this problem was circumvented by
using an ultrathin metal layer for the source in combination with a super-capacitor, enabling very high fields at
the metal interface. Another method to overcome the
source shielding was developed by creating a perforated
(patterned) electrode[48,51] such that the gate-field could
penetrate through the holes in the conductor layer and
thus alleviate the need for a super-capacitor. An even
simpler design of the electrode was realised more recently
by the use of a carbon nanotube mesh.[20,52–54] While the
use of nanotubes offers a much simpler process, the use
of a perforated metal layer offers better control over the
electrode’s properties[15] and render it suitable for the detailed modelling[55–56] that could be used to enhance its
performance[57–58] and open the way to designs based on
semi-standard lithography.[59]
While publications on OFETs are numerous, vertical
organic FET (VOFET) research is quite new and the
number of publications following the 2004 paper is shown
in Figure 24. We can conclude that the volume of re-
7. Other Structures
7.1 The Vertical Field Effect Transistor
Field effect transistors based on amorphous semiconductors and especially on poorly crystalline organic materials
are attractive due to their low cost and their potential for
large area electronic device manufacturing via printing
methodologies. An inherent disadvantage of several organic semiconductors is their low carrier mobility when
compared to crystalline materials, which in turn may require different device architectures to achieve certain performance goals. In this context, several types of vertical
field-effect transistors (VFETs)[43–46] have been gaining interest in the field of organic electronics[23,47–48] . For the
current discussion, two relevant structures were invented
in 2003[49] and 2006.[50] The essence of the device structure
is described in the paper by Ma et al.[23] and is shown in
Figure 23. This architecture consists of all the layers
stacked on top of each other in a sequence that is different to the static induction transistor case.[43, 47]
Placing a metal layer between the gate/gate oxide and
the semiconductor makes it close to impossible to induce
Figure 24. VOFET publications since 2004. The list includes publications from the following years: 2004,[23] 2007,[60–61] 2008,[52,62]
2009,[15] 2010,[54,63–64] 2011,[20,55–56,65–67] 2012,[53,57–58,68–69] and
2013.[39,59,70–73]
search done worldwide so far is very limited compared to
the VOFETs practical potential – although it is clearly
on the rise. We expect very soon that a number of research efforts will come to maturation, which will further
extend the versatility of this platform.
7.1.1 Mechanisms of Operation – The Schottky Based Transistor
Figure 23. (a) The vertical structure invented by Yang and Ma[49]
that consisted of a layer sequence of gate electrode, gate insulator,
ultra-thin source electrode, semiconductor, drain electrode. (b) The
modified vertical structure,[48, 50] where the ultra-thin source electrode was replaced by a perforated one.
Isr. J. Chem. 2014, 54, 568 – 585
Figure 25 shows a 3D illustration of both lateral (a) and
vertical (b) Metal-Oxide-Semiconductor (MOS)-OFETs.
Both designs share the same functional layers: gate, gate
dielectric, source, semiconductor, and drain. While in lateral devices the channel length L – perhaps the most important structural parameter – is determined by lithography processes, in the vertical design, it is simply determined by the semiconductor layer thickness. Hence, L
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
581
Review
Figure 25. Illustration of MOS-OFETs, the labels S, G, and D indicate the source, gate, and drain electrodes, respectively. Blue and
green regions indicate the insulating layer and the semiconductor
layer, respectively. Electrodes are indicated by yellow and gray colours. (a) Lateral transistor with bottom gate and bottom contacts
(BGBC) configuration. (b) Patterned source VOFET architecture. (c)
VOFET cross section
can be easily downscaled to a few tens of nanometres,
counterbalancing the low mobility of organic semiconductors and doing away with complex lithography processes.[52,57]
As mentioned in the previous section, for the gate field
to affect the transistor, the natural shielding of the source
electrode should be overcome. In the structure proposed
by Ma and Yang,[23,49] the electrode is made very thin, and
on top of that, the insulator contains mobile ions such
that the gate capacitor acts as a super capacitor with all
the gate bias falling on the electrode interface. In the
structure proposed by Ben-Sasson et al.,[15,48,50] the electrode is non-continuous or perforated. In the following,
we use Figure 26 to explain the basics of the patterned
source VFET. Figure 26a shows again the schematic of
the transistor structure in which the patterned electrode
is presented as having circular holes. In Figure 26b, we
zoom on one of the holes (perforations) and show the
region into which charges will flow, thus defining a basic
unit of the vertical FET. In Figure 26c and Figure 26d, we
show a cross section of a single hole and the source metal
surrounding it. Figure 26c shows that if we dont use the
gate bias to turn on the device (VG < VT), then the device
acts like a metal-semiconductor-metal Schottky diode and
the Off current is kept low by making sure that the barrier for injection is high. This sub-figure also defines two
important structural parameters: the perforation width/diameter (D) and the thickness of the source electrode (hs).
To understand the VFET operation in the On state, we
turn to Figure 26d. Let us first ignore the upper part and
the existence of a drain electrode. We observe a gate dielectric, where there is the gate electrode on one side and
on the other side, it looks as if there are two electrodes.
Namely, the structure looks like a bottom contact lateral
field effect transistor (see Figure 2). Due to the high injection barrier, this is a Schottky type thin film transistor[22] where, by applying a gate field, a channel can be
created.
Once a “channel” is formed in the perforation (hole),
charges accumulate close to the insulator interface. This
charge density can be high enough to so that the Fermi
level in the channel is close to the relevant transport
band. In this case, we can consider the channel of the
Isr. J. Chem. 2014, 54, 568 – 585
Figure 26. Illustration of the Patterned Electrode-Semiconductor
Schottky Barrier-based VOFET operational mechanisms. (a) VOFET
structure functional elements are spatially defined by the perforation regions in the Patterned Electrode (PE). (b) Formation of the
virtual contact on top of the insulating layer inside the perforations. The current regimes are shown on the cross section of
a single perforation. (c) Off current which flows from the top of the
source electrode due to drain-source bias. (d) On current flows
from the virtual contact, that was formed by the gate, to the drain
electrode.
“lateral transistor” as a virtual contact for the vertical
transistor.[55–56] However, it is not clear how charges that
are pulled towards the insulator by the gate field can be
considered as an injection contact for the channel that
needs to form in the vertical direction. This is resolved if
we recall Figure 16 and Figure 17, which show that due to
the presence of diffusion, there is a tail that extends away
from the insulator interface. By applying a drain voltage,
a field is created between the source and drain and it
pulls the charges, which diffused away from the insulator,
to create a drift current in the vertically formed channel.[55–56] This is depicted in Figure 27, which shows a 2D
Figure 27. Charge concentration distribution, logarithmic scaled,
for a device with structural parameters of D = 60 nm, hd = 50 nm,
hs = 6 nm, fb0 = 0.6 eV and L = 100 nm, and biasing conditions: VG =
5 V, VS = 0 V, VD = 2 V.
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
582
Review
numerical simulation result of the charge density distribution for a VFET in the On state.
As Figure 27 shows, the charge density decays exponentially away from the gate insulator up to a point where it
becomes constant. The exponential decay indicates the
region where diffusion dominates (see also Figure 16 and
Figure 17). The almost constant density region (the vertical channel) is governed by drift current. This indicates
that the closer to the insulator the drain field can start
pulling charges, the higher the current would be or the
better the virtual contact would be. For this to be effective, we need the electric field induced by the drain to
reach the bottom of the perforation. This is hampered by
the presence of the source electrode surrounding the virtual contact since the field lines would tend to terminate
at the source metal electrode. This is where the aspect
D
ratio of the hole ðhS Þ becomes important.[57] If this aspect
ratio is not large enough, then the field is not able to
reach inside and pull at a high enough charge density.
This effect is shown in Figure 28a through a simulation of
devices with varying source electrode thickness and in
Figure 28b where two otherwise identical VOFETs were
fabricated using source metal layers of 7 nm and 13 nm.
show[55–56] that when the gate is unbiased, the current regimes take the form of a Schottky diode being limited by
injection from the source to the semiconductor (Equation (45)). On the other hand, when the gate is fully
biased, we assume that the patterned source electrode
perforations are saturated with charge carriers, and hence
these regions act similar to an ohmic contact. As a result,
in this situation the current regime would be similar to
that found in a space charge limited (SCL) diode (Equation (46)). The full details of Equations (45) and (46) can
be found in Refs. [55–57]; note that the fill factor (FF)
parameter, a parameter we added here to both equations,
which is the patterned electrode fill factor (the ratio between the electrode metallic area and perforations area),
is a very simplified model, shown to underestimate the
importance of the perforations aspect ratio.
JOff
q
¼ qmn N0 exp kT
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi!!
q VDS
b0 4pe0 eLOff
9
V2
FF
JOn ¼ e0 emn DS
8
L3
Figure 28. (a) Simulated transfer characteristics of devices with
varying source electrode thickness (hs) values.[55] Inset: On/Off ratio
vs. source electrode thickness. (b) Measured transfer characteristics
of N-type VOFETs having source electrode thicknesses of 7 nm
(square symbols) and 13 nm (round symbols).[57]
Using Figure 26d, we described the creation of the virtual electrode as a creation of a channel in a bottom contact lateral FET. Kleemann et al. have shown that by replacing the bottom contact configuration with a top contact one (i.e., inserting a semiconductor layer between
the source and insulator layers),[59] excellent device performance can be achieved.
7.1.2 VOFET Analytical Description – a FET or a Diode?
Since the device operation is governed by many structural
and physical details, an analytical description can only be
applied to a simplified model. Under this model, the
device behaves similar to a diode and the gates role is to
change the characteristics of one of the diode electrodes;
in our case, the source electrode. We were able to
Isr. J. Chem. 2014, 54, 568 – 585
ð45Þ
VDS
ð1 FFÞ
LOff
ð46Þ
This simplified analytical description yields a number
of insights:
On/Off current ratio is a strong function of the Schottky barrier height, unlike in lateral OFETs where contacts
are ideally ohmic;
On/Off ratio increases as channel length decreases, an
opposite trend to the one found in short channel length
OFETs;
Given a specific channel length, the applied drain bias
is determined for the maximization of On/Off performance.
Based on data fitting to Equations (45) and (46), two
important parameters can be extracted. The first is the
potential barrier between the source and the semiconductor, denoted in Equation (45) as fb0. The second is the
bulk materials charge carrier mobility, denoted in Equation (46) as m.
7.1.3 Vertical FETs as Efficient Switching Elements
As a result of the vertical OFETs short channel length, it
can drive high current densities, operate at low-power
consumption, and at high-frequency, as shown in
Figure 29 ((a) and (d)), making it an ideal candidate, for
example, to drive active matrix OLED pixels. A set of results produced in this work indicate that this device is
also a potentially ideal candidate for low mobility semiconductor-based logic circuits. Firstly, the device transfer
characteristics (IDSVGS) shown in Figure 29a demonstrate an On/Off current ratio exceeding 104. Our study
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
583
Review
Figure 29. Brief overview of the vertical transistor performance. (a) Transfer characteristics IDVGS demonstrate On/Off higher than 104 implemented using metallic nanowires. Similar performance was measured using other setups and configurations.[15] (b) Output characteristics of low-power and low-voltage VOFET implemented using molecular vapour deposition (MVD) of AlOx as gate dielectric.[70] (c) Ambipolar
VOFET operation using N2200 as the semiconductor.[58] (d) Fast switching measurement of standard VOFET (full line = source current,
dashed line = drain current).[39]
indicates that the On/Off ratio can be further increased
by judicial device design, removing the negative influence
that short-channel length has on On/Off ratio.[55–56] Secondly, using self-assembly methods to design both the dielectric layer and the source electrode allows us to implement low-voltage VOFET operation (see Figure 29b).
While low-power performance relies on the low resistivity
of the short channel length, low voltage operation relies
also on the ability of the gate to form the channel. This is
perhaps one of the most central challenges specifically associated with the vertical design. Finally, based on the
unique physics that governs the VOFET operation, an ambipolar behaviour – which is critical for complementary circuit technology – can be realised, as shown in Figure 29c.
The VOFET combines excellent performance (lowpower, low-voltage, high frequency and ambipolar operation), together with simplicity of fabrication. But the advantages associated with this design far exceed the mere
improved performance of existing organic lateral transistors. In a nutshell, the vertical design can be used to implement new functions, such as light emitting transistors,[52,61] or to serve as a unique platform to explore bulk
material properties.
8. Summary
In this contribution, we described the basic principles and
uniqueness of disordered organic field effect transistors.
There are many other special features that may arise due
to specific density of states functions, as well as electronphonon interactions (polarons). If you read the body of
the paper, you know these are not really covered here
and should be sought elsewhere.
Acknowledgment
Part of the results shown here were achieved within research (No. 695/10) supported by the Israel Science Foundation.
Isr. J. Chem. 2014, 54, 568 – 585
References
[1] J. H. Burroughes, C. A. Jones, R. H. Friend, Nature 1988,
335, 137 – 141.
[2] A. R. Brown, A. Pomp, C. M. Hart, D. M. Deleeuw, Science
1995, 270, 972 – 974.
[3] C. J. Drury, C. M. J. Mutsaers, C. M. Hart, M. Matters, D. M.
de Leeuw, Appl. Phys. Lett. 1998, 73, 108 – 110.
[4] B. Crone, A. Dodabalapur, Y. Y. Lin, R. W. Filas, Z. Bao,
A. Laduca, R. Sarpeshkar, H. E. Katz, W. Li, Nature 2000,
403, 521 – 523.
[5] S. R. Forrest, IEEE J. Sel. Top. Quantum Electron. 2000, 6,
1072 – 1083.
[6] G. Horowitz, F. Deloffre, F. Garnier, R. Hajlaoui, M.
Hmyene, A. Yassar, Synth. Met. 1993, 54, 435 – 445.
[7] W. Fix, A. Ullmann, J. Ficker, W. Clemens, Appl. Phys. Lett.
2002, 81, 1735 – 1737.
[8] F. Garnier, R. Hajlaoui, A. Yassar, P. Srivastava, Science
1994, 265, 1684 – 1686.
[9] M. G. Kane, J. Campi, M. S. Hammond, F. P. Cuomo, B.
Greening, C. D. Sheraw, J. A. Nichols, D. J. Gundlach, J. R.
Huang, C. C. Kuo, L. Jia, H. Klauk, T. N. Jackson, IEEE
Electron Device Lett. 2000, 21, 534 – 536.
[10] K. Myny, S. Steudel, S. Smout, P. Vicca, F. Furthner, B. van
der Putten, A. K. Tripathi, G. H. Gelinck, J. Genoe, W. Dehaene, P. Heremans, Org. Electron. 2010, 11, 1176 – 1179.
[11] T. Granlund, T. Nyberg, L. S. Roman, M. Svensson, O. Inganas, Adv. Mater. 2000, 12, 269 – 273.
[12] D. Pede, G. Serra, D. Derossi, Mat. Sci. Eng. CBiomim.1998,
5, 289 – 291.
[13] J. A. Rogers, Z. Bao, M. Meier, A. Dodabalapur, O. J. A.
Schueller, G. M. Whitesides, Synth. Met. 2000, 115, 5 – 11.
[14] E. Avnon, Y. Paz, N. Tessler, Appl. Phys. Lett. 2009, 94.
[15] A. J. Ben-Sasson, E. Avnon, E. Ploshnik, O. Globerman, R.
Shenhar, G. L. Frey, N. Tessler, Appl. Phys. Lett. 2009, 95,
213301.
[16] H. Sirringhaus, N. Tessler, R. H. Friend, Science 1998, 280,
1741 – 1743.
[17] A. Dodabalapur, Z. Bao, A. Makhija, J. Laquindanum, V.
Raju, Y. Feng, H. Katz, J. Rogers, Appl. Phys. Lett. 1998,
73, 142 – 144.
[18] H. E. A. Huitema, G. H. Gelinck, J. B. P. H. Van der Putten,
K. E. Kuijk, K. M. Hart, E. Cantatore, D. M. De Leeuw,
Adv. Mater. 2002, 14, 1201 – 1204.
[19] C. D. Sheraw, L. Zhou, J. R. Huang, D. J. Gundlach, T. N.
Jackson, M. G. Kane, I. G. Hill, M. S. Hammond, J. Campi,
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
www.ijc.wiley-vch.de
584
Review
[20]
[21]
[22]
[23]
[24]
[25]
[26]
[27]
[28]
[29]
[30]
[31]
[32]
[33]
[34]
[35]
[36]
[37]
[38]
[39]
[40]
[41]
[42]
[43]
[44]
[45]
[46]
[47]
[48]
B. K. Greening, J. Francl, J. West, Appl. Phys. Lett. 2002, 80,
1088 – 1090.
M. A. McCarthy, B. Liu, E. P. Donoghue, I. Kravchenko,
D. Y. Kim, F. So, A. G. Rinzler, Science 2011, 332, 570 – 573.
N. Tessler, Y. Preezant, N. Rappaport, Y. Roichman, Adv.
Mater. 2009, 21, 2741 – 2761.
S. M. Sze, Physics of Semiconductor Devices, Wiley, New
York, 1981.
L. P. Ma, Y. Yang, Appl. Phys. Lett. 2004, 85, 5084 – 5086.
Y. Roichman, N. Tessler, Appl. Phys. Lett. 2002, 80, 151 –
153.
O. Tal, Y. Rosenwaks, Y. Roichman, Y. Preezant, N. Tessler,
C. K. Chan, A. Kahn, Appl. Phys. Lett. 2006, 88, 043509.
A. R. Brown, C. P. Jarrett, D. M. de Leeuw, M. Matters,
Synth. Met. 1997, 88, 37 – 55.
E. J. Meijer, C. Detcheverry, P. J. Baesjou, E. van Veenendaal, D. M. de Leeuw, T. M. Klapwijk, J. Appl. Phys. 2003,
93, 4831 – 4835.
B. Lssem, M. L. Tietze, H. Kleemann, C. Hoßbach, J. W.
Bartha, A. Zakhidov, K. Leo, Nat. Commun. 2013, 4.
N. Tessler, Y. Roichman, Org. Electron. 2005, 6, 200 – 210.
M. Vissenberg, M. Matters, Phys. Rev. B: Condens. Matter
Mater. Phys. 1998, 57, 12964 – 12967.
Y. Roichman, N. Tessler, Appl. Phys. Lett. 2002, 80, 1948 –
1950.
Y. Roichman, Y. Preezant, N. Tessler, Phys. Status Solidi A
2004, 201, 1246 – 1262.
D. Mendels, N. Tessler, J. Phys. Chem. C 2013, 117, 3287 –
3293.
O. Tal, Y. Rosenwaks, Y. Preezant, N. Tessler, C. K. Chan,
A. Kahn, Phys. Rev. Lett. 2005, 95, 256405.
O. Tal, I. Epstein, O. Snir, Y. Roichman, Y. Ganot, C. K.
Chan, A. Kahn, N. Tessler, Y. Rosenwaks, Phys. Rev. B:
Condens. Matter Mater. Phys. 2008, 77, 201201.
N. Tessler, Y. Roichman, Appl. Phys. Lett. 2001, 79, 2987 –
2989.
L. Burgi, R. H. Friend, H. Sirringhaus, Appl. Phys. Lett.
2003, 82, 1482 – 1484.
Y. Roichman, N. Tessler, Mater. Res. Soc, Symp. Proc, 2005,
871, 132 – 137.
M. Greenman, A. J. Ben-Sasson, Z. Chen, A. Facchetti, N.
Tessler, Appl. Phys. Lett. 2013, 103, 073502.
G. Horowitz, M. E. Hajlaoui, R. Hajlaoui, J. Appl. Phys.
2000, 87, 4456 – 4463.
Y. Roichman, N. Tessler, Synth. Met. 2003, 135–136, 443 –
444.
S. Shaked, S. Tal, Y. Roichman, A. Razin, S. Xiao, Y.
Eichen, N. Tessler, Adv. Mater. 2003, 15, 913 – 916.
J. I. Nishizawa, T. Terasaki, J. Shibata, IEEE Trans. Electron
Devices 1975, ED22, 185 – 197.
D. C. Mayer, N. A. Masnari, R. J. Lomax, IEEE Trans. Electron Devices 1980, 27, 956 – 961.
Z. Ravnoy, L. T. Lu, E. Kapon, S. Mukai, S. Margalit, A.
Yariv, Appl. Phys. Lett. 1984, 45, 258 – 260.
D. Klaes, J. Moers, A. Tonnesmann, S. Wickenhauser, L.
Vescan, M. Marso, T. Grabolla, M. Grimm, H. Luth, Thin
Solid Films 1998, 336, 306 – 308.
K. Kudo, D. X. Wang, M. Iizuka, S. Kuniyoshi, K. Tanaka,
Synth. Met. 2000, 111–112, 11 – 14.
O. Globerman, Technion Israel Institute of Technology
(Israel), 2006.
Isr. J. Chem. 2014, 54, 568 – 585
[49] Y. Yang, L. P. Ma, Vertical Organic Field Effect Transistor,
US 7,476,893 B2, US, 2009.
[50] N. Tessler, M. Margalit, O. Globerman, R. Shenhar, Transistor Structures and Methods of Fabrication, US 8,309,953 B2,
US, 2012.
[51] N. Tessler, R. Shenhar, O. Globerman, Transistors structures
and methods of fabrication, WO 2007/080576 A1, 2007.
[52] B. Liu, M. A. McCarthy, Y. Yoon, D. Y. Kim, Z. Wu, F. So,
P. H. Holloway, J. R. Reynolds, J. Guo, A. G. Rinzler, Adv.
Mater. 2008, 20, 3605 – 3609.
[53] P.-H. Wang, B. Liu, Y. Shen, Y. Zheng, M. A. McCarthy, P.
Holloway, A. G. Rinzler, Appl. Phys. Lett. 2012, 100,
173514.
[54] M. A. McCarthy, B. Liu, A. G. Rinzler, Nano Lett. 2010, 10,
3467 – 3472.
[55] A. J. Ben-Sasson, N. Tessler, J. Appl. Phys. 2011, 110, 12.
[56] A. J. Ben-Sasson, N. Tessler, Proc. SPIE 2011, 8117, 81170Z.
[57] A. J. Ben-Sasson, N. Tessler, Nano Lett. 2012, 12, 4729 –
4733.
[58] A. J. Ben-Sasson, Z. Chen, A. Facchetti, N. Tessler, Appl.
Phys. Lett. 2012, 100, 263306 – 263304.
[59] H. Kleemann, A. A. Gnther, K. Leo, B. Lssem, Small
2013, 9, 3670 – 3677.
[60] S. H. Li, Z. Xu, L. P. Ma, C. W. Chu, Y. Yang, Appl. Phys.
Lett. 2007, 91, 083507.
[61] Z. Xu, S. H. Li, L. Ma, G. Li, Y. Yang, Appl. Phys. Lett.
2007, 91, 092911.
[62] S. H. Li, Z. Xu, G. W. Yang, L. P. Ma, Y. Yang, Appl. Phys.
Lett. 2008, 93, 213301.
[63] J. Jiang, J. Sun, B. Zhou, A. Lu, Q. Wan, Appl. Phys. Lett.
2010, 97, 052104.
[64] M. A. McCarthy, B. Liu, R. Jayaraman, S. M. Gilbert, D. Y.
Kim, F. So, A. G. Rinzler, ACS Nano 2010, 5, 291 – 298.
[65] Y.-C. Chao, M.-C. Niu, H.-W. Zan, H.-F. Meng, M.-C. Ku,
Org. Electron. 2011, 12, 78 – 82.
[66] L. Rossi, K. F. Seidel, W. S. Machado, I. A. Hummelgen, J.
Appl. Phys. 2011, 110, 094508 – 094505.
[67] M. Puri, S. Bhanja, in Renewable Energy and the Environment, OSA Technical Digest (CD) (Optical Society of
America, 2011), paper JWE5.
[68] W. Mehr, J. Dabrowski, J. C. Scheytt, G. Lippert, X. YaHong, M. C. Lemme, M. Ostling, G. Lupina, IEEE Electron
Device Lett. 2012, 33, 691–693.
[69] K. Seidel, L. Rossi, R. Q. Mello, I. Hmmelgen, J. Mater.
Sci.: Mater. Electron. 2013, 24, 1052 – 1056.
[70] A. J. Ben-Sasson, G. Ankonina, M. Greenman, M. T.
Grimes, N. Tessler, ACS Appl. Mater. Interfaces 2013, 5,
2462 – 2468.
[71] W. Chen, A. Rinzler, J. Guo, J. Appl. Phys. 2013, 113,
234501.
[72] V. Di Lecce, R. Grassi, A. Gnudi, E. Gnani, S. Reggiani, G.
Baccarani, IEEE Trans. Electron Devices 2013, 60, 3584 –
3591.
[73] T. Georgiou, R. Jalil, B. D. Belle, L. Britnell, R. V. Gorbachev, S. V. Morozov, Y.-J. Kim, A. Gholinia, S. J. Haigh, O.
Makarovsky, L. Eaves, L. A. Ponomarenko, A. K. Geim,
K. S. Novoselov, A. Mishchenko, Nat. Nanotechnol. 2013, 8,
100 – 103.
2014 Wiley-VCH Verlag GmbH & Co. KGaA, Weinheim
Received: February 7, 2014
Accepted: March 6, 2014
Published online: June 6, 2014
www.ijc.wiley-vch.de
585