John H. Lau
ASME Fellow
S.-W. Ricky Lee1
ASME Member
Chris Chang
Express Packaging Systems, Inc.,
1137 San Antonio Road,
Palo Alto, CA 94303
1
Solder Joint Reliability of Wafer
Level Chip Scale Packages
(WLCSP): A Time-TemperatureDependent Creep Analysis
A novel and reliable wafer level chip scale package (WLCSP) is investigated in this
paper. It consists of a copper conductor layer and two low cost dielectric layers. The
bump geometry consists of the eutectic solder, the copper core, and the under bump
metallurgy. Nonlinear time-temperature-dependent finite element analyses are performed
to determine the shear stress, shear creep strain, shear stress and shear creep strain
hysteresis loops, and creep strain energy density of the corner solder joint. The thermalfatigue life of the corner solder joint is then predicted by the averaged creep strain energy
density range per cycle and a linear fatigue crack growth rate theory. The WLCSP solder
bumps are also subjected to shear test. Finally, the WLCSP solder joints are subjected to
both mechanical shear and thermal cycling tests. 关S1043-7398共00兲01004-5兴
Introduction
Solder bumped flip chips on expensive substrates such as ceramics have been used since 1960s. The past few years have witnessed an explosive growth in research and development efforts
devoted to solder bumped flip chips on low cost substrates such as
FR-4 printed circuit board 共PCB兲 or bismaleimide triazine 共BT兲
substrate. Typical examples include Tsukada et al. 关1兴, Pompeo
et al. 关2兴, Suryanarayana et al. 关3兴, Nguyen et al. 关4兴, Wang and
Wong 关5兴, Crane et al. 关6兴, Wun and Margaritis 关7兴, Pascarella and
Baldwin 关8兴, Naguyen et al. 关9兴, Wong et al. 关10兴, Vincent and
Wong 关11兴, Tong et al. 关12兴, Lau 关13兴, and Lau and Lee 关14兴.
There are at least two major reasons why it works. One is the
availability of high density substrate with fine line and width such
as the PCB with sequential or built-up circuits and micro vias
such as the DYCOstrate, plasma etched redistribution layers
共PERL兲, surface laminar circuits 共SLC兲, film redistribution layer
共FRL兲, interpenetrating polymer build-up structure system 共IBSS兲,
high density interconnect 共HDI兲, conductive adhesive bonded flex,
sequential bonded films, sequential bonded sheets, and filled micro via technologies. Unfortunately, they are not commonly available at reasonable costs yet.
The other, probably more important, reason is the underfill epoxy encapsulant used to reduce the effect of the global thermal
expansion mismatch between the silicon chip and the low cost
organic PCB or substrate. 共Since the chip, underfill, and substrate
are deformed together like a unit; i.e., the relative deformation
between the chip and the substrate is very small; thus the shear
deformation of the solder joint is very small.兲 The other advantage
of underfill encapsulant is to protect the chip from moisture, ionic
contaminants, radiation and hostile operating environments such
as thermal, mechanical, shock, and vibration.
The major disadvantages of underfill encapsulant are the difficulty in rework and the reduction in manufacturing through-put.
Even though the research efforts on reworkable underfill are very
active 关1–6兴, however, most of them are using solvent-based
chemicals and most of the chips 共such as passivation兲 and substrates 共such as solder mask, via, and copper pads兲 are degraded or
1
On sabbatiacal leave from Hong Kong University of Science & Technology.
Contributed by the Electrical and Electronic Packaging Division for publication in
the JOURNAL OF ELECTRONIC PACKAGING. Manuscript received by the EEPD Aug.
15, 1999; revised manuscript received May 29, 2000. Associate Technical Editor:
Tony Rafanelli.
Journal of Electronic Packaging
even damaged after rework. These issues further complicate the
known good die related problems and indicate that more work
needs to be done in this area.
As to the manufacturing through-put issue, fast-flow and fast
cure underfill encapsulants are currently under development
关7–12兴. However, the material properties of these underfills may
be degraded 共due to excessive/large voids, too high a thermal
coefficient of expansion, and too low a Young’s modulus兲 and,
thus affect the mechanical and physical properties of the solder
bumped flip chip on board assembly.
Meantime, a class of new packaging technology called wafer
level chip scale package 共WLCSP兲 关14兴 is emerging. It provides a
solution to the aforementioned problems. The unique feature of
most WLCSPs is the use of a metal layer to redistribute the very
fine-pitch peripheral-arrayed pads on the chip to much larger-pitch
area-array pads with much larger solder joints on the PCB. Thus,
with WLCSPs, the demand on PCB is relaxed, the underfill is not
needed, and the known-good-die 共KGD兲 issues become much
simpler.
In this paper, a novel WLCSP is presented. It consists of a
copper conductor layer and two low-cost dielectric layers. The
bump geometry consists of the SMT compatible 63wt% Sn37wt% Pb solder and a copper core on the under bump metallurgy
共UBM兲 of the chip. Cross-sections of samples are examined for a
better understanding of the redistribution, UBM, Cu core, and
solder joints. Also, the thermal-fatigue life of the solder joint is
predicted through a creep analysis and an empirical equation. Finally, the WLCSP solder bumps are subjected to shear test and the
WLCSP assembly is subjected to both mechanical shear and thermal cycling tests.
2
WLCSP and PCB Assembly
Figure 1 shows a square chip (9.64 mm⫻9.64 mm) with 144
peripheral-arrayed pads. The pad size is 0.1 mm⫻0.1 mm and the
pitch is 0.25 mm. By adding an additional metal layer on top of
the wafer, the fine-pitch peripheral-arrayed pads on the chip can
be redistributed to a much larger pitch and area-array pads in the
interior of the chip. In this case, the pitch is 0.75 mm and the pad
size is 0.3 mm in diameter. Figure 2 shows the details of redistribution. It can be seen that the 63wt%Sn-37wt%Pb solder bump is
supported by a Cu core, which is connected to the redistributed
Cu/Ni pad through the Cu/Ti UBM. The redistributed metal layer
is made of Cu/Ni.
Copyright © 2000 by ASME
DECEMBER 2000, Vol. 122 Õ 311
Fig. 3 WLCSP solder bump with copper core
Fig. 1 WLCSP of a peripheral-arrayed chip „in mm…
The key steps of the wafer bumping process for the present
WLCSP, Fig. 2, are briefly discussed as follows. First of all, the 8
in. 共200 mm兲 wafers are ultrasonic cleaned.
• Step 1: The polyimide is spun on the wafer and cured for an
hour. This will form a polyimide layer of 4–5 ␮m thick.
• Step 2: Apply photoresist and mask, then use photolithography technique 共align and expose兲 to open vias on the aluminum pads.
• Step 3: Etch the desired vias.
• Step 4: Strip off photoresist.
• Step 5: Sputter Ti and Cu over the entire wafer.
• Step 6: Apply photoresist and mask, then use photolithography technique to open the redistribution traces locations.
• Step 7: Electroplate Cu.
• Step 8: Electroplate Ni.
• Step 9: Same as Step 4.
• Step 10: Etch off the Ti/Cu.
• Step 11: Same as Step 1.
• Step 12: Apply photoresist and mask, then use photolithography technique to open vias for the desired bump pads and
cover the re-distribution traces.
• Step 13: Same as Step 3.
• Step 14: Same as Step 4.
• Step 15: Same as Step 5.
Fig. 2 Structural cross section of the WLCSP
312 Õ Vol. 122, DECEMBER 2000
• Step 16: Apply photoresist and mask, then use photolithography technique to open the vias on the bump pads to expose
the areas with UBM.
• Step 17: Electroplate Cu core.
• Step 18: Electroplate 63Sn-37Pb eutectic solder.
• Step 19: Same as Step 4.
• Step 20: Same as Step 10.
• Step 21: Reflow the eutectic solder.
A typical cross section of the WLCSP bump is shown in Figs.
3 and 4. The solder bump height and Cu core height of the
WLCSP are measured and the results are shown in Fig. 5. It can
Fig. 4 Cross sections of WLCSP-PCB assembly
Transactions of the ASME
Fig. 7 Shear fracture surfaces of WLCSP solder bumps
Fig. 5 WLCSP bump height and copper core height
be seen that the Cu core height and the solder bump height are all
very uniform. 共In this paper, the solders on the chip before joining
to the PCB are called solder bumps. After the solder bumps have
been reflowed on the PCB, they are called solder joints.兲
The solder bumps of the WLCSP are subjected to shear test
with the following conditions: 共1兲 shear blade speed is 100 ␮m/s,
and 共2兲 the tip of shear blade is 100 ␮m from the chip surface.
The results are shown in Fig. 6. It can be seen that the averaged
solder bump shear strength is 404 gf, which is many times higher
than that 共⬃50 gf兲 of the conventional flip chip solder bumps. It is
noted that the failure location is in the solder bump 共not at the
UBM兲 and the fracture surface is shear dominated, Fig. 7.
It is very easy to assemble the WLCSP on PCB. After the
63Sn-37Pb solder bumped WLCSP is aligned with the PCB with
a look-up camera and a look-down camera, then the chip is placed
face-down on the PCB with a minimum force. After chip placement, the PCB is placed on the conveyor belt of a reflow oven
with a maximum on-PCB temperature of 220°C. A typical cross
section of the WLCSP PCB assembly is shown in Fig. 4. The
details of the redistribution layer and the UBM are also shown in
Fig. 2. It can be seen that the Ti/Cu on the Al pad are supporting
the redistribution trace 共Cu/Ni兲 which is protected by the polyimide. At the solder joint, the Cu core on the Ni/Cu pad is connected
by the Cu/Ti UBM, which is isolated from the Si chip with a layer
of polyimide dielectric.
3
Finite Element Modeling
Detailed dimensions of the WLCSP assembly under consideration in this study are shown in Fig. 8. A commercial finite element code, ANSYS 共Version 5.5兲, is employed. A two-
Fig. 8 Typical structure of the WLCSP solder joint
dimensional model is established using 8-node plane strain
elements. It should be noted that all detailed assembly structures
such as the chip, Al pads, polyimide, passivation, UBM, Ni layer,
Cu layer, solder joint, Cu core, Cu pads, and solder mask are
modeled in the finite element analysis. Besides, due to the symmetry in the assembly structure, only one half of the diagonal
cross-section is considered.
4
Time-Temperature-Dependent Creep Analysis
The material properties used in the computational modeling are
shown in Table 1. Since the scope of this Section is to investigate
the effects of Cu core height and solder joint height on the solder
joint reliability, except that the eutectic solder 共63Sn-37Pb兲 is a
time-temperature-dependent creep material, all other constituents
are considered as linear elastic materials.
The Garofalo-Arrhenius steady-state creep is generally expressed by 共see for example, Eq. 共1-188兲 through Eq. 共1-191兲 of
Lau 关15兴兲
冉 冊冋 冉 冊册 冉 冊
d␥
G
⫽C
dt
␪
Fig. 6 Shear strength of WLCSP solder bumps
Journal of Electronic Packaging
sinh ␻
␶
G
n
exp
⫺Q
k␪
(1)
where ␥ is the steady-state shear creep strain, d ␥ /dt is the steadystate shear creep strain rate, t is the time, C is a material constant,
G is the temperature dependent shear modulus, ␪ is the absolute
DECEMBER 2000, Vol. 122 Õ 313
Table 1 Material properties of the WLCSP PCB assemblies
temperature (K), ␻ defines the stress level at which the power law
stress dependence breaks down, ␶ is the shear stress, n is the
stress exponent, Q is the activation energy for a specific
diffusion mechanism, and k is the Boltzmann’s constant. For
60wt%Sn/40wt%Pb solder, the material constants have been experimentally determined by Darveaux and Banerji, Eq. 共1-44兲 of
Lau 关16兴 with a single hyperbolic sine function and are shown in
Fig. 9.
The temperature loading imposed on the WLCSP assembly is
shown in Fig. 10. It can be seen that for each cycle 共60 minutes兲
the temperature condition is between ⫺20°C and 110°C with 15
minutes ramp, 20 minutes hold at hot, and 10 minutes hold at
cold. Three full cycles are executed.
A typical deformation of the WLCSP assembly is shown in Fig.
11. It can be seen that the maximum relative deformation 共dominated by shear兲 is at the corner solder joint. This is due to the
thermal expansion mismatch between the chip and the PCB. The
location of the maximum shear stress and shear creep strain is in
the corner joint at the interface between the lower left-hand corner
of the Cu core and the solder joint, see Figs. 12 and 13.
For time-dependent analysis, it is important to study the responses
for multiple cycles until the hysteresis loops become stabilized.
The shear stress and shear creep strain at the maximum location
共corner兲 are shown 共in solid-line兲 in Figs. 14 and 15, respectively.
Figure 16 shows the maximum shear stress and shear creep strain
hysteresis loops 共in solid-line兲 for multiple cycles. It can be seen
that the creep shear strain is quite stabilized after the first cycle.
Figure 17 shows the time history of creep strain energy density
at the maximum location. The averaged creep strain energy density range per cycle (⌬W) at the corner solder joint can be obtained by averaging the creep strain energy density ranges of the
last two cycles, which is 0.57 N/mm2 ⫽82.5 psi. Similarly, the
shear stress, shear creep strain, shear stress and shear creep strain
hysteresis loops, and creep strain energy density at the center of
Fig. 10 Temperature profile for modeling and thermal cycling
test
Fig. 11 Deformed shape of half of the WLCSP assembly
Fig. 12 Shear stress distribution in the corner solder joint
Fig. 9 Constitutive equation of eutectic solder with creep
deformation
314 Õ Vol. 122, DECEMBER 2000
Fig. 13 Shear creep strain distribution in the corner solder
joint
Transactions of the ASME
Fig. 14 Time-dependent shear stress at the maximum and
center locations of the corner solder joint
Fig. 17 Time-dependent creep strain energy density at the
maximum and center locations of the corner solder joint
5 Thermal-Fatigue Life Prediction of WLCSP Corner
Solder Joint
Once we have ⌬W, the thermal fatigue crack initiation life
(N 0 ) can be estimated from 共Darveaux兲 Equation 共13.35兲 of Lau
关17兴, i.e.,
N 0 ⫽7860⌬W ⫺1 ⫽95 cycles at the corner
(2)
N 0 ⫽7860⌬W ⫺1 ⫽313 cycles at the center
(3)
and the thermal fatigue crack propagation life 共N兲 based on the
linear fatigue crack growth rate theory can be estimated by
共Darveaux兲 Eq. 共13.36兲 of Lau 关17兴, i.e.,
da/dN⫽4.96⫻10⫺8 ⌬W 1.13
(4)
N⫽N 0 ⫹ 共 a f ⫺a 0 兲 / 共 4.96⫻10⫺8 ⌬W 1.13兲
(5)
or
Fig. 15 Time-dependent shear creep strain at the maximum
and center locations of the corner solder joint
where a is the crack length of the solder joint; a 0 is the initial
crack length, which is assumed to be zero; and a f is the final crack
length. It can be seen that in order to determine N, we need to
choose an a f . For example, if a f ⫽0.364 mm 共solder cracks
through near the bottom of the Cu core兲, then N⫽95⫹1,973
⫽2,068 cycles. On the other hand, if a f ⫽0.390 mm 共solder cracks
through the middle of the solder joint兲 then N⫽313⫹8,111
⫽8,420 cycles.
It should be pointed out that, due to a numerical integration
scheme error in the old version of the finite element code ANSYS,
for some very special cases, Darveaux’ thermal-fatigue life prediction equations may involve errors as high as 16 percent, as
reported by Anderson et al. 关18兴. This subject has also been discussed in greater details by Darveaux 关19兴.
Fig. 16 Hysteresis loops of the shear stress and shear creep
strain at the maximum and center locations of the corner solder
joint
the solder joint are shown 共in dotted-line兲 in Figs. 14, 15, 16, and
17, respectively. It can be seen that, due to stress concentration at
the corner of Cu core, the shear creep strain at the corner of solder
joint is about 3 times of that at the center. The averaged creep
strain energy density range per cycle (⌬W) at the center of corner
solder joint is 0.17 N/mm2 ⫽25.1 psi.
Journal of Electronic Packaging
6 WLCSP-PCB Assembly Under Shear and Thermal
Cycling Tests
WLCSP-PCB assemblies have been subjected to thermal cycling test with the temperature profile given in Figure 10. At the
time of this writing, all the solder joints have survived for more
than 1300 cycles without any failure. The test is still on going.
The WLCSP-PCB assemblies are subjected to shear tests also.
A typical load-displacement curve is shown in Fig. 18. It can be
seen that the maximum force is 17 kgf for 45 solder joints, i.e.,
380 gf per solder joint. This is very close to the shear strength of
solder bumps measured in Section 2. Again, the failure mode is in
the solder 共dominated by shear fracture兲, not at the UBM, Fig. 19.
DECEMBER 2000, Vol. 122 Õ 315
The WLCSP-PCB assemblies have been subjected to the shear
test. The shear strength per solder joint is 380 gf, which is close to
that measured from the WLCSP solder bumps. The failure mode
is in the solder joint and is dominated by shear.
Acknowledgments
The authors would like to thank APTOS for making the solder
bumps and for supporting this project.
References
Fig. 18 Load-displacement curve of the WLCSP-PCB assembly under shear test
Fig. 19 Shear fracture surfaces of the WLCSP solder joints
7
Summary
A cost effective and reliable WLCSP has been investigated in
this study. It consists of a Cu/Ni conductor layer and a couple of
polyimide dielectric layers. The solder bump geometry consists of
the SMT compatible eutectic solder and a copper core on the
redistributed Ni/Cu supporting pad with the Ti/Cu as the UBM.
The thermal-fatigue life of the corner solder joint of the
WLCSP assembly has been predicted by a time-temperaturedependent creep analysis and the empirical equation given by
Darveaux. It is found that the thermal-fatigue life of the corner
solder joint of the WLCSP is more than 2000 cycles 共60 minutes
cycle between ⫺20°C and 110°C with 15 minutes ramp, 20 minutes hold at hot, and 10 minutes hold at cold兲. This is adequate for
most of the operating conditions.
The key process steps for WLCSP wafer bumping have been
briefly presented. Also, the bump height and bump strength of the
WLCSP have been measured. The averaged bump shear strength
is 404 gf. This value is much larger than that 共shear strength ⬃ 50
gf兲 of the conventional flip chip solder bumps.
316 Õ Vol. 122, DECEMBER 2000
关1兴 Tsukada, Y., Tsuchida, S., and Mashimoto, Y., 1993, ‘‘A Novel Chip Replacement Method for Encapsulated Flip Chip Bonding,’’ Proceedings of IEEE
Electronic Components & Technology Conference, Orlando, FL, June, pp.
199–204.
关2兴 Pompeo, F. L., Call, A. J., Coffin, J. T., and Buchwalter, S., 1995, ‘‘Reworkable Encapsulation for Flip Chip Packaging,’’ Proceedings of the International
Intersociety Electronic Packaging Conference, Maui, HA, March, pp. 781–
787.
关3兴 Suryanarayana, D., Varcoe, J. A., and Ellerson, J. V., 1995, ‘‘Reparability of
Underfill Encapsulated Flip-Chip Packages,’’ Proceedings of IEEE Electronic
Components & Technology Conference, Las Vegas, NV, May, pp. 524–528.
关4兴 Nguyen, L., Fine, P., Cobb, B., Tong, Q., Ma, B., and Savoca, A., 1998,
‘‘Reworkable Flip Chip Underfill—Materials and Processes,’’ Proceedings of
the International Symposium on Microelectronics, San Diego, CA, November,
pp. 707–713.
关5兴 Wang, L., and Wong, C. P., 1999, ‘‘Epoxy-Additive Interaction Studies of
Thermally Reworkable Underfills for Flip-Chip Applications,’’ Proceedings of
IEEE Electronic Components & Technology Conference, San Diego, CA,
June, pp. 34–42.
关6兴 Crane, L., Torres-Filho, A., Yager, E., Heuel, M., Ober, C., Yang, S., Chen, J.,
and Johnson, R., 1999, ‘‘Development of Reworkable Underfills, Materials,
Reliability and Proceeding,’’ Proceedings of NEPCON WEST, February, pp.
144–151.
关7兴 Wun, K. B., and Margaritis, G., 1996, ‘‘The Evaluation of Fast-Flow, FastCure Underfills for Flip Chip on Organic Substrates,’’ Proceedings of IEEE
Electronic Components & Technology Conference, Orlando, FL, May, pp.
540–545.
关8兴 Pascarella, N., and Baldwin, D., 1997, ‘‘Advanced Encapsulation Processing
for Low Cost Electronics Assembly—A Cost Analysis,’’ The 3rd International
Symposium and Exhibition on Advanced Packaging Materials, Processes,
Properties, and Interfaces, Braselton, GA, Mar., pp. 50–53.
关9兴 Naguyen, L., Hoang, L., Fine, P., Tong, Q., Ma, B., Humphreys, R., Savoca,
A., Wong, C. P., Shi, S., Vincent, M., and Wang, L., 1997, ‘‘High Performance Underfills Development—Materials, Processes, and Reliability,’’ IEEE
1st International Symposium on Polymeric Electronics Packaging, Norrkoping, Sweden, Oct., pp. 300–306.
关10兴 Wong, C. P., Vincent, M. B., and Shi, S., 1997, ‘‘Fast-Flow Underfill Encapsulant: Flow Rate and Coefficient of rmal Expansion,’’ Proceedings of the
ASME Adv. Electro. Packag., 19-1, pp. 301–306.
关11兴 Vincent, M. B., and Wong, C. P., 1998, ‘‘Enhancement of Underfill Encapsulants for Flip-Chip Technology,’’ Proceedings of Surface Mount International
Conference, San Jose, CA, Aug., pp. 303–312.
关12兴 Tong, Q., Savoca, A., Nguyen, L., Fine, P., and Cobb, B., 1999, ‘‘Novel Fast
Cure and Reworkable Underfill Materials,’’ Proceedings of IEEE Electronic
Components & Technology Conference, San Diego, CA, June, pp. 43–48.
关13兴 Lau, J. H., 2000, Low Cost Flip Chip Technologies for DCA, WLCSP, and
PBGA Assemblies, McGraw-Hill, New York, NY.
关14兴 Lau, J. H., and Lee, S. W. Ricky, 1999, Chip Scale Package, Design, Materials, Process, Reliability, and Reliability, McGraw-Hill, New York, NY.
关15兴 Lau, J. H., 1993, Thermal Stress and Strains in Microelectronics Packaging,
Van Nostrand Reinhold, New York, NY.
关16兴 Lau, J. H., 1994, Chip On Board Technologies for Multichip Modules, Van
Nostrand Reinhold, New York, NY.
关17兴 Lau, J. H., 1995, Ball Grid Array Technology, McGraw-Hill, New York, NY.
关18兴 Anderson, Guven, T., I., Madenci, E., and Gustafsson, G., 1999, ‘‘The Necessity of Reexamining Previous Life Prediction Analyses of Solder Joints in
Electronic Packages,’’ Proceedings of IEEE Electronic Components & Technology Conference, June, pp. 656–663.
关19兴 Darveaux, R., 2000, ‘‘Effects of Simulation Methodology on Solder Joint
Crack Growth Correlation,’’ Proceedings of IEEE Electronic & Components
Technology Conference, May, pp. 1048–1058.
Transactions of the ASME