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CSE 140 Midterm 1 - Solutions
Prof. Tajana Simunic Rosing
Spring 2013
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Do not start the exam until you are told.
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Write your name and PID at the top of
every page. Do not separate the pages.
•
Turn off and put away all your
electronics.
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This is a closed-book, closed-notes,
no-calculator exam. You may only
refer to one 8 ½ x 11” page of your
handwritten notes.
•
Do not look at anyone else's exam.
Do not talk to anyone but an exam
proctor during the exam.
•
If you have a question, raise your hand
and an exam proctor will come to you.
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You have 80 minutes to finish the exam.
When the time is finished, you must
stop writing.
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Write your answers in the space
provided.
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No credit will be given if you do not
show all steps of your work.
1. 15 points
2. 15 points
3. 15 points
4. 20 points
5. 20 points
6. 15 points
Total (100 pts.)
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Problem 1 Using the truth table shown in Table I:
Table I: Truth Table for Function F
a) Write down the SOP canonical forms for F(A,B,C,D) and F’(A,B,C,D)
F(A,B,C,D)=Σm(1,7,9,12,14,15) + Σd(3,5,11,13)
F’(A,B,C,D)=Σm(0,2,4,6,8,10) + Σd(3,5,11,13)
b) Write down the POS canonical forms for F(A,B,C,D) and F’(A,B,C,D)
F(A,B,C,D)=πM(0,2,4,6,8,10) * πd(3,5,11,13)
F’(A,B,C,D)=πM(1,7,9,12,14,15) * πd(3,5,11,13)
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Problem 1
c) Use a Karnaugh map to find the minimum size boolean expression in POS form for the
truth table provided in Table I.
POS: F(A,B,C,D)=(A+D)(B+D)
Problem 2
a) Find and circle the critical path in the circuit below. Calculate the maximum propagation delay from
inputs to the output Y.
Gate
NOT
2-NAND
2-NOR
2-AND
2-OR
2-XOR
Delay (ps)
15
20
20
30
30
45
15 + 45 + 15 + 30 = 105ps
b) Simplify and implement the circuit with NAND gates.
AB\CD
00
01
11
10
00
0
1
0
1
01
0
1
0
1
11
0
1
0
1
10
0
1
0
1
Problem 3
Implement the Boolean equation Y= (A’B+C)’ using the minimum number of PMOS and NMOS
transistors.
Problem 4
Partially-specified schematic below implements the function F=A'C+B'D+CD. Without adding any
gates to the circuit, complete the implementation by identifying the unspecified inputs. (Hint: the inputs
can only be A, B, C, D, 0 or 1).
Problem 5
a) Write the minimal SOP expression for the circuit below. The control inputs are A & D, where MSB
is A & LSB is D.
AB\CD
00
01
11
10
00
1
1
1
1
01
0
0
1
0
11
1
1
1
0
10
0
0
1
1
SOP: C’D’ + AB + AD’ + A’CD
b) Are there any static-1 hazards in the minimal SOP implementation? If so, add additional terms to
your expression that are required to fix the hazard. If not, explain why not.
Yes, there is a Hazard. To fix the hazard, add BCD term to the logic equation.
Problem 6
For the circuit below assume A=1 & B=0 & C=1 initially. Find the delay at point X, when input C
changes from 1->0 and the other two inputs remain constant. Assume Rp=2Rn and the unit delay is
RnCg. Express your answer in terms of the unit delay.
Two PMOS transistors are in the charging path so Req= 2Rp.
The point X is driving equivalent downstream capacitance of 2Cg.
Hence the rising delay tr= 2Rp*2Cg = 4RpCg = 8RnCg.
Given Circuit
Equivalent Circuit to use for solution