Investigation of Choline Hydroxide for Selective Silicon Etch from a
Gate Oxide Failure Analysis Standpoint
Valentina Korchnoy,
Intel Israel (74) Ltd., Haifa, Israel
E-mail: [email protected]
robust procedure for selective to SiO2 poly-silicon
wet etch using choline hydroxide. An investigation of
some general silicon etching characteristics of choline
hydroxide, such as etch rate, silicon to SiO2
selectivity, surface roughness, and hillocks formation
has been also carried out.
Previously, many etchants have been proposed for
selective to SiO2 silicon etching, including the
inorganic aqueous solutions KOH, NaOH, CsOH,
NH4OH [4], as well as organic solutions containing
tetramethyl
ammonium
hydroxide
(TMAH),
ethylenediamine-pyrocatechol-water
(EDP)
and
hydrazine-water (N2H4)n solutions [5]. As reported in
[3],[6],
choline
hydroxide
[(CH3)3N(CH2CH2OH)OH] has been used for silicon
etching from the BS that leaves the underlying gate
oxide untouched.
Abstract
A robust procedure for poly-silicon wet etch selective
to SiO2 is presented. The procedure is applicable for
CMOS devices and maintains the integrity of the gate
oxide film. The technique uses a 50% wt. choline
hydroxide aqueous solution. The optimum etching
conditions, which allow exposure of gate oxide to
enable its further inspection using SEM or AFM were
determined. An investigation of general silicon
etching characteristics of choline hydroxide, as etch
rate, selectivity and surface quality, has been carried
out as well.
Introduction
The trend in the semiconductor technology is to
increase component density and reduce device
minimum dimensions, such as channel length and
gate oxide thickness. These changes make devices
more susceptible to gate oxide related failures, such
as shorts or leakage due to gate oxide holes or soft
gate oxide breakdown. From the failure analysis point
of view, micro-miniaturization introduces additional
challenges to device de-layering, particularly to gate
oxide exposure targeted for SEM inspection. It’s
important to note, that some gate oxide related
defects, such as soft gate oxide breakdown, cannot be
visualized using standard analytical tools. In recent
years, Atomic Force Microscopy (AFM) and AFM
based tunneling techniques have been reported [1] as
potential methods for gate oxide leakage mapping.
AFM also requires gate oxide exposure to enable the
analysis. This makes gate oxide exposure a key
sample preparation step for root cause analysis of
gate oxide related failures.
The most common etchants used for FS poly-silicon
removal are KOH and TMAH aqueous solutions.
TMAH is the most popular because of its relatively
low toxicity and high etch selectivity of silicon to
oxide [7]. However, TMAH and KOH have several
demerits, namely, higher etch rate for n-doped polysilicon over p-doped, strong etch rate dependence on
dopant type and doping level [8], and a strong effect
of small amounts of contaminants on the etch rate [9],
[10]. The latter property results in additional
requirements to sample preparation prior to the
etching. Etch rate similarity for n- and p-doped
silicon is essential for CMOS FA applications,
especially for SRAM, where gate oxide under both ndoped and p-doped poly should be exposed for
further inspection.
In the present investigation we use a 50% wt. choline
hydroxide aqueous solution for FS poly-silicon
etching. This choice is determined mainly by unique
silicon to oxide etching selectivity. Choline hydroxide
is an organic etchant, which develops strong
oxidizing properties. The oxidizing agents are OHions.
Two approaches exist in gate oxide exposure
techniques. The first approach uses planar polishing
and selective poly-silicon wet etch to expose the gate
oxide from the front side (FS) [2]. The second
includes silicon bulk grinding followed by wet silicon
etching for gate oxide exposure from the back side
(BS) [3]. The present work is devoted mainly to the
first of the above-mentioned methods, and describes a
In the first part of the paper, a set of experiments,
which investigates the general etching characteristics
of silicon and SiO2 in choline hydroxide, such as etch
1
rate, selectivity, and surface quality of silicon, is
described.
match within 1 m with the data obtained by optical
microscope.
The second part of the paper is devoted to the failure
analysis applications of the obtained results. In this
set of experiments FS poly-silicon etch for gate oxide
exposure was performed. The goal was to find the
best etching conditions, which enable exposure of
gate oxide under both: the n- poly and the p- poly
simultaneously, and to develop a reliable and robust
procedure for gate oxide exposure for subsequent
SEM analysis.
SiO2 film thickness before and after the etching was
measured using a spectrophotometer. SiO2 etch rate
was calculated by dividing the film thickness
difference by the etching time.
Silicon surface roughness was measured using an
alpha-step profilometer, by performing four 2-mm
length scans for each specimen with a sampling rate
of 1 point/micron, and averaging the results over four
scans. Silicon surface morphology was examined
using an optical microscope and SEM.
Experimental Method
The second part of the work was devoted to the
application of silicon and SiO2 etch data obtained in
the first part, to gate oxide failure analysis. In these
experiments, FS poly-silicon selective etching for
gate oxide exposure was performed. CMOS 0.13 m
technology SRAM specimens were used for the
experiments. The sample preparation preceding the
etching includes FS polishing of dies down to the
poly-silicon layer, optical and SEM inspection, and
final polishing targeted to remove any salicide
residuals and SEM-related carbon built-up, which can
interfere with the etching process. The setup of this
experiment was the same as for the first set. The
variables were etch temperature and etching time.
The etching results were documented using SEM
micrographs at 40,000X magnification.
The etch rate of silicon and SiO2 in choline hydroxide,
Si/SiO2 selectivity, and the etch influence on silicon
surface morphology were investigated. Silicon
substrate specimens 3 mm x 10 mm x 0.75 mm with
(100) orientation, p-type doped to 5-10 milliohms-cm
were used. Two sets of specimens were prepared. The
first one had unpolished surfaces with overall average
roughness of 850 Å. In the second set, mirror-face
polished silicon specimens with initial average
roughness of 70 Å were used. A part of each
specimen was covered by 1 micron of SiO 2, grown by
PECVD. This oxide was used as an etch mask for the
silicon.
SiO2 etching experiments were carried out on 700 nm
thick oxide films, grown by PECVD on mirror-face
polished silicon specimens.
The high viscosity of choline hydroxide creates
problems in rinsing and cleanling. This makes the
post-etching cleaning procedure essential for enabling
the consequent SEM inspection of a specimen. It is
standard practice to allow the specimen to soak in DI
water for several minutes after the etching. This
procedure was followed by the treatment in hot
solvents accordingly to the following scheme:
- boiling acetone for 8 minutes, and then
ultrasonic bath in acetone for 2 minutes;
- boiling methyl alcohol for 6 minutes, and
then ultrasonic bath in methanol for 2
minutes;
- ultrasonic bath in isopropyl alcohol for 2
minutes at room temperature.
This procedure completely removes all choline
residues from the specimens providing the clarity of
the SEM micrographs.
Etching experiments were performed in 50% wt.
choline hydroxide aqueous solution, heated to
temperatures ranging from 20°C to 92°C. Etching
was carried out in a glass vessel thermostated with a
water bath on a laboratory hot plate. The temperature
variation was less than +/- 1.5ºC. The solution was
slowly stirred during the etching. The specimens were
kept in a teflon strainer. A reflux condenser was used
to reduce concentration change during the etching.
The silicon specimens were dipped for 15 seconds in
2% hydrofluoric acid prior to the etching to remove
the native oxide layer. The etch rate for Si (100) was
calculated by dividing the etch depth by the etching
time. The silicon etch depth was measured by
focusing an optical microscope on the grown SiO 2
film and then on the etched silicon surface, and
subtracting the respective heights, giving the result
with an accuracy of ~+/- 1 m. In addition, the silicon
etch depth was measured using an electronic
micrometer. The last method gives the data that
Results and Discussion
2
reaches 10000:1 at room temperature. The selectivity
decreases slowly to ~5000 with the temperature
increase up to 93°C. This high silicon to SiO2
selectivity provides a good basis for the gate oxide
failure analysis application. If the standard polysilicon gate thickness is ~10-7 m, and the gate oxide
thickness is ~10-9 m, we still have enough selectivity
reserve for a robust process which is tolerant to
etching condition variability.
Etch Rate and Si/SiO2 Selectivity
Figure 1 represents a graph of the logarithm of the
etch rate of silicon and SiO2 vs. inverse absolute
temperature. One can see from the graph, that silicon
and SiO2 etch in choline hydroxide is a thermallyactivated process which obeys the Arrhenius Law:
(1)
V =Aexp( -Ea/kT),
Table 1: Si and SiO2 Etch Rates in Choline
Hydroxide and Si to SiO2 Etching Selectivity at
Various Etch Temperatures
where V is the etch rate, T is absolute temperature, E a
is the activation energy, k is the Bolzman coefficient,
and A is a constant. The calculated values of
activated energy are: 0.51 eV for unpolished silicon
specimens, 0.61 eV for mirror-face polished silicon
specimens, and 0.72 eV for SiO2.
Etch
Temparature,
ºC
22
38
52
73
87
93
The etch rate for mirror-face polished p-doped silicon
ranges from ~4 nm/min at room temperature to ~360
nm/min at 90°C. This etch rate is sufficient for polygate etching applications, taking into account that
poly gate thickness is typically several hundreds of
nanometers for modern technologies, and assuming
that poly-silicon etch rate should be close to
monocrystalline silicon etch rate.
Si
Etch rate,
nm/min
3.8
17.2
40.7
200
344
427
SiO2
Etch rate,
nm/min
0.00036
0.0025
0.0074
0.029
0.055
0.083
Si to SiO2
Etching
Selectivity
10555
6880
5500
6896
6254
5144
Etch Rate, nm/min
Silicon Surface Morphology
10
3
10
2
10
1
10
0
10
-1
10
-2
10
-3
Ea=0.51 eV
Ea=0.61 eV
Surface morphology dependence on etching
temperature, etch time, and initial surface roughness
was investigated.
- SiO2
- mirror polished Si
- unpolished Si
Figures 2(a)-3(f) show surface relief development
during etching in choline hydroxide for unpolished
silicon specimens etched at varying temperatures.
One can see that the etching yields surfaces that are
texturized, i.e. covered with pyramids, whose sizes
and shapes depend on etching temperature. Sizes
range from several microns (at 20°C) to 100 micron
(at 90°C). Table 2 represents an average background
roughness of the specimens shown in Figure 2. The
roughness of the specimens increases considerably
with etch temperature.
Ea=0.72 eV
-4
10
2.6
2.8
3.0
3.2
3.4
3.6
3
10 /T, 1/K
Figure 1: Arrhenius plot of etch rate of silicon and
SiO2 in choline hydroxide.
The etch rate for unpolished silicon specimens is
higher than for mirror-face polished ones, reaching
430 nm/min at 90°C. The simple explanation for this
fact is, that the rougher surface provides more total
contact area with the reactive agent during the
etching.
Table 2: Roughness of Unpolished Silicon Surface
after Choline Hydroxide Etch at Various Etch
Conditions
Table 1 represents Si and SiO2 etch rates at various
temperatures and shows the dependence of Si to SiO2
etching selectivity on temperature. One can see that
the selectivity of silicon to oxide is superior and
Sample
number
3
Etch
temperature,
Etch time,
hours
Surface
roughness,
1 (ref)
2
3
4
5
6
°C
20
34
55
80
92
temperature. Roughness data for mirror-face polished
specimens, represented in Table 3, confirm this
assumption.
Å
847
908
1045
1760
1839
2661
1.5
0.5
0.5
0.33
0.5
Figure 4 shows an example of small square-based
{111}-bounded pyramid-shaped hillocks, which
appears on the mirror-face polished surface after
choline etch.
22ºC
50 hours
a
b
0
90°C
3 hours
100m
0
100 m
Figure 3: Optical micrographs of etched silicon
mirror-face polished samples showing the effect of
etch conditions on surface morphology.
c
Table 3: Roughness of Mirror-Face Polished Silicon
Surface after Choline Hydroxide Etch at Various Etch
Conditions
d
Sample
number
e
1 (ref)
2
3
4
5
6
7
8
f
Figure 2: Optical micrographs of etched unpolished
silicon samples showing the effect of temperature on
silicon surface morphology.
The surface of mirror-face polished specimens after
choline hydroxide etch differs considerably from the
surface of unpolished specimens. As can be seen in
Figure 3, a similar overall surface finish has been
obtained in two cases: after 50 hours etching at room
temperature, and after 3 hours etching at 90°C. The
surface remains smooth, although a distribution of
varying sized square-shaped pyramids (hillocks)
appears on both samples. It has been found, that for
mirror-face polished specimens, the surface quality
depends on etch time, rather than on the etch
4
Etch
temperature,
°C
22
22
39
50
63
90
90
Etch time,
hours
3
50
3
3
3
1
3
Surface
roughness,
Å
70
68
143
78
95
93
110
140
temperature increase. These considerations have
resulted in the etch temperature choice of 55°C.
Figure 4: SEM micrograph of pyramid-shaped
hillocks.
Figures 6 through 9 show the etching results at
temperature 55°C for 2, 4, 6, and 8 minutes of
etching, respectively. One can see that the poly gate is
completely etched and the gate oxide is exposed
under both n-doped and p-doped poly, when etching
lasts 4, 6, or 8 minutes. Taking into account silicon to
SiO2 selectivity data, the upper time limit can be
estimated as ~12 minutes. It’s important to note, that
the etching doesn’t introduce artifacts and yields to
the clearly exposed gate oxide. As can be seen in
Figure 6, etching during two minutes results in gate
oxide exposure only under n-doped poly. This means
that some etch selectivity between n-doped and pdoped poly exists. The author’s estimations give ~7080 nm/min for n-poly etch rate, 30-35 nm/min for ppoly etch rate, which results in factor of 2 for n-poly
to p-poly selectivity. The poly-silicon etch rate at
55°C in these experiments is found to be lower than
that obtained from bulk silicon etching. This can be
explained by the heavy doping level of poly-gates,
which can degrade the etch rate. In addition, the gate
width to gate thickness ratio can also be responsible
for the etch rate decrease.
Silicon surface roughness and morphology are
essential for micromachining applications, which
require a mirror-like quality. In general, the nature of
surface morphology formation in aqueous hydroxide
solutions (as KOH or TMAH) is a competition
between the rate of dissolution of silicon and the local
passivation of the surface by the accumulation of
masking species. Hydrogen bubbles [11], reaction
by-products [12], and foreign impurities [9], while
adsorbing to the silicon surface, can act as nucleation
points for relief formations. As reported, surface
roughness also depends on such factors as OH- ion
concentration [12] and silicon etch anisotropy in
different crystallographic directions [13]. In the
current study we didn’t investigate the influence of
the above-mentioned factors on the surface quality.
However, by comparison of our results with the data
presented in literature for KOH and TMAH, we can
conclude that silicon etching in choline hydroxide
yields a surface good enough for MEMS applications.
Poly-Silicon Etching and Gate Oxide Exposure
The etching conditions thus proposed by the author
are: etching during 4-8 minutes at 55°C. This
provides complete and artifact-free poly-gate etching
for both n- and p- regions with a high selectivity to
gate oxide. Etch rate for gate oxide has been
estimated to be <0.01nm/min. This ensures a high
tolerance of the suggested method to the etching
conditions (etch time and temperature) variations.
On the basis of the data obtained in the first part of
this investigation, the method for gate oxide exposure
by selective poly-silicon gate etching has been
elaborated. The goal is to find the best etch
conditions, which enable exposure of gate oxide
under both the n- poly and the p- poly simultaneously,
and to develop a reliable and robust procedure for
gate oxide exposure.
Figure 5 presents a SEM micrograph of SRAM
memory cells at ILD0/contacts/poly level with
completely exposed (and free of salicide) poly-gates.
This is an example of a specimen that is ready for
choline etching. The remaining poly thickness is
estimated as ~100-120 nm. Etch temperatures 34°C,
55°C, and 92°C have been tried. Accordingly to the
data obtained from p-doped bulk silicon etching, the
etch rates for these temperatures should be ~10
nm/min, ~50 nm/min, and ~400 nm/min, respectively.
The best etching results were found at 55°C. At 34°C,
the etching is too slow. Alternatively, heating the
choline hydroxide aqueous solution above 90°C
results in a change in choline concentration: it looses
water and intensively consumes CO2 from the
atmosphere. The process becomes too fast and
uncontrollable under these conditions. In additional,
etching selectivity decreases with the etch
contacts
n
n
poly
p
Figure 5: A SEM micrograph of SRAM cells
prepared for choline hydroxide etching.
5
GOX
exposed
remaining ppoly
Figure 6: A SEM micrograph of an SRAM structure
after 2 minutes of etching.
Figure 9: A SEM micrograph of an SRAM structure
after 8 minutes of etching.
Conclusion
This paper presents the novel technique for FS gate
oxide exposure using choline hydroxide. The
technique is based on the extremely high silicon to
SiO2 etch selectivity of choline hydroxide. The
Si:SiO2 selectivity reaches 10,000 at room
temperature, and decreases gradually to 5000 with the
temperature increase to 92°C.
Etching in choline hydroxide considerably degrades
the Si surface quality, if applied to initially rough and
unpolished surface. However, the etching causes
minimal degradation to previously polished Si
surfaces. This fact, together with the superior Si/SiO2
selectivity, and good process controllability, makes
choline hydroxide a promising process for MEMS
production.
Figure 7: A SEM micrograph of an SRAM structure
after 4 minutes of etching.
Etching conditions, which allow the simultaneous
etching of n-doped and p-doped poly-silicon and
reliable gate oxide exposure, fit for subsequent SEM
inspection have been found.
The regime of post-etching specimens cleaning which
enables the subsequent SEM inspection has been
elaborated.
Figure 8: A SEM micrograph of an SRAM structure
after 6 minutes of etching.
The method has been successfully used for failure
analysis of Intel’s integrated circuit components.
Figure 10 shows a SEM micrograph of a real gate
oxide defect in a CMOS component, which was
exposed using the proposed technique.
6
Side Approach, ISTFA 91 Proceedings, 225-229
(1991)
Figure 10: A SEM micrograph of a real gate oxide
defect exposed using choline hydroxide etch.
Acknowledgements
The author is grateful to Dr. Michael Lisiansky,
Victor Sidorov and Dr. Yuval Greenzweig for helpful
discussions.
7.
J. Tsaur, Chen-Hsun Du and C. Lee,
Investigation of TMAH for Front-Side Bulk
Micromachining process from Manufacturing
Aspect, Sensors and Actuators A92, 375-383
(2001)
8.
E. Steinsland, M. Nese, A. Hanneborg, R. W.
Bernstein, H. Sandmo and G. Kittilsland, Boron
Etch-Stop in TMAH Solution, Sensors and
Actuators A54, 728-732 (1996)
9.
H. Tanaka, K. Inoue, Y. Abe, T. Yoneyama,
J.Ishikawa and O. Takenaka, Effect of Small
Amount of Impurities on Etching of Silicon in
Aqueous Potassium Hydroxide Solutions,
Sensors and Actuators, 82, 270-273 (2000)
10. T.A. Kwa and R.F. Wolffenbuttel, Effect of
Solution Contamination on Etched Silicon
Surfaces, J. Micromech. Microeng., X, 5, 95-97
(1995)
The author would like to thank Dr. Ted Tessner and
Dr. Suneeta Neogi for the technical review.
11. S.A. Campbell, K. Cooper, L. Dixon, R.
Earwaker, S.N. Port, and D.J. Schiffrin,
Inhibition of Pyramid Formation in The Etching
of Si p<100> in Aqueous Potassium HydroxideIsopropanol, J. Micromech. Microeng., 5, 209218 (1995)
The author would like to express appreciation to
Anna Sierra and Shimon Dolev for technical support.
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